Issue



Table of Contents

Solid State Technology

Year 2006
Issue 4

DEPARTMENTS

Editorial


Resistance at 450mm

According to the 2005 International Technology Roadmap for Semiconductors (ITRS), the industry should plan on shifting from 300mm to 450mm wafer production by the year 2012.


News


World News


News


Technology News


News


Product News


Dfm


Encrypting process information for litho-aware OPC models

The practice of using design rules to communicate manufacturing capability to the design community failed with the advent of sub-wavelength imaging’s recommended and suggested design rules.


Nanotechnology


Low-power electrical characterization of CNTs and nanoscale devices

Manufacturers of carbon nanotubes (CNTs) or other low-power nanoscale devices continue to face challenges as potential uses for these devices grow.


Metrology


Improving 300mm wafer yield using x-ray diffraction inspection

Digital x-ray diffraction inspection of bare and patterned 300mm wafers is challenging conventional semiconductor wafer inspection systems.


Industry Forum


The essentials of single-wafer wet processing: selectivity and partnering

Chipmakers are migrating to single-wafer tools, driven by the need for highly reliable processes that can meet the stringent performance and throughput requirements of state-of-the-art fabs.


FEATURES

Cover Article


Optimizing SU-8 resist to fabricate micro-metallic structures

Conventional precision engineering technologies are reaching their limits concerning minimum feature size and precision demands, so alternative technologies, such as LIGA (from the German acronym: lithographie, galvanik, abformung), gain importance [1].


Mems


MEMS applications using diamond thin films

Diamond thin film offers advantages over silicon and other thin-film materials used in micro- and nanofabrication.


Mask Cleaning


Removing sub-50nm particles during blank substrate cleaning

The current International Technology Roadmap for Semiconductors (ITRS) requires that all defects ≥32nm on the EUV mask blank and ≥27nm on EUV substrates (i.e., mask blank before the multilayer [ML] coating) be removed by 2010.


Next Generation Processe


Implant process modifications for suppressing WPE

The threshold voltages of CMOS transistors can vary significantly depending on their proximity to an implant well boundary.


Nanotechnology


Creating metal and nonmetal nanosystems using conductive jettable inks

There is a great deal of interest in the development of ink-jettable systems for RFID tags and other types of interconnection.