Issue

Despite the compelling agendas put forth in the current adminsitration’s American Competitiveness Initiative, as well as in the National Academies’ Rising Above the Gathering Storm report and the Council on Competitiveness’s Innovate America report, Congress adjourned last year without passing the widely acclaimed National Competitiveness Investment Act of 2006 (NCIA).

Market conditions for NOR flash memory weren’t as harsh in 2006 as they were in 2005, but it was still no picnic with ASP getting pummeled, especially in the mobile phone sector, according to data from iSuppli Corp.

Progress in water immersion exposure technology since last year’s SPIE Advanced Lithography Symposium has been so convincing that its insertion into manufacturing at the 55nm and 45nm generations (as reported by Toshiba, STMicroelectronics, and others) is not likely to be interrupted.

More energy from sunlight hits the Earth in just one hour than the vast amount of energy consumed by all humans in an entire year.

Advanced transistors: Last of three partsAfter years of struggling to delay the inevitable, it is clear that a replacement for the traditional oxide/polysilicon gate stack is needed, and sooner rather than later.

One of the main contributors to cycle time is the impact of tool-measurement interrupts due to nonoptimal recipe creation.

Today’s analog systems (PCS, Bluetooth, WLAN) have turned to a mixed-signal system-in-package (SiP) that requires specialty foundries providing advanced analog CMOS-based process technologies for better cost, performance, and time to market than a system-on-chip (SoC).

The tectonic plates beneath the semiconductor industry are shifting faster and more extensively than ever before.

Many power devices rely on a silicon trench technology for operation. This article discusses the importance of trench depth control, provides examples of various trench etch applications, and evaluates a technique for in situ depth monitoring.

Engineered arrays of micron-sized scattering pixels, written inside the fused silica mask substrate by a femtosecond pulsed laser, can selectively alter the effective illumination locally, correcting for CD variations at the wafer to a fraction of a nanometer.

The primary problem with committing to today’s nanometer DFM solutions is the lack of understanding of the net benefit provided by this new generation of EDA tools.

Chrome-less phase lithography (CPL) technology was introduced as a potential strong resolution enhancement technology (RET) for the application to 90 and 65nm node logic gate layers.