Table of Contents
Solid State Technology
Year 2004
Issue 9
 | DEPARTMENTS
Editorial
If China's dicey, why not
It seems like all the semiconductor industry can think about these days is China.
World News
World News
Tech News
Technology News
Feol
A need for reassessing risk management in reticle handling
For many years, the International Technology Roadmap for Semiconductors (ITRS) has provided guidance to the semiconductor industry about technical problems facing future technology nodes that are defined according to circuit feature dimensions
Interconnect
Yield improvement by defect reduction in metal and via module cleans
In wafer cleaning, a series of tradeoffs always exists — balancing chemical cost, process throughput, and removal efficiency vs. particle redeposition, wafer surface alteration, and potential etching of the exposed thin films.
Tap
ECTC: Focus on integration
One focus at this year's Electronic Components and Technology Conference (ECTC) was highly integrated components and structures, with leading researchers taking this beyond the integrated passives that are becoming more common.
Product News
Product News
Perspectives
The industry goes back to school
It's no secret that school children in the US are not embracing careers in science, math, or engineering.
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ATTENDEES-CHOICE-AWARDS
Attendees Choose Best In
Attendees choose 'best-in-show' products
Solid State Technology invited Semicon West attendees to vote on the best products they saw at the trade show, which took place from July 12–14 at San Francisco's Moscone Convention Center and July 14–16 at the San Jose Convention Center.
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FEATURES
Advanced Process Control
Making the move to fab-wide APC
Major efforts are underway to move semiconductor manufacturing to fab-wide solutions for advanced process control after initial deployment, which was primarily aimed at greater control over single process steps and certain tool sets.
Contamination Control
Using re-association kinetics to identify impurities in p-type silicon
A new approach to in-line monitoring of impurities that pair with boron in p-type silicon is based on recombination lifetime measurements performed by a commercially available surface-charge profiler tool.
Photomasks
Model-based RET using interference maps, algorithms for random contacts at 65nm
Wafer-exposure imaging conditions and interference maps are employed by a novel model-based approach for optimum placement of resolution enhancement features on subwavelength photomasks.
Mems
Hybrid silicon-on-insulator micromachining for critical MEMS components
Researchers have developed a new fabrication process using SOI wafers as the starting substrate in surface micromachining.
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DATA-STORAGE-SUPPLEMENT
Editorial
Thanks for the memories...
Integrated circuit technology is sometimes considered the greatest triumph of industrial technology, spawning an electronics revolution.
Features
Using an atom probe microscope to characterize read heads
The accurate characterization and control of buried interfaces is increasingly important to manufacturers of devices at the nanoscale.
Features
Structure and performance of TGMR heads for next-generation HDDs
This article will provide a general view and the current status of the new tunneling magnetoresistive technology to achieve recording performance suitable for next-generation hard disk-drive (HDD) products.
Features
Processing considerations for CMP on thin-film head wafers
As critical dimensions (CDs) in thin-film magnetic read/write heads have become smaller, chemical mechanical planarization (CMP) processes have become more critical to overall manufacturing-process performance.
Features
Hard disk-drive technology revolutionizes processing
This article reviews trends in magnetic hard disk drive (HDD) technology and discusses underlying magnetoresistive phenomena, magnetic media materials issues, and processes for fabricating leading-edge write and read heads for state-of-the-art HDDs.
Features
New memory materials will enable future 'untethered' electronics
Growing uneasiness over the ability to continue shrinking existing CMOS memory cells and the push toward portable electronics are helping to foster R&D on new memory technologies.
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