Issue

Makers of advanced microchips have been doing a magnificent job of bringing 300mm wafer fabs on stream and ramping to even better yields than they had hoped for as they moved from 130nm to 90nm.

The push of leading-edge manufacturing technologies toward sub-0.1μm feature sizes places extreme performance demands on manufacturing processes and equipment.

Optoelectronic devices using III-V compound semiconductor materials are increasingly central to optical communications.

The ability to integrate mechanical elements with supporting electronics on a micro scale has bolstered microelectromechanical systems (MEMS) as an enabling technology, sparking interest in an impressive range of applications.

Solid State Technology asked industry execs to comment on the proliferation of DFM solutions and their integration into the product flow.

Precise interfacial layer control and film compositional control are needed to extend SiON layers with high nitrogen content for 32nm node high-performance (HP) logic devices, as well as when Hf-based films at the 65nm node are introduced for low standby-power (LSTP) logic devices.

Although stress has been used to increase carrier mobility for the past several years, its measurement and control have also proven difficult.

Integrated scatterometry will be an essential part of the monitoring and control in product manufacturing at the 65nm node and beyond.

Unexplained progressive mask defects continue to plague and puzzle semiconductor manufacturers.

Compatibility with existing design methodology dictates the continued use of planar transistors at the 45nm technology node.

Predictive diagnostics techniques are applied to networked vacuum systems in wafer-processing applications using an array of data collection, mining, and advanced analysis concepts.

The increasing demand for high-performance computers and the widespread use of more complex consumer products continue to fuel the scaling of leading-edge logic devices.

An elaborate testing methodology is used to study the impurity removal characteristics of point-of-use carbon monoxide gas purifiers.

The dual-damascene process used to create copper interconnect exhibits nonuniformities in both Cu deposition and removal rates that, if not closely controlled, result in structures of varying thickness or unwanted residual material on the wafer surface.