Issue



Table of Contents

Solid State Technology

Year 2005
Issue 6

DEPARTMENTS

Editorial


China: Threat or opportunity?

Japan was the first Asian country to challenge the US in advanced chipmaking. Subsequently, other countries around the Pacific Rim were able to follow the Japanese model to become leading chipmakers themselves - first South Korea and then Taiwan.


World News


World News


Tech News


Technology News


Tap


Stacking chip-scale packages

The practice of stacking packaged DRAMs to achieve higher-density memories has been around for decades.


Interconnect


Prospects and challenges for chip-level optical interconnects

Increasing speed and functionality in ICs place severe demands on current interconnects in terms of speed (bandwidth), power, and density.


Semicon Preview


Semicon West 2005 Preview

The 35th annual Semicon West conference and exhibition is back in one location this year - San Francisco - due to the expanded size of the Moscone Convention Center.


Semicon Preview


Product News


Perspectives


Taking nanotechnology to market

Solid State Technology asked industry experts to discuss how semiconductor companies can use what they already know to commercialize nanotechnology.


FEATURES

Cover Article


Low-temperature RTP for source/drain engineering

Relatively low-temperature rapid thermal processing offers some new alternatives for addressing the critical question of how to reduce source-drain parasitic resistance through ultralow thermal budget approaches.


Chemical Handling


Rapid and selective post-etch residue removal for Cu and low-k devices

The adoption of copper and low-k dielectrics has enabled the industry to overcome inherent limitations in aluminum and silicon dioxide materials used in IC interconnects as feature sizes and pitch spacing scale down.


Deposition


Meeting the Cu diffusion barrier challenge using ALD tungsten nitride carbide

Shrinking dimensions leave less volume for copper in interconnect structures, thereby increasing via and line resistances.


Implantation


Transistor scaling is moving implant energies lower

As transistors scale down in size, implant processes must accommodate requirements for lower energies and higher doses to improve advanced transistor performance.


Etch


Using a single-wafer spin system to prevent dielectric film peeling

The challenges associated with modern wafer processing in semiconductor manufacturing are being driven by an increase in the number of processing steps, increasing complexity of device technologies, process integration flows, and new materials incorporation.


Photoresists


Applications of spin-on hybrid BARCs for FEOL and BEOL integration

Bottom antireflective coatings (BARC) enable semiconductor manufacturers to control substrate reflectivity, improve critical dimension (CD) patterning, and increase depth of focus in high-resolution photolithography.


Photomasks


Using profilometer metrology to create a phase measurement standard

While the National Institute of Standards and Technology (NIST) has critical dimension calibration standards for photomasks, the US agency has not yet developed a standard for phase measurements.