Issue



Table of Contents

Solid State Technology

Year 2003
Issue 1

DEPARTMENTS

Editorial


The rocky road to 300mm automated factories

We've all seen the commercial with the greasy mechanic warning: "You can pay me now, or you can pay me laterU."


Letters


Monkeyshines

I enjoyed your November editorial "What will get the monkey off our back?"


World News


Chip sales rise, equipment orders still down in October

Chip sales were up month-to-month and year-to-year in October, sign of a healthy industry recovery, according to the Semiconductor Industry Association (SIA), San Jose, CA.


Tech News


One nano step toward efficient LED lighting

Engineers at Kopin Corp. (Taunton, MA) are using nanotechnology (patent pending as NanoPockets) to produce "CyberLites" — blue light-emitting diodes (LEDs) smaller than a grain of sand (Fig. 1).


Feol


Favorable results without wet chemicals in dry FEOL resist strip-clean

Engineers from LSI Logic, Gresham, OR, and Ulvac Technologies, Methuen, MA, have developed a production process eliminating sulfuric-acid hydrogen-peroxide wet cleans for post high-dose ion implantation.


Interconnect


Why we need to rethink copper low-k reliability issues

With the introduction of copper and low-k dielectric interconnects for advanced ICs, the semiconductor industry faces tremendous new challenges because reliability performance and failure mechanisms are not well understood (see figure).


Calendar


Calendar


Product News


Product News


Perspectives.html


Perspectives

SST editors ask ITRS authors about tough roadmap problems


FEATURES

Ald Special Report Where


ALD Special Report: Where's the metal?

ALD promises an exceptionally clean process technology at low temperature that could provide conformal and uniform coatings with extendibility to several nodes — for at least 10 years or more according to some (see table on p. 36 and "The market outlook" on p. 38).


High K Gate Dielectric A


High-k gate dielectric applications using ALD Hf-based oxides

The major issue and fundamental limitation for further scaling of the gate dielectric is the tunneling current's exponential increase due to the reduction in thickness.


Thermal Processing


Accurate measurements in the DUV PEB process

The chemically amplified resists employed at the 130–70nm technology nodes require post-exposure bake (PEB) steps where the photo-acid catalyst generated by the exposure renders the resist soluble in a developer solution.


Deposition


SPA plasma for sub-100nm

Plasma characteristics of a slot plane antenna plasma reactor were investigated — especially the ability of its low electron temperature and high plasma density to achieve damage-free processes.


Automation Robotics


OCR strategy for successful 100% single-wafer tracking

Single-wafer tracking in combination with randomizing, which is essential for yield analysis, requires a wafer-ID read at many different process steps.