Issue

Winning isn't easy in the tough, rapidly evolving semiconductor market. Many of the new applications call for specialized chips to maximize performance and minimize space and power requirements.

Flip chip technology has already expanded in two major areas: one driven by the high performance needs of microprocessor, ASIC, and high-end DSP devices, the other driven by form factor, where die sizes are small and packaging cost must be as minimal as the package itself.

Worldwide Highlights; USA; Japan; Europe; Asia Pacific...

Attendees of a worldwide workshop on "intrinsic birefringence" in CaF₂ — a key material for future 157nm lithography — agreed that this phenomenon does not constitute a showstopper. One International Sematech workshop participant at the Semicon West conference observed, however, that "the problem is worse than they are admitting...

What a year! Soaring sales, unprecedented expansion, and a seemingly infinite tech-driven economy gave Semicon West a party atmosphere, full of hope, optimism, and plans for future prosperity. The year, unfortunately, was 2000.

RTP system for 300mm by Axcelis Technologies Inc., Beverly, MA; Litho cluster for wafer level packaging by Karl Suss, Munich, Germany; Submicron prober by MFI Technologies, San Jose, CA; Point-of-use pump by Alcatel Vacuum Technology/Applied Materials Inc., Annecy, France...

A listing of industry events, covering September to November 2001.

To evaluate the efficacy of various resolution enhancement techniques (RETs), a method is proposed that gathers aerial intensity images from real masks under actual illumination conditions. Correlations to wafer-generated process latitudes are then established.

To reexamine the optimal insertion points for OPC and PSM, pattern data are manipulated and presented both in the context of the litho/design flows and as a set of transformations between discrete states. Although OPC retains its insertion point at layout verification, PSM represents a more complicated situation.

Only when both ion implantation and rapid thermal annealing are tightly controlled can successful ultrashallow junction production be performed. An implanter's sensitivities are to dose variation, energy, and elemental contamination. These can be controlled with advanced software-driven control systems, precision power supplies, and accurately designed beamline geometry.

n current magnetic recording media the signal-to-noise ratio needed for high-density recording is achieved by statistically averaging a large number of weakly interacting magnetic grains per recorded bit. Traditional engineering of magnetic media to achieve higher recording densities involves reducing the grain diameter and film thickness, but this approach is increasingly limited by instabilities due to thermal fluctuations.

The measurement and control of optical lens contamination by airborne molecular contaminants has not received much attention. To control and enhance light throughput, the universal solution is to purge optical parts with ultra-high-purity gases [1].

CMP is considered the biggest process challenge for the new generation of copper-based chips. Problems that arise here ultimately affect chip performance. However, chip manufacturers can significantly improve results by optimizing pre- and post-CMP steps. This article looks at copper CMP in the context of the entire interconnect process flow, examining steps that can be taken to make CMP easier in next-generation device processing.

Today, we are basically without good baselines and specifications for the quality of air in cleanrooms. Most fab engineers do not know the level, type, or quantity of contaminants that exist in their cleanrooms or what these should be by product type.

As transistor scaling extends below the 0.18?m technology node, propagation delays associated with interconnects begin to bottleneck the operating speeds of transistors. New interconnect materials are needed to reduce the RC time constant associated with the delays.

Cu/low-k interconnect technology has become a critical technology for 0.1µm and sub-0.1µm IC device manufacturing due to the increased device speed, enhanced electromigration resistance, and improved scalability it affords.

During full production, tight process control becomes the priority. With the move to copper, each step must be optimized to maintain high yields. The addition of 300mm increases the cost of process excursions; a finished 300mm wafer is expected to be 1.5 times as expensive as a comparable 200mm wafer [1, 2].

The explosion in Internet usage and wireless communications has driven an unparalleled demand for cost-competitive, high-performance computing, communications, and information technology products. The challenge for the semiconductor industry in meeting this hunger for new and more sophisticated products is to bring new technologies into high-volume manufacturing in the shortest time and with the minimum development and manufacturing costs.