Issue

It's Semicon West time again, when the whole semiconductor device fabrication industry gets together to see what's new. And what is new this year? The answer: virtually everything.

A lissting of industry events, covering July to December 2001.

Lithography process design and optimization; CMP system for 300mm; Single-wafer wet cleaners and processors; Fully automatic 300mm die attach system...

In the article "Newly defined limit provides a key to future developments in microelectronics" (April 2001, p. 36), it is stated that some researchers at the Georgia Institute of Technology have determined a new fundamental limit that defines a minimum (activation) energy for a statistical process (of a binary switch)...

The North American book-to-bill ratio saw historic numbers in April — unfortunately, they were a new low. The ratio dropped to 0.42 for the month of April, according to Semi, which also revised its March book-to-bill ratio to 0.59, down from 0.64...

Semiconductor startup Ziptronix Inc., Research Triangle Park, NC, has developed a revolutionary and widely applicable 3-D wafer-scale integration and interconnect technology that allows for stacking fabrics...

System chip technology has hit a wall, and so has the system chip business. Indeed, some wonder if system chips may turn out to be just a niche market. Improving process technology usually means chip performance/unit cost roughly doubles every year, but the system chip has fallen off this curve.

Lambda Physik and Jenoptik form joint venture; Despite slowdown, European equipment suppliers buoyant.

While the concept of system-on-a-chip (SoC) has been around for a decade, it is only now that software tools and semiconductor processing have advanced to where SoC is accessible to more than the largest design teams. In the past, a SoC project needed 20-100 or more engineers and programmers, supported by an array of a dozen or so million dollar electronic design automation (EDA) tools. This level of expense and capital investment demands a continuous series of SoC projects, and a substantial in

What's the smart way to pay for intellectual property (IP) at the top of the semiconductor food chain? One concept is a percentage of profit-impact for the customer — some portion of a measured outcome surpassing normal. This is what we have called "gainsharing."

A yet unheralded alternative for future lithography, step-and-flash imprint lithography, appears to be an inexpensive method for pattern generation capable of sub-100nm resolution on silicon wafers.

The vacuum performance of any processing tool is critically determined by a number of factors, including the design of the processing chambers, the selection, configuration and operating techniques for pumping and, of course, the process itself.

In new generations of semiconductor devices, the composition of silicon-based epitaxial films becomes increasingly more complex, with the addition of not only dopants such as boron, arsenic, or phosphorus, but also germanium and, in some cases, carbon.

The 2000 International Technology Roadmap for Semiconductors has identified the production requirements of low-k dielectrics extending over three device generations. The question facing the industry is "What is the best method for depositing low-k films: spin-on or CVD?"

HF-ozone cleaning chemistry can perform the same functions as a conventional four-chem clean — organic removal, particle removal, chemical-oxide strip and regeneration, and metal contamination removal. This process chemistry also reduces cycle time and requires significantly less complex hardware.

Changes in semiconductor manufacturing accompanying the move to 300mm wafers and the continual shrinkage of critical dimensions are placing new demands on essentially all fab systems. In particular, connections between the MES, the transport system, the equipment integration systems, and the scheduler must become more robust and rich.

With 300mm wafer processing, expect to see a shift from conventional proximity aligners to more applications of 1x steppers for backend bump processing. While passé for leading-edge frontend applications, 1x steppers provide clear advantages for semiconductor manufacturing's backend, in cost of ownership, automation, and processing.

With increasing demand for high-performance optical and communications devices, the drive for mass fabrication of III-V components is forcing many manufacturers to examine the limits of their processing technology.

Since the early 1960s, the use of high-pressure, specialty gases in semiconductor manufacturing has significantly contributed to the rapid evolution of integrated circuit technology. Compressed gas cylinders typically contain pressures up to 2500 psig.e

Spectroscopic ellipsometry has been the technique of choice to characterize thin films and multilayers in semiconductor manufacturing. Extending this technology into the vacuum ultraviolet range, down to 140nm, however, for emerging 157nm optical lithography applications, requires an environment that avoids the absorbing effects of oxygen and water vapor below the 190nm wavelength; these must be reduced to the parts/million range.

A new nondestructive elastic probe technology enables semiconductor manufacturers to conduct advanced electrical testing on product wafers at production speeds. The cost savings can be enormous, and the accuracy and flexibility of the technology facilitate continued miniaturization.

Perfluorocompounds (PFCs) are some of the most chemically inert substances known [1, 2]. Examples of these compounds include CF₄ and C₂F₆, which are employed during dry chemical etching and chamber cleaning operations in the manufacture of semiconductor devices.

In IC fabrication, the polysilicon ("poly") layer is one of the critical layers that influence chip yield (Fig. 1). Gate patterns, in particular, require tight critical dimension (CD) control because the gate CD determines the gate length of a MOS transistor, hence transistor characteristics such as drive current and switching speed. On the other hand, poly interconnect CDs are less determinant of chip performance.