Issue

Studs Terkel, outstanding American historian and radio interviewer, would sometimes end his broadcasts by exhorting listeners to "Put all your eggs in one basketellipseand then guard that basket!"

July's Solid State Technology carried an article "Simplified Interconnect Processing for Cost-Sensitive Chips" (p. 99), in which Seiko Epson Corp. describes the economic benefits of Flowfill's self-planarizing dielectric layer (requiring no CMP) and its integration into a 0.25µm, three-metal-level consumer IC.*

Market researchers see boom in 2001. Two new forecasts for the semiconductor equipment market suggest that while some improvement is being seen now, there will be no full-boom period until late 2000 or 2001. Re searchers Dataquest, San Jose, CA, and The Information Network, New Tripoli, PA, both see restrained capital spending over the next 18 months with continued excess DRAM capacity; the latter firm expects a short-lived recovery in equipment bookings in the next few quarters. Dataques

Etec Systems Inc., Hayward, CA, will develop multicolumn electron beam equipment for both mask production and direct write-to-wafer applications under a $14.2 million contract from the Defense Advanced Research Projects Agency through the Space and Naval Warfare Systems Center.

IMEC, the microelectronics research consortium based in Leuven, Belgium, has developed a dedicated, nonvolatile memory cell that is compatible with standard 0.35µm CMOS processes. The patented HIMOS (High Injection MOS) cell, based on source-side injection, offers very high programming speeds at moderate voltages and power consumption, with low development entry cost, leading to a truly embedded memory processing module that can be combined with any standard CMOS process.

When the big get bigger, the small get nervous. That's the case for Taiwan's chipmakers currently negotiating the establishment of a semiconductor equipment and materials research consortium.

In a recent market study of the use of low-dielectric-constant (low-k) materials for interlayer dielectrics (ILDs), we assessed the semiconductor industry's transition from the workhorse dielectric silicon dioxide (SiO2), through fluorinated silicon oxyfluoride (FSG) and hydrogen silsesquioxane (HSQ), to spin-on organic materials and inorganic systems deposited by chemical vapor deposition (CVD). Our findings are based on interviews with suppliers and potential suppliers of low-k materials,

A newly expanded web site allows visitors to purchase a range of gases manufactured to match specific performance requirements for all major brands of lab instruments. Included on the site are TechniMate high-purity lab instrument support gases, SCOTTY transportable products, and equipment items. The site also features an on-line quoting system that provides customers with prices on pure gases, mixtures, and custom products within two hours. Scott Specialty Gases, Plumsteadville, PA; ph 215/7

Wafer temperature is one of the hidden parameters in plasma etching that has a significant impact on process results and can cause variation between presumably identical process tools. Many conventional measurement techniques have limited sensitivity, but there is a new tech nology for in situ direct monitoring. It has provided new insights into plasma process behavior and identified process parameters that affect wafer temperature.

Here is a proven method for bumping singulated die using wire bonding. It enables cost-effective evaluation and entry into flip-chip applications.

While a focus on overall equipment effectiveness has been in place for some time, the new drive will be toward achieving it through system simplification, new throughput enhancements, and increased reliability. System simplification will be applied directly to fluid delivery systems and those logistical systems that support them. This trend is further supported by the move to 300mm wafers, which will cause a focus on simpler delivery systems that are cheaper and carry lower cost of ownership (CO

The integrated fab approach to gas management is now being extended to include vacuum and abatement solutions through sophisticated software modeling. The benefits of full integration of principal fab facilities include lower costs in fab construction and operations; improved environmental, safety, and handling results; faster execution of new fab construction; and the ability to address unique tool process needs that are enhanced with guarantees of total gas, chemical, and vacuum system perform

Plasma doping is the leading candidate to replace today's beam-line ion implantation, which is being pushed to the limit by the need for ultra-shallow junctions. Cluster-compatible hardware is envisioned to provide simpler, more economical, higher-throughput wafer processing. Part one of this article, in the September issue of SST, reviewed the status of plasma doping, cited device data, and touched on process and equipment issues. Part two discusses potential problems, including charge dama

In semiconductor fabrication, a polymeric stress buffer layer between the IC final passivation layer and plastic molding compound interface is often required to protect the delicate layers of oxide and circuitry on the silicon surface from the stresses induced by the molding compound during operation of the chip. The stress buffer or overcoat is applied and patterned as the last step in traditional wafer fabrication. The coating also affords protection to the wafer during subsequent backgrinding

A key factor in the race to increasing export markets in recent years has been the emergence of advanced technologies, often from innovative new companies, which rapidly escalate the growth of new industry. Until recently, however, there have been very few high-tech start-ups in Europe. In the US, by contrast, the emphasis on technology has played a significant role in fueling the economic engine, as evidenced by the $11.4 billion invested by the US venture capital (VC) industry in the first hal

While CMOS silicon-on-insulator clearly results in improvements in device physics and electrical parasitics, its application has to address issues associated with using this material substrate, including changes, although minor, to several wafer fabrication processes and modified CAD tools. Manufacturers pursuing this route need to ask: Are the added R&D costs and the overall improvement in performance cost effective compared to standard bulk-silicon or epitaxial-based VLSI CMOS technology?