Packaging edges into the spotlight
09/01/2007
At last, the importance of MEMS packaging and interconnection has gained recognition.
BY RANDY FRANK
The minute details of intricate microelectromechanical systems (MEMS) structures and what they can accomplish have always provided intrigue-intrigue that has overshadowed the niggling but important issue of production packaging. In fact, packaging has proven to be one of the technology’s greatest limitations.
Inspired by the prospect of substantial cost savings, though, start-ups and even established MEMS suppliers have recently taken on the packaging challenge. The advancements they’ve made could lead to greater acceptance of MEMS devices.
Packaging legacy
Depending on the MEMS device, packaging approaches can vary widely between MEMS devices exposed to the environment (such as pressure sensors) and those isolated from the environment (such as accelerometers and RF MEMS). Micro-optoelectromechanical systems (MOEMS), bioMEMS, and MEMS actuators all have their own unique packaging issues. In fact, the International Technology Roadmap for Semiconductors (ITRS) (www.itrs.net/Links/2006Update/FinalToPost/11_AP2006UPDATE.pdf, page 12) identifies unique packaging requirements and potential direction for RF, bio, inertial, and optical MEMS. This degree of planning for MEMS packaging is new-and welcome.
In many respects, MEMS packaging has not been a part of the up-front design process. At least that’s how it would appear to an outsider noting the placement of a state-of-the-art structure into a metal can or ceramic package that was designed 20 or more years earlier. According to the Micro and Nanotechnology Commercialization Education Foundation’s (MANCEF) Second Edition of International Micro-Nano Roadmap (www.mancef.org
oadmap2.htm), “Packaging was an afterthought for most MEMS designers and manufacturers only a few years ago.” Consequently, packaging has been attributed to be as high as 70% of the total cost of a MEMS device. Based on its unfair share of the cost, greater attention is now being directed at packaging. In fact, packaging is receiving greater research and development focus as a key enabler for microsystems commercialization.
Eric Mounier, project manager for MEMS and optoelectronics at market research firm Yole Developpement (www.yole.fr), confirms packaging’s high percentage of the total MEMS cost. “Today MEMS packaging is very expensive. That is why most MEMS companies have moved away from die-level packaging to wafer level packaging (WLP),” he says. “Texas Instruments, for example, is currently investigating WLP for its DLP chip.”
One of the major factors impacting the direction of MEMS technology, including packaging, is an evolving business model. “Ten years ago, the business model that most start-up MEMS companies had was ‘we will build a factory,’ ” says Roger Grace, president of Roger Grace Associates (www.rgrace.com) as well as past president and co-founder of MANCEF. “What we are seeing now is that the MEMS industry has basically adopted the same strategy as the semiconductor industry and many of the newest companies are fabless, which makes them more dependent on the infrastructure.”
As a result of this increasing dependency on outside contractors for production expertise, packaging has relied on standards from microelectronics manufacturing and has taken advantage of new MEMS-specific approaches developed by companies providing a new MEMS infrastructure.
Riding on CMOS
MEMS packaging for high-volume consumer applications-such as the low-cost time-reference market currently dominated by quartz crystals and imaging stabilization for cameras in cell phones-requires a departure from the traditional approaches. Taking advantage of the cost-effectiveness and broad availability of CMOS processing technology, some start-ups have developed packaging techniques to use the CMOS process without requiring any modifications. Two companies, InvenSense and SiTime, take similar, yet different, approaches.
InvenSense’s (www.invensense.com) MEMS gyroscope uses a bulk micromachined structure. “Basically the whole concept here is integrating bulk silicon MEMS with the CMOS directly,” says Steven Nasiri, CEO and founder (in 2003) of InvenSense. A patented process allows InvenSense to reduce the size and cost of the MEMS gyro to meet the requirements of consumer applications.
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“What you are looking at is almost like engineered SOI with a bunch of micromachining on the wafer,” says Nasiri. Part of the micromachining on the top of that engineered SOI (silicon on insulator) wafer is a seal ring and electrical interconnect posts. When this wafer mates to the CMOS, it simultaneously creates a hermetic seal by bonding the MEMS directly to the aluminum of the CMOS. It also creates the electrical interconnects between the MEMS and the aluminum. The layer of material on top of the bulk silicon establishes a eutectic bond to the CMOS.
“In our case, electronics and the MEMS, everything hermetically sealed at the wafer level, 90% of my cost is done,” says Nasiri. “Assembly and test is 10% to 15% of the cost.” This allows the use of low-cost plastic packaging.
Another key part of the whole technology is a very small sealing area. “We are taking advantage of the multi-layer metal that already comes to us free in the CMOS,” says Nasiri.
Using the MEMS First process developed and patented by Robert Bosch, SiTime (www.sitime.com), founded in 2004, creates a small, low-cost MEMS-based replacement for quartz crystals. In SiTime’s device, deep reactive ion etching (DRIE) defines the beam structure for the resonator and creates isolation for the electrical path to electrostatically drive the structure and sense the capacitance.
Instead of a separate bulk micromachined cover that would increase the MEMS device size by 200% or more, a silicon cap grown over the resonator structure provides its hermetic seal. Vias cut through the cap silicon form electrical contacts to the resonator’s drive and sense electrodes. The complete MEMS portion is manufactured by Jazz Semiconductor. “They do all of the MEMS fabrication, including the deep reactive ion etching, sacrificial etch release, the encapsulation of the silicon, and so on,” says Joe Brown, head of strategic alliances for SiTime.
The oscillator, temperature sensor, and temperature compensation circuitry are manufactured on a standard 200mm CMOS wafer line. Carsem, SiTime’s assembly and test partner, performs the piggyback assembly of the MEMS resonator to the CMOS oscillator chip treating the sealed structure just like a semiconductor.
From a single step to a complete solution
Some packaging advancements address a single processing step. This is the case with Applied MicroStructures Inc. Historically, surface modification using self-assembled monolayers is usually performed in a liquid phase. Founded in 2003, Applied MicroStructures (www.appliedmst.com) applies these materials in a gaseous vapor state called Molecular Vapor Deposition (MVD), which allows the growth of ultra-thin films with a wide range of properties in a high-volume process.
“It is a surface reaction, so it is 100% conformal,” says Jeffrey Chinn, president and CEO of Applied MicroStructures. “Any hidden crevice on an atomic scale will be coated.” Because of surface tension and capillary forces, a liquid phase deposition cannot be controlled nearly as well as the gaseous state process. The transition follows the semiconductor industry’s move from liquid to gaseous phase processing. The thin monolayer coatings provide a passivation, lubricant, or anti-stiction layer for MEMS devices.
 The DRIE-defined structure in SiTime’s timing reference gets a silicon cap at the wafer level before being merged with a CMOS structure in its QFN package. |
When you require a volume of 10,000 units or less, dedicated automated assembly can pose a serious problem. In contrast to addressing a single processing step, for such sensor applications the Bennington Microtechnology Center (BMC) (www.benningtonmicro.org) provides a complete packaging solution. Founded in 2004, BMC works closely with the University of Texas at Arlington’s Automation & Robotics Research Institute (http://arri.uta.edu) to implement production-ready approaches from R&D.
According to Henry Klim, executive director of BMC, his company addresses lower volume units with a modular platform approach. With its M3 (macro-meso-micro) design methodology, the same process used for initial prototypes can take the product into volume production. The easily reconfigurable approach handles a variety of packages.
Addressing the fragmentation in the MEMS market requires BMC to use more than a single tool suite. “Because we have to reconfigure our assets all the time, we refer to it as knowledge intensive manufacturing as opposed to the more labor-intensive manufacturing where you push the button and everything is automated,” says Harry Stephanou, professor and director, Automation & Robotics Research Institute at the University of Texas at Arlington.
Revising the packaging infrastructure
From a single process step to a complete system, MEMS packaging has industry support at several levels in between as well. For example, Panasonic’s MIPTEC (Microscopic Integrated Processing Technology) approach to 3D packaging (http://miptec.net/e/) integrates multiple chips and functions into a single very small package. In addition to other products, the technology has been applied to MEMS sensors.
Vectra liquid crystal polymer (www.ticona.com
edesign/products/vectra_cp) from Ticona, and proprietary epoxies from RJR Polymers (www.rjrpolymers.com) have enabled the development of air-cavity packaging to replace ceramic and metal packages. The low-cost protection from environmental and mechanical stresses these approaches afford can benefit MEMS devices among other products.
At the wafer level, IMEC (www.imec.be), an independent research center, is developing a range of 3D packages that could benefit MEMS companies in the future. In addition to 3D system-in-a-package based on the classic packaging infrastructure, the company is addressing 3D wafer-level-packaging based on the emerging wafer-level-packaging infrastructure and 3D stacked IC based on foundry-level 3D technology.
 A multiscale robotic assembly and packaging system in Bennington Microtechnology Center provides a macro, meso, and micro, or M3 level packaging platform. |
For vacuum-sealed wafer-level packages, Innovative Micro Technology’s (IMT’s) getter deposition services could provide a key process step. In its Class 100 cleanroom, IMT has achieved vacuum levels below 10mTorr in the production of inorganic devices. The getter deposition services are performed on 150mm or smaller wafers.
With MEMS packaging as part of the ITRS and MANCEF road maps, it is no surprise that other organizations have recognized the importance and dedicated resources to this area. ASM International has developed a MEMS materials database (www.asminternational.org/mems) specifically for packaging. The online resource allows users to navigate through generic and specific materials, as well as case studies, processes, producers, and more.
Coming attractions
For high-volume MEMS production situations, individual companies can justify a significant packaging investment in proprietary processes. For other applications that do not have high-volume consumer potential, a more generic approach to packaging technology could provide the solution. Researchers at the University of Michigan are actively working on these types of process capabilities.
Khalil Najafi, professor in the Wireless Integrated MicroSystems area in the U of M’s Department of Electrical Engineering and Computer Science says one of the key interests is performing vacuum or hermetic packaging at the wafer level-and doing it at low cost. He notes that the IC industry performs low-temperature metal-to-metal bonding, but it is very difficult to get those approaches to work for MEMS hermetic and vacuum packaging. “If you can develop techniques that work down at 200°C, that would be very good for most applications,” says Najafi.
“We are working on different solder type technologies that allow you to do basically vacuum-type seals, but at the same time, let you get good reliable bonds.” Based on development funding from the U.S. Defense Advanced Research Projects Agency (DARPA) as part of the Harsh Environment Robust Micromechanical Technology (HERMIT) program, some of these techniques could be available soon.
MEMS actually has the potential to serve as an interconnect technology for nano assembly. According to ARRI’s Stephanou, the nanomanufacturing community is increasingly realizing that it will not be able to rely solely on bottom-up device manufacture. He says some top-down robotics methodology will be needed. Combined with some of the research being done in universities at the nanoscale, BMC’s M3 approach could be taken to even smaller structures (e.g., to manipulate nanowires). “Having the ability to manipulate precisely in 3D could have quite a bit of impact on interconnects whether it’s thermal dissipation or electrical interconnects,” says Stephanou.