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By Dr. Jeongdong Choe, Senior Technical Fellow, TechInsights

There has been a great deal of speculation around the composition of Intel’s Optane™ XPoint memory technology: PCM or ReRAM, selector, layouts, patterning technology, technology node, multi-stacked cell structure, die floor plan, interconnection to each electrode (wordlines and bitlines), functional blocks, scalability and process integration.

TechInsights set about to find answers. We have analyzed Optane’s memory cell structure, materials, cell array and memory peripheral array design, layouts, process flow and circuitry. Our Advanced CMOS Essential (ACE) analyses on Intel’s XPoint memory presents our complete findings and market trend predictions. The following paragraphs present some of the highlights.

Intel XPoint memory is based on PCM and selector memory (storage) cell elements. GST-based PCM, Ge-Se-As-Si based Ovonic Threshold Switch (OTS) and two memory cell stacked array architecture are common across Intel’s and Micron’s XPoint technologies.

We examined effective memory cell area efficiency vs. memory array efficiency, and compared it to current DRAM and NAND products. In our previous analysis on XPoint memory die, we found that memory density per die is 0.62 Gb/mm2 and memory efficiency is over 91%. The memory array efficiency, however, may not represent the reality because the memory peripheral and CMOS circuitry cover most of the die area.

We can define the effective cell area efficiency as a ratio of the real area of the cell memory elements (storage) to the total die area. For example, the effective memory cell area efficiency on Toshiba 15 nm 2D planar NAND is 43.9% due to excluding BC, CSL, SSL, GSL dummy wordlines and peripheral area on a die, while memory array efficiency is 72%. Figure 1 shows comparison of the effective memory cell area efficiency for 2D/3D NAND products from Toshiba/SanDisk (Western Digital), Micron/Intel, SK Hynix and Samsung, and 3D XPoint (OptaneTM from Intel).

Figure 1. A comparison of effective memory cell area efficiency on 2D/3D NAND and XPoint memory

Figure 1. A comparison of effective memory cell area efficiency on 2D/3D NAND and XPoint memory

When it comes to the effective unit cell size per 1 bit, NAND flash devices have been scaled down from 2D NAND (320 nm2) to 48L 3D NAND (145.8 nm2) or even to 64L 3D NAND (88.5 nm2) for Toshiba NAND products, while Intel OptaneTM two cell stacked XPoint memory has 800 nm2 (effectively 2F2) (Figure 2).

Figure 2. A comparison of effective unit cell area per bit on 2D/3D NAND and XPoint memory

Figure 2. A comparison of effective unit cell area per bit on 2D/3D NAND and XPoint memory

A comparison of memory density with DRAM products shown in Figure 3 illustrates that XPoint has higher memory density (0.62 Gb/mm2) than Samsung 1x nm (0.19 Gb/mm2), SK Hynix 2y nm (0.15 Gb/mm2) and Micron 20 nm (0.094 Gb/mm2) DRAM dice. Micron announced that the memory density of XPoint would be ten times higher than commercial DRAM products. This is true if we compare it with 30 nm class DRAM products, because most of the 30 nm class DRAM products from major DRAM manufacturers have 0.06 Gb/mm2 memory density. The first commercial XPoint memory die has three times (vs. Samsung 1x DRAM) or six times (vs. Micron 20 nm DRAM) higher memory density than those of current DRAM products.

Figure 3. A comparison of die size and memory density on DRAM (25nm/20nm/18nm) and XPoint memory

Figure 3. A comparison of die size and memory density on DRAM (25nm/20nm/18nm) and XPoint memory

We found that Intel introduced some innovative and compelling technologies on their first XPoint products such as PCM/OTS stack used for memory elements, GST based PCM, Ge-Se-As-Si based OTS and carbon based conductor and 2-bit cell stacked memory array with three electrodes. Intel successfully used a 20nm SADP double patterning technology to build a very uniform GST-based PCM/OTS memory square/island. Complete details on the of TechInsights’ XPoint memory analysis can be found here.

Click here to hear more from Dr. Choe and his TechInsights colleagues on 3D NAND.

Since the 2009 semiconductor downturn and strong 2010 recovery year, power transistor sales have been rocked by market volatility, falling in three of the last five years because of inventory corrections and drawdowns by systems makers worried about ongoing economic weakness and price erosion in some product categories. After recovering from a 7% drop in 2015, power transistor sales grew 5% in 2016 to $12.9 billion and are forecast to set a new record high this year with worldwide revenues rising 6% to $13.6 billion, according to IC Insights’ 2017 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discrete Semiconductors.

The expected 2017 growth in power transistor sales will be the first back-to-back annual increase in this semiconductor market segment in six years, and that will push dollar volumes past the current record high of $13.5 billion set in 2011. In 2012 and 2013, power transistors suffered their first back-to-back annual sales decline in more than three decades—dropping 8% and 6%, respectively—after rising 12% in 2011 and surging 44% in the 2010 recovery from the 2009 downturn year. The power transistor market then rebounded in 2014 with a strong 14% increase, only to drop 7% in 2015. In 2016, this semiconductor discretes market category began to stabilize and is expected to continue expanding at a modest rate in the next several years, based on IC Insights’ O-S-D Report forecast (Figure 1).

Power transistors are the primary growth engine in the $23 billion discrete semiconductor market because they play a vital role in controlling and conditioning electricity for all types of electronics—including a growing number of battery-operated systems. Worldwide efforts to reduce the waste of power in electric utility grids have significantly increased the importance of power transistors in consumer, commercial, and industrial systems. Renewable-energy applications (e.g., wind and solar systems) as well as electric and hybrid vehicles have also become important applications for power transistors in the last 15 years.

Figure 1

Figure 1

However, volatility in the first half of this decade resulted in an uncharacteristic drop in market size for power transistors during the last five years.  Between 2011 and 2016, power transistor sales fell by a compound annual growth rate of -0.9% compared to a 25-year historical annual average increase of 6.4% (between 1991 and 2016).  The 2017 O-S-D Report is projecting that worldwide power transistor sales will grow by a CAGR of 4.2% between 2016 and 2021, reaching $15.8 billion in the final year of the forecast.

All power transistor technology categories are expected to register sales growth in 2017 with MOS field effect transistor (FET) products increasing 6% to nearly $7.7 billion, insulated-gate bipolar transistor (IGBT) products also rising 6% to $4.1 billion, and bipolar junction transistor products growing 4% to about $875 million.  RF/microwave power transistors and module sales are forecast to rise 3% in 2017 to $960 million, according to the O-S-D Report.

Advancements in spintronics


September 25, 2017

Applications now include nanoscale Spintronics sensors that further enhance the areal density of hard disk drives, through MRAMs that are seriously being considered to replace embedded flash, static random access memories (SRAM) and at a later stage dynamic random access memories (DRAM).

BY HIDEO OHNO, MARK STILES, and BERNARD DIENY, IEEE

Spintronics is the concept of using the spin degree of freedom to control electrical current to expand the capabilities of electronic devices. Over the last 10 years’ considerable progress has been made. This progress has led to technologies ranging from some that are already commercially valuable, through promising ones currently in development, to very speculative possibilities.

Today, the most commercially important class of devices consists of magnetic sensors, which play a major role in a wide variety of applications, a particularly prominent example of which is magnetic recording. Nonvolatile memories called magnetic random access memories (MRAMs) based on magnetic tunnel junctions (MTJs), are commercial products and may develop into additional high impact applications either as standalone memories to replace other random access memories or embedded in complementary metal–oxide–semiconductor (CMOS) logic.

Some technologies have appealing capabilities that may improve sensors and magnetic memories or develop into other devices. These technologies include three- terminal devices based on different aspects of spin-transfer torques, spin-torque nano-oscillators, devices controlled by electric fields rather than currents, and devices based on magnetic skyrmions. Even further in the future are Spintronics-based applications in energy harvesting, bioinspired computing, and quantum technologies.

But before we get into detail about where Spintronics is today, we need to cover the history of Spintronics.

The history of spintronics

Spintronics dates to the 1960s and was discovered by a group at IBM headed by Leo Esaki, a Japanese physicist who would later go on to win a share of the Nobel Prize I 1973 for discovering the phenomenon of electronic tunneling. Esaki and his team conducted a study which showed an antiferromagnetic barrier of EuSe sandwiched between metal electrodes exhibits a large magnetoresistance.

Subsequent advances of semiconductor thin film deposition techniques such as molecular beam epitaxy led to the development of semiconductor quantum structures, which prompted studies of magnetic multilayers. Ensuing studies of magnetic multilayers resulted in the discovery of giant magne- toresistance (GMR) in 1988. This effect was used to make magnetic sensors, which boosted the areal density of information stored on hard disk drives and led to the 2007 Nobel Prize in Physics awarded to Albert Fert and Peter Grunberg.

Since then rapid progress has continued to enhance both the role and the potential of Spintronics. So, let’s take a look at where we are now.

Where we are now

Applications now include nanoscale Spintronics sensors that further enhance the areal density of hard disk drives, through MRAMs that are seriously being considered to replace embedded flash, static random access memories (SRAM) and at a later stage dynamic random access memories (DRAM). Applica- tions also include devices that utilize spin current and the resulting torque to make oscillators and to transmit information without current.

Now let’s look at those applications and more in-depth.

Modern Hard Disk Drives: Two breeds of Spintronics sensors have replaced traditional anisotropic magnetoresistance (AMR) sensors. Those sensors include giant magnetoresistance (GMR) sensors (used in hard disk drives between 1998 and 2004) and tunnel magnetoresistance (TMR) sensors (used since 2004).

Those sensors are part of the technology development that enabled the increase of storage density of hard disk drives by several orders of magnitude, laying the foundation of today’s information age in the form of data centers installed by the cloud computing industry.

Magnetoresistive Random Access Memory (MRAM): MRAM and particularly spin-transfer- torque MRAM (STT-MRAM) is a nonvolatile memory with very high endurance and scalability. The current STT-MRAM technology uses an array of MTJs with an easy axis of magnetization oriented out of the plane of the layers. These MTJs utilize interface perpendicular anisotropy at the CoFeB–MgO interface, along with the large TMR of the system, for reading the state of magnetization. The spin-transfer torque exerted by a spin polarized current is used to change the magneti- zation direction, offering an efficient way of rewriting the memory. FIGURE 1 show the main families of MRAM that have evolved since 1995.

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Three Terminal Magnetic Memory Devices: Recent physics developments raise the prospect of three- terminal spintronic memory devices. These devices have an advantage over the standard two-terminal devices used in memory applications such as MRAM in that separating the read and write functions poten- tially overcomes several future roadblocks in the devel- opment of MRAM. There are two writing schemes: one is based on spin currents generated by an electrical current running through a heavy metal adjacent to the free layer of the MTJ. The current causes a spin current both in the bulk of the heavy metal and at the interface; this spin current then exerts a torque, called the spin-orbit torque, on the magnetization. In this scheme, the write current does not pass through the MTJ, separating the write and read functions. The other scheme uses current-induced domain wall motion to move a domain wall in the free layer of the MTJ from one side of the fixed layer to the other. In this scheme, the current passes through the free layer, but not the tunnel barrier, again separating the read and write functions.

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing: Spintronic-based nonvolatile embedded working memory used in conjunction with CMOS-based logic applications is a crucial first step toward standby-power-free logic circuits that are much needed for Internet of Things (IoT) applications. MRAM based logic-in-memory reduces the overhead of having memory and logic apart and gives both minimized interconnection delay and nonvolatility.

Security: These devices have shown great promise for logic and memory applications due to their energy efficiency, very high write endurance, and nonvolatility. Besides, these systems gather
many entropy sources which can be advantageously used for hardware security. The spatial and temporal randomness in the magnetic system associated with complex micromagnetic configurations, the nonlinearity of magnetization dynamics, cell-to-cell process variations, or thermally induced fluctuations of magnetization can be employed to realize novel hardware security primitives such as physical unclonable functions, encryption engines, and true random number generators.

Spin-Torque and Spin-Hall Nano-Oscillators: Spin-torque nano-oscillators (STNO) and spin-Hall effect nano-oscillators (SHNO) are in a class of miniaturized and ultra-broadband microwave signal generators that are based on magnetic resonances in single or coupled magnetic thin films. These oscil- lators are based on magnetic resonances in single or combined magnetic thin films where magnetic torques are used to both excite the resonances and subsequently tune them. The torques can be either spin-transfer torques due to spin-polarized currents (STNOs) or spin Hall torques due to pure spin currents (SHNOs). These devices are auto-oscillators and so do not require any active feedback circuitry with a positive gain for their operation. The auto-oscillatory state is strongly nonlinear, causing phase– amplitude coupling, which governs a wide range of properties, including frequency tunability, modulation, injection locking, mutual synchronization, but also causes significant phase noise. STNOs and SHNOs can, in principle, operate at any frequency supported by a magnetic mode, resulting in a potential frequency range of over six orders of magnitude, from below 100 MHz for magnetic vortex gyration modes to beyond 1 THz for exchange dominated modes. Since STNOs and SHNOs can also act as tunable detectors over this frequency range, there is significant potential for novel devices and applications.

Beyond the applications listed, the spin degree of freedom is also being used to convert heat to energy through the spin Seebeck effect, to manipulate quantum states in solids for information processing and communication, and to realize biologically inspired computing. These may lead to new develop- ments in information storage, computing, communication, energy harvesting, and highly sensitive sensors. Let’s take a look at these new developments.

Thermoelectric Generation Based on Spin Seebeck Effects: The study of combined heat and spin flow, called spin caloritronics, may be used to develop more efficient thermoelectric conversion. Much of the focus of research in spin caloritronics has been the longitudinal spin Seebeck effect, which refers to spin-current generation by temperature gradients across junctions between metallic layers and magnetic layers. The generated spin current in the metallic layer gets converted into a charge current by the inverse spin Hall effect, making a two-step conversion process from a thermal gradient perpen- dicular to the interface into a charge current in the plane of the interface. This process can be used for thermoelectric conversion. Device structures using the spin Seebeck effect differ significantly from those using conventional Seebeck effects due to the orthog- onality of the thermal gradient and resulting charge current, giving different strategies for applications of the two effects.

Electric-Field Control of Spin-Orbit Interaction for Low-Power Spintronics: Control of magnetic properties through electric fields rather than currents raises the possibility of low energy magnetization reversal, which is needed for low-power electronics and Spintronics. One specific way to accomplish this low energy switching is through electric-field control of electronic states leading to modification of the magnetic anisotropy. By applying a voltage to a device, it is possible to change the anisotropy such that the magnetization rotates into a new direction. While such demonstrations of switching alone are not sufficient to make a viable device, voltage controlled reversal is a promising pathway toward low-energy nonvolatile memory devices.

Control of Spin Defects in Wide-Bandgap Semiconductors for Quantum Technologies: The spins in deep level defects found in diamond (nitrogen- vacancy center) and in silicon carbide (divacancy) have a quantum nature that manifests itself even at room temperature. These can be used as extremely sensitive nanoscale temperature, magnetic-field, and electric-field sensors. In the future, microwave, photonic, electrical, and mechanical control of these spins may lead to quantum networks and quantum transducers.

Spintronic Nanodevices for Bioinspired Computing: Bioinspired computing devices promises low-power, high-performance computing but will likely depend on devices beyond CMOS. Low-power, high performance bioinspired hardware relies on ultrahigh- density networks built out of complex processing units interlinked by tunable connections (synapses). There are several ways in which spin-torque-driven MTJs, with their multiple, tunable functionalities and CMOS compatibility, are very well adapted for this purpose. Some groups have recently proposed a variety of bioin- spired architectures that include one or several types of spin-torque nanodevices.

Skyrmion-Electronics: An Overview and Outlook: The concept of skyrmions derives from high energy physics. In magnetic systems, skyrmions are magnetic textures that can be viewed as topological objects. Theory suggests that they have properties that might make them useful objects in which to store and manip- ulate information. Many of the ideas are similar to ideas that were developed decades ago for bubble memory or, more recently, racetrack memory. There are several possible advantages for skyrmion devices as compared to other related devices. They are potentially higher density and lower energy, although the arguments for these remain to be experimentally verified.

So, what does the future of spintronics have in store?

The future

Spintronics will continue to have increasing impact, but the future is somewhat uncertain. The importance of magnetic sensors is likely to remain important while the importance of the magnetic sensors in hard disk drives appears to depend on the economics of mass storage in the cloud.

MRAM seems likely to play an increasing role both as standalone memory and embedded in CMOS. The degree of adoption still depends on a few technical and many economic considerations. The acceleration, over the past few months, of announcements and demonstrations related to STT-MRAM produced by major microelectronics companies, seems to indicate that large volume production of STT-MRAM is getting quite close. If the adoption of this technology by microelectronics industry becomes a reality, the whole field will be strongly boosted.

In the future, Spintronics can play a critical role in areas such as IoT, ultralow-power electronics, high-performance computing (HPC). Besides, in the next 10 to 15 years, we are likely to see a much greater role played by alternative forms of computing. The role that Spintronics plays in those technologies is likely to be strongly influenced by the success of MRAM. If MRAM is successful, we will have developed the ability to manufacture it making it easier to import into other technologies.

Some of the recent technical developments that have significant virtues for applications will likely play a role in technology 10 to 15 years from now but many will not. Research on many of these ideas will continue and will spawn related areas. Material research is key along this road.

Innovative materials allowing efficient charge to spin and spin to charge current conversion, or good control of magnetic properties by voltage, or efficient injection/manipulation/detection of spins in semicon- ductors can play major roles. Along with this idea, the use of oxide materials in spintronic devices can become quite important. Oxides share crystal- linity with semiconductors in distinction to metallic magnetic devices. Will the greater control that comes with crystallinity give advantages to oxides in future devices? These are some of the many topics that are likely to be addressed in the coming years.

The basics of laser marking are reviewed, as well as current and emerging laser technologies.

BY DIETRICH TÖNNIES, Ph.D. and DIRK MÜLLER, Ph.D., Coherent Inc., Santa Clara, CA

Laser marking is established at multiple points in semiconductor production and applications continue to diversify. There are several laser technologies servicing the application space. This article reviews the basics of laser marking and the current and emerging laser technologies they utilize. It is intended to give a clear sense of what applications parameters drive the choice of laser (speed, cost, resolution, etc.), and provide those developing a new application some guidance on how to select the optimum technology.

Laser marking basics

Laser marking usually entails inducing a visible color or texture change on a surface. Alternatively, although less commonly, marking sometimes involves producing a macroscopic change in surface relief (e.g.engraving). To understand what laser type is best for a specific marking application, it is useful to examine the different laser/ material interactions that are generated by commonly used laser types.

Most frequently, lasers produce high contrast marks through a thermal interaction with the work piece. That is, material is heated until it undergoes a chemical reaction (e.g. oxidation) or change of crystalline structure that produces the desired color or texture change. However, the particulars of this process vary significantly between different materials and laser types.

CO2 lasers have been employed extensively for PCB marking because they provide a fast method of producing high contrast features. However, they are rarely selected when marking at the die or package level. This is because the focused spot size scales with wavelength due to diffraction. CO2 lasers emit the longest infrared (IR) output of any marking laser. Additionally, IR penetrates far into many materials, which can cause a substantial thermal impact on surrounding structures. Consequently, CO2 laser marking is limited to producing relatively large features where a significant heat affected zone (HAZ) can be tolerated.

Fiber lasers, which offer high power output in the near IR, have emerged over the past few years as one of the most cost effective tools for high-speed marking. Furthermore, the internal construction of fiber lasers renders a compact footprint, facilitating their integration into marking and test handlers. Cost and space savings are further enhanced when the output of a single, high power fiber laser is split, feeding two scanner systems.

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But fiber lasers have disadvantages, too. One reason for the low cost of many fiber lasers is that they are produced in high volumes with designs meant for general-purpose applications. For example, they usually produce a high quality beam with a Gaussian intensity profile. This is advantageous for many material processing applications, but not always for laser marking. In fact, a more uniform beam intensity distribution, called a flat-top profile, is sometimes more useful since it produces marks with a sharper, more abrupt edge (rather than a smooth transition from the marked to the unmarked region). Coherent recently introduced a new type of fiber (NuBEAM Flat-Top fiber technology) which enables efficient conversion of single-mode laser beams into flat-top beam profiles, specifically to address this issue.

Other quality criteria, such as high-purity linear polarization, and stability of pulse energy and pulse width, are difficult to achieve with low-cost fiber lasers. This limits their use in more stringent or sensitive marking applications. From a practical standpoint, most fiber lasers cannot be repaired in the field, but are replaced as a whole. This leads to longer equipment downtime and increased maintenance efforts as compared to traditional marking lasers based on diode-pumped, solid-state (DPSS) technology (specifically, DPSS is used here to refer to lasers with crystal resonators).

DPSS lasers also emit in the near infrared. Generally, these lasers are more expensive than a fiber laser of the same output power level. So, infrared DPSS lasers are most commonly used in applications having technical requirements that cannot be met by fiber lasers,such as high volume production of more advanced and expensive semiconductor devices.

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One advantage of DPSS laser technology is that it can be configured to directly produce a multi-mode beam profile which is essentially flat-top. The Coherent ❘ Rofin PowerLine E Air 30-1064 IC is an example which has found extensive use in semiconductor marking, since it provides an efficient way to rapidly produce very high contrast marks.

Another useful feature of DPSS lasers, which produce pulsewidths in the nanosecond regime, is that their output is much more stable than that of fiber lasers. This makes it much easier to reliably frequency double or triple their infrared light within the laser head, giving a choice of output in the green or ultraviolet (UV). Output at these wavelengths provides two significant benefits. First, they offer additional options in matching the absorption of the material to the laser wavelength. Stronger absorption generally yields higher marking efficiency and reduced HAZ, since the laser light doesn’t penetrate as far into the material. The second benefit of shorter wavelengths is the ability to focus to smaller spot sizes (because of their lower diffraction) and produce smaller, finer marks.

However, frequency multiplied DPSS lasers are generally more costly and voluminous than either fiber lasers or infrared DPSS lasers with comparable output power. Lower power translates into reduced marking speed.

Therefore, green and UV DPSS lasers are typically employed when they offer a significant advantage due to the particular absorption characteristics of the material(s) being marked.

Another emerging and important class of marking lasers has pulsewidths in the sub-nanosecond range. Due to the nature of the laser/material interaction at short pulsewidths, these lasers tend to produce the smallest possible HAZ with excellent depth control.

There are just a few products currently on the market that exploit this property. One example is the PowerLine Pico 10 from Coherent ❘ Rofin which generates 0.5 ns laser pulses in either the near IR (8 W total power) or green (3 W total power), at pulse repetition rates between 300 kHz and 800 kHz. This combination of output characteristics makes it capable of high speed marking of a wide range of materials where mark penetration depth must neces- sarily be shallow because of low material thickness, or to minimize HAZ.

Laser marking today

Typically, the first consideration in choosing a laser for a specific application is matching the absorption characteristics of the material with the laser wavelength. Similarly, desired feature size is also driven by laser wavelength, as well as by the precision of the beam scanning system. Next, HAZ constraints usually determine the maximum pulsewidth which can be used (although this choice is again highly material dependent). To see how these parameters interact in practice, it’s useful to review some real world applications.

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Epoxy-based molding compounds

The most commonly used molding compounds absorb very well in the near IR. Specifically, the near IR laser transforms the usually black molding compound into a gray/white powder, yielding high contrast marks. Plus, many IC packages have mold compound caps thick enough to easily tolerate a marking depth of 30 μm to 50 μm. As a result, many marking systems based on near IR lasers, both fiber and DPSS, are currently in use.

However, some semiconductor devices with small form factor have only thin mold compound caps to protect wire bonded silicon dies, and a marking depth of only 10 μm or less is required. Increasingly, green lasers are used for this type of shallow marking because of a stronger absorption at this wavelength by the epoxy matrix.

Ceramics

The process window when marking ceramics, such as used in packaging power semiconductors, high-brightness LEDs, RF devices, saw filters or MEMS sensors, is relatively narrow. Accurate focus and high pulse energy are critical to ensure reliable marking results, and ideally, the laser marker should have the capability to adjust the focus of the laser beam onto the ceramic surface in real time, in order to compensate for package height variations. Because of their more reliable interaction with ceramic materials, DPSS lasers based on Nd:YAG, which offer high pulse energies and relatively long pulses, are often still used for marking ceramic lids and substrates. Coherent ❘ Rofin has also developed a special fiber laser (the PowerLine F 20 Varia IC), which offers adjustable pulse widths up to 200 ns, specifically to improve process windows for marking applications of this type.

The ceramic substrates used with high-power LEDs often require tiny marks to identify individual devices. IR lasers are the preferred lasers for marking these ceramic substrates, providing their spot size is not too big for the layout to be marked. For very small marking features a green laser or UV laser is often required.

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Organic substrates

IC substrates or interposers are marked during production with traceable data matrix codes. The thin green solder resist layer on top of the substrate has to carry the mark, and care has to be taken that the copper underneath the solder resist is not exposed. Moreover, data matrix codes can be quite small, with cell sizes of only 125 μm or even less. Since the spot size of the focused laser beam must thus be much smaller than the cell size, the final spot diameter must be significantly less than 100 μm.

Defective IC substrates often are identified by marking large features (e.g., a cross) into the solder resist layer. Although the part is defective, the properties of the mark are still important. This is because it has to be reliably recognized by subsequent processing tools, and also, because any delamination of the solder resist layer might cause problems during succeeding processes.

IC strips have gold pads along their periphery which are used to identify parts found to be defective after die attach and wire bonding. For defective parts, the gold pad is marked by converting its color from gold to black or to dark grey.

Ideally, it is desirable to have one laser marker that can accomplish all three of these marking applications tasks. The green DPSS laser has become the standard laser marker for these applications, with UV lasers occasionally employed for high-end substrates.

Semiconductors

The growing demand for flip-chip devices, wafer-level packaging and defective die identification drives the need for direct marking of silicon, GaAs, GaN/sapphire or other semiconductors. Silicon is partially trans- parent in the near IR, and lasers at this wavelength are used whenever deep marks into silicon are required, such as placing wafer IDs near the wafer edge. Near IR laser markers are also selected for marking molded fan-out wafer level packaging wafers.

However, for marking either flip-chips or the backside of wafers, green lasers are preferred because of the strong absorption of this wavelength in silicon. Wafer backside marking requires only very shallow marks and the shallow laser penetration avoids potential damage to the circuitry on the reverse side of the flip-chip or wafer. The need for shallow marking also minimizes the laser power requirement. For example, Coherent ❘ Rofin provides a 6 W green laser (the PowerLine E 12 SHG IC) that is well suited for wafer backside marking, and can also mark the wafer through the tape whenever the wafer is mounted on a film frame.

Metals

Near IR lasers are widely used for marking the metal lids used with microprocessors and other high power consumption ICs.

Leadframes, which are plated with tin, silver or gold, are marked either before or after plating. Since leadframes are used for cost sensitive devices, capital investment is critical, and economical fiber lasers are often chosen for this reason.

Laser marking tomorrow

As packages get thinner and smaller, they will require shallower, higher resolution marks. Sub-nanosecond lasers are the most promising method for producing these types of marks, and are compatible with a wide range of materials. The diverse capabilities of this technology are shown in Figure 5, which depicts marking results on four different materials using a sub-nanosecond laser (Coherent ❘ Rofin PowerLine Pico 10-532 IC).

The first image is a flexible IC substrate; very thin solder resist layers and metal coatings make it important that the laser does not cause delamination. Here, the circular gold pad has been converted to black without delamination. In the next image, an IC substrate has been given a white mark, again without delaminating the solder resist.

The third image shows very small characters (< 150 μm) marked on the backside of a silicon wafer containing hundred thousands of tiny discrete semiconductor devices. Producing marks of this resolution through the film would be difficult to accomplish with a nanosecond pulsewidth laser.

The final image is a copper leadframe coated with thin silver film. Here, the goal is to produce a shallow mark with high contrast without engraving the under- lying material, which has been accomplished with the sub-nanosecond laser.

Conclusion

Semiconductor fabrication and packaging represent challenging marking applications, often requiring small, fine marks produced without a significant effect on surrounding material. An overall trend towards smaller and thinner device geometries will drive increased use of higher precision laser tools, such as those utilizing green and UV nanosecond lasers, and even sub-nanosecond lasers, while cost-sensitive applications will continue to utilize inexpensive fiber lasers.

Despite a slightly down first quarter, the semiconductor industry achieved near record growth in the second quarter of 2017, posting a 6.1 percent growth from the previous quarter, according to IHS Markit (Nasdaq: INFO). Global revenue came in at $101.4 billion, up from $95.6 billion in the first quarter of 2017. This is the highest growth the industry has seen in the second quarter since 2014.

The memory chip market set records in the second quarter, growing 10.7 percent to a new high of $30.2 billion with DRAM and NOR flash memory leading the charge, growing 14 percent and 12.3 percent quarter-on-quarter, respectively.

“The DRAM market had another quarter of record revenues on the strength of higher prices and growth in shipments,” said Mike Howard, director for DRAM memory and storage at IHS Markit. “Anxiety about product availability in the previous third and fourth quarters weighed on the industry. This led many DRAM buyers to build inventory — putting additional pressure on the already tight market. This year is shaping up to smash all DRAM revenue records and will easily pass the $60 billion mark.”

“For NOR, the supply-demand balance has tightened raising average selling prices and revenue,” said Clifford Leimbach, senior analyst for memory and storage at IHS Markit. “This mature memory technology has been in a steady decline for many years, but some market suppliers are reducing supply or leaving the market, which has tightened supply recently, resulting in the increase of revenue.”

In terms of application, consumer electronics and data processing saw the most growth, increasing in revenue by 7.9 percent and 6.8 percent, respectively, quarter-on-quarter. A lot of this growth can be attributed to the continual growth in memory pricing, as supply still remains tight.

Industrial semiconductors showed the third highest growth rate at 6.4 percent during the same period. This growth can be attributable to multiple segments, such as commercial and military avionics, digital signage, network video surveillance, HVAC, smart meters, traction, PV inverters, LED lighting and medical electronics including cardiac equipment, hearing aids and imaging systems.

Another trend in the industrial market is increasing factory automation, which alone is driving growth for discrete power transistors, thyristors, rectifiers and power diodes. The market for these devices is expected to reach $8 billion in 2021, up from $5.7 billion in 2015.

Intel remains the number one semiconductor supplier in the world, followed by Samsung Electronics by a slight margin. IHS Markit does not include foundry operations and other non-semiconductor revenue in the semiconductor market rankings.

Among the top 20 semiconductor suppliers, Advanced Micro Devices (AMD) and nVidia achieved the highest revenue growth quarter over quarter by 24.7 percent and 14.6 percent, respectively. There was no market share movement in the top 10 semiconductor suppliers. However, seven of the 10 companies in the 11 to 20 market share slots did change market share.

top_5_semiconductor_companies

The latest update to the World Fab Forecast report, published on September 5, 2017 by SEMI, again reveals record spending for fab equipment. Out of the 296 Front End facilities and lines tracked by SEMI, the report shows 30 facilities and lines with over $500 million in fab equipment spending.  2017 fab equipment spending (new and refurbished) is expected to increase by 37 percent, reaching a new annual spending record of about US$55 billion. The SEMI World Fab Forecast also forecasts that in 2018, fab equipment spending will increase even more, another 5 percent, for another record high of about $58 billion. The last record spending was in 2011 with about $40 billion. The spending in 2017 is now expected to top that by about $15 billion.

fab equipment spending

Figure 1: Fab equipment spending (new and refurbished) for Front End facilities

Examining 2017 spending by region, SEMI reports that the largest equipment spending region is Korea, which increases to about $19.5 billion in spending for 2017 from the $8.5 billion reported in 2016. This represents 130 percent growth year-over-year. In 2018, the World Fab Forecast report predicts that Korea will remain the largest spending region, while China will move up to second place with $12.5 billion (66 percent growth YoY) in equipment spending. Double-digit growth is also projected for Americas, Japan, and Europe/Mideast, while other regions growth is projected to remain below 10 percent.

The World Fab Forecast report estimates that Samsung is expected to more than double its fab equipment spending in 2017, to $16-$17 billion for Front End equipment, with another $15 billion in spending for 2018. Other memory companies are also forecast to make major spending increases, accounting for a total of $30 billion in memory-related spending for the year. Other market segments, such as Foundry ($17.8 billion), MPU ($3 billion), Logic ($1.8 billion), and Discrete with Power and LED ($1.8 billion), will also invest huge amounts on equipment. These same product segments also dominate spending into 2018.

In both 2017 and 2018, Samsung will drive the largest level in fab spending the industry has ever seen. While a single company can dominate spending trends, SEMI’s World Fab Forecast report also shows that a single region, China, can surge ahead and significantly impact spending. Worldwide, the World Fab Forecast tracks 62 active construction projects in 2017 and 42 projects for 2018, with many of these in China.

For insight into semiconductor manufacturing in 2017 and 2018 with more details about capex for construction projects, fab equipping, technology levels, and products, visit the SEMI Fab Database webpage (www.semi.org/en/MarketInfo/FabDatabase) and order the SEMI World Fab Forecast Report. The report, in Excel format, tracks spending and capacities for over 1,200 facilities including over 80 future facilities, across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities.

By Ajit Manocha, president and CEO, SEMI

In my first six months at SEMI, I’ve visited with many member companies and industry leaders.  One theme I hear repeatedly is a concern about our most fundamental source of innovation and productivity – people.

Our industry has a significant need for additional workers and several trends are working against us.

For one, only 11 percent of elementary students in the U.S. indicate an interest in science, technology, engineering, and mathematics (STEM) education according to the National Science Foundation.  In other regions, recruiting and retaining high-skilled workers remains a constant challenge.

Ironically, the incredible electronics manufacturing technology that we create has enabled many of the new-tech industries in software, social media, internet services and applications that now directly compete for the best and brightest technical talent.  Young engineers have other choices and many are lured to newer growth industries with familiar internet brands.

Today, due to continued industry advancement and robust growth, capital equipment companies, device makers and materials companies collectively have thousands to tens-of-thousands of open unfilled positions. Furthermore, the representation of women in the high-tech workplace remains disproportionately low.

We have long been aware of the need to support a diverse pipeline for high-skilled workers.  In 2001, the SEMI Foundation was established to encourage STEM education and stimulate interest in high-tech careers. SEMI and its Foundation launched the High-Tech U (HTU) program to engage and excite high school students. HTU enlists industry volunteers to work with local high school students in a three-day interactive hands-on curriculum. Young people get a fun and inspirational exposure to binary logic, circuit making, a fab or electronics manufacturing setting and other aspects of professional development.

To date, we’ve delivered 216 HTU programs and reached nearly 7,000 students in 12 states and nine countries.  The results are compelling.  Our 2016 survey of HTU alumni shows that they enter college at five times the national rates and 70 percent that graduated college are employed in a STEM field.   By any measure, the initiative is successful and worthwhile.

However, the talent problem statement has grown. Industry needs are greater and the time has come to redouble our effort to attract and retain talent for our high-skilled manufacturing sector.  Therefore, SEMI is elevating workforce development as a top strategic priority.

The SEMI HTU team is already engaged with key member companies to develop our enhanced roadmap for workforce development including a comprehensive study with Deloitte Consulting to underpin the key problems and solutions in areas of focus for decisive and systematic SEMI action.

Belle Wei, SEMI Foundation Board member and the Carolyn Guidry Chair in Engineering Education and Innovative Learning at San Jose State University said, “It is critical that we work to prepare the future workforce.  This requires a high level of collaboration between industry and higher education.  We appreciate SEMI’s leadership role in this collaboration to further develop the workforce pipeline.”

We have launched a HTU Certified Partner Program (CPP) with the goal of reaching more students through industry partners who commit to long-term participation and independent delivery of High Tech U.  In addition, we are expanding outreach to universities and community colleges and preparing to launch an industry image campaign to better tell the remarkable story of opportunity in our industry.

The capacity to innovate and the skills to manage complex design, engineering and manufacturing processes are essential factors that sustains our high-tech industry – and they are dependent on people.

Finally, as mentioned above, we have already started some new initiatives to enhance our HTU. A SEMI workforce development roadmap and execution plan will be detailed in a future SEMI Global Update article following the upcoming SEMI International Board Meeting.  SEMI welcomes any inputs in addition to your continued support.

This endeavor is increasingly urgent and recruiting the industry’s future innovators is well-aligned with SEMI’s mantra to connect, collaborate, innovate, grow and prosper.

Following a substantial increase in semiconductor capital expenditures during the first half of this year, IC Insights raised its annual semiconductor capex forecast to a record high of $80.9 billion for 2017, a 20% increase from $67.3 billion in 2016. Previously, 2017 semiconductor capex was expected to grow 12% in 2017 to $75.6 billion.

A little over half of 2017 capex spending is forecast for wafer foundries (28%) and upgrades for NAND flash memory (24%), as shown in Figure 1. With a projected 53% increase in 2017, the DRAM/SRAM segment is expected to display the largest percentage growth in capital expenditures of the major product types this year. With DRAM prices surging since the third quarter of 2016, DRAM manufacturers are once again stepping up spending in this segment. Although the majority of this spending is going towards technology advancement, DRAM producer SK Hynix recently admitted that it can no longer keep up with demand by technology advancements alone and needs to begin adding wafer start capacity.

Figure 1

Figure 1

Even with a DRAM spending surge this year, capital spending for flash memory in 2017 ($19.0 billion) is still expected to be significantly higher than spending allocated to the DRAM/SRAM category ($13.0 billion). Overall, IC Insights believes that essentially all of the spending for flash memory in 2017 will be dedicated to 3D NAND process technology, including production of 3D NAND at Samsung’s giant new fab in Pyeongtaek, South Korea.

Overall, capital spending for the flash memory segment is forecast to register a 33% surge in 2017 after a strong 23% increase in 2016. However, historical precedent in the memory market shows that too much spending usually leads to overcapacity and subsequent pricing weakness. With Samsung, SK Hynix, Micron, Intel, Toshiba/Western Digital/SanDisk, and XMC/Yangtze River Storage Technology all planning to significantly ramp up 3D NAND flash capacity over the next couple of years (and new Chinese producers possibly entering the market), IC Insights believes that the future risk for overshooting 3D NAND flash market demand is high and growing.

IC Insights has revised its outlook for semiconductor industry capital spending and presented its new findings in the August Update to The McClean Report 2017.  IC Insights’ latest forecast is for semiconductor industry capital spending to climb 20% this year.

Figure 1 shows the steep upward trend of quarterly capital spending in the semiconductor industry since 1Q16. Although there was a slight pause in the upward trajectory in 1Q17, 2Q17 set a new record for quarterly spending outlays.   Moreover, 1H17 semiconductor industry spending was 48% greater than in 1H16.  IC Insights believes that whether industry-wide capital spending in the second half of 2017 can match the first half of the year is greatly dependent upon the level of Samsung’s 2H17 spending outlays.

Not only has Samsung Semiconductor been on a tear with regard to its semiconductor sales, surging into the number one ranking in 2Q17, but the company has also been on a tremendous capital spending spree for its semiconductor division this year.  As depicted in Figure 2, Samsung spent a whopping $11.0 billion in capital outlays for its semiconductor group in 1H17, more than 3x greater than the company spent in 1H16 and only $300 million less than the company spent in all of 2016!   In fact, Samsung’s capital expenditures in 1H17 represented 25% of the total semiconductor industry capital spending and 28% of the outlays in 2Q17.

While the company has publicly reported that it spent $11.0 billion in capital outlays for its semiconductor division in 1H17 (a $22.0 billion annual run-rate), Samsung has been very secretive about revealing its full-year 2017 budget for its semiconductor group (it might be afraid of shocking the industry with such a big number!).  In 2012, the year of Samsung’s previous first half spending surge before 1H17, the company cut its second half capital outlays by more than 50%, from $8.5 billion in 1H12 to $3.7 billion in 2H12.  Will the company follow the same pattern in 2017?  At this point, it is impossible to tell.  IC Insights believes that Samsung’s full-year 2017 capital expenditures could range from $15.0 billion to $22.0 billion!

Figure 1

Figure 1

If Samsung spends $22.0 billion in capital outlays this year, total semiconductor industry capital spending could reach $85.4 billion, which would represent a 27% increase over the $67.3 billion the industry spent in 2016.

It is interesting to note that two of the major spenders, TSMC and Intel, are expected to move in opposite directions with regard to their 2H17 capital spending plans. TSMC spent about $6.8 billion in capital outlays in 1H17. If it sticks to its $10.0 billion budget this year, which it reiterated in its second quarter results, it would only spend about $3.2 billion in 2H17, less than half its outlays in 1H17. In contrast, Intel spent only about $4.7 billion in 1H17, leaving the company to spend about $7.3 billion in 2H17 in order to reach its stated full-year 2017 spending budget of $12.0 billion.

Figure 2

Figure 2

Worldwide semiconductor capital spending is projected to increase 10.2 percent in 2017, to $77.7 billion, according to Gartner, Inc. This growth rate is up from the previous quarter’s forecast of 1.4 percent, due to continued aggressive investment in memory and leading-edge logic which is driving spending in wafer-level equipment (see Table 1).

“Spending momentum is more concentrated in 2017 mainly due to strong manufacturing demand in memory and leading-edge logic. The NAND flash shortage was more pronounced in the first quarter of 2017 than the previous forecast, leading to over 20 percent growth of etch and chemical vapor deposition (CVD) segments in 2017 with a strong capacity ramp-up for 3D NAND,” said Takashi Ogawa, research vice president at Gartner.

According to Gartner’s latest view, the next cyclical down cycle will emerge in 2018 to 2019 in capital spending, compared with 2019 to 2020 in the previous quarter’s forecast. “Spending on wafer fab equipment will follow a similar cycle with a peak in 2018. While the most likely scenario will still keep positive growth in 2018, there is a concern that the growth will turn negative if the end-user demand in key electronics applications is weaker than expected,” said Mr. Ogawa.

Table 1: Worldwide Semiconductor Capital Spending and Equipment Spending Forecast, 2016-2020
(Millions of Dollars)

2016

2017

2018

2019

2020

Semiconductor Capital Spending

70,568.9

77,794.5

77,443.5

71,814.8

73,239.5

Growth (%)

9.1

10.2

-0.5

-7.3

2.0

Wafer Fab Equipment, Including Wafer-Level Packaging

37,033.1

43,661.0

43,690.4

40,515.8

41,342.7

Growth (%)

11.4

17.9

0.1

-7.3

2.0

Other Semiconductor Capital Spending

33,535.8

34,133.5

33,753.2

31,299.0

31,896.8

Growth (%)

6.8

1.8

-1.1

-7.2

1.9

Source: Gartner (July 2017)

This research is produced by Gartner’s Semiconductor Manufacturing program. This research program, which is part of the overall semiconductor research group, provides a comprehensive view of the entire semiconductor industry, from manufacturing to device and application market trends.