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TECHCET CA, an advisory service firm providing electronic materials information, today announced that the silicon wafer supply for semiconductor device fabrication is forecasted to appreciably lag demand starting next year, and could remain in shortage through the year 2021 despite investments in China. Silicon wafer area demand is forecasted to steadily increase at a CAGR of ~3.1% over the 2016-2021 period to reach over 13,000 million square inches (MSI). Executives of silicon wafer suppliers have stated that average selling prices have remained too low to allow for investment in 300mm expansions, as detailed in a quarterly update to the TECHCET Critical Materials Report, “Silicon Wafers Market & Supply-Chain.”

The silicon wafer supply-chain is dominated by two suppliers–Shin-Etsu Handotai and SUMCO–combining to capture almost two-thirds of the global wafer market in 2016, and the top five representing over 92% of total revenues. The silicon wafer market is maturing as evidenced by recent mergers and acquisitions, the two most notable being the acquisition of SunEdison Semi by GlobalWafers (Taiwan) and the assumption of majority ownership of LG Siltron by SK Holdings (Korea).

“Over the last five years, the average selling price per square inch of semiconductor-grade silicon wafers has declined by about a third and more than a half from the 2007 level,” explained Michel Walden, lead author of the report and senior technology analyst with TECHCET. “However, current tightness in the supply-chain has led to greater stability and even price increases in some cases, all of which is likely needed for the long-term health of the wafer suppliers.”

Over the past few years, silicon suppliers decommissioned roughly 25% of the peak capacity for 200mm wafers. Of the remaining 200mm capacity, roughly 65% of the total demand is for epitaxial (epi) wafers, and a series of epi service companies have embraced this opportunity and provide a variety of layer configurations for their customers.

BY ELISABETH BRANDL, THOMAS UHRMANN and MARTIN EIBELHUBER, EV Group, St. Florian, Austria

Fan-out packaging is an established technology for many mobile applications. Whereas early semiconductor packages have been single-chip packages, the continuing trend of expanding the wiring surface to support increased functionality has led to more complex packages, stacked packages, systems inpackageaswellashigh-performancepackages. With this development, fan-out technology is bridging a gap between cost-competitive packaging and high performance. For all aforementioned packages, temporary bonding will be needed, either to enable the thinning of wafers to address the need for smaller form factors, to achieve cost savings on mold materials or to serve as a processing platform for redistribution-layer (RDL) first processes.

Temporary bonding requires both a bonding and debonding process. Determining the right debonding technology can be difficult and confusing as every application from fan-out wafer-level packaging (FoWLP) to power devices has its own requirements in terms of process temperature, mechanical stress and thermal budget, to name just a few considerations. In this article, we will focus on laser debonding, where high- temperature compatible materials are available. We will point out for which applications the laser debond characteristics fit well.

To limit the thermal input associated with debonding, UV lasers are utilized for debonding where several materials from different temporary bonding material suppliers are available. To confine the maintenance effort to a minimum, a diode-pumped solid-state (DPSS) laser is the right choice in combination with beam-shaping optics for high process control and minimum heat input.

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Challenges of temporary bonding for FoWLP

FoWLP has gained significant industry interest in part due to carrier, the requirements of the temporary bonding material in terms of chemical and thermal compat- ibility are high. Certain kinds of polyimides comply with this harsh environment and are also suitable for laser debonding.

By just comparing these two processes, the require- ments differ significantly even though both are FoWLP processes. By looking at the wide variety of semiconductor processes for various applications, it becomes clear that no single debonding process solution is compatible with all semiconductor processes, but rather several solutions are necessary. This is the reason why a variety of debonding processes (temporary bonding is characterized by the debonding technology) have been developed and are still in use today.

Comparison of the mainstream debonding technologies

The most common debonding methods are thermal slide-off debonding, mechanical debonding and UV laser debonding. These three methods are all in high- volume manufacturing and differ strongly in their process compatibility.

Thermal slide-off is a method that employs a thermo-plastic material as an adhesive interlayer between the device and carrier wafer. The debonding method uses the reversible thermal behavior of the thermoplastic material, meaning that at elevated temperatures the material experiences a drop in viscosity, which enables debonding to be accomplished by simply sliding the wafers off of each other. The character- istics of thermal slide-off debonding is bonding and debonding at elevated temperatures, which depending on the thermoplastic material being used can range between 130 and 350°C. Temperature stability depends in large part on mechanical stress, which can be observed due to the thermoplastic’s low viscosity at high temperatures [1].

Mechanical debonding is a method that is highly dependent on the surface properties of the wafers involved as well as the adhesion and cohesion of the temporary bonding material. For most material systems, a mechanical release layer is applied to achieve a controlled debonding mechanism. Key characteristics of mechanical debonding include processing at room temperature and a strong dependence on mechanical stress. Since mechanical debonding needs a low adhesion between the temporary bonding material and the wafer for a successful debond process, it can be tricky to use it for FoWLP applications. This is because the high wafer stress associated with FoWLP processing can lead to spontaneous debonding, even during the thinning process, which in turn can result in a drastic drop in yield [2].

Laser debonding is a technology that has been implemented with several different variations. The debond mechanism depends on the type of laser as well as the temporary bonding adhesive or the specific release layer used for the process. Infrared lasers work on the principle of the photo thermal process, where light is absorbed and transferred into heat, which leads to high temperatures within the bond interface. UV laser debonding typically uses the photo chemical process, where light is absorbed and the energy is used for breaking chemical bonds. Breaking the chemical bonds of a polymer results in the production of fragments of the original polymer. These fragments comprise gases, which increase the pressure within the interface to support the debonding process. For FoWLP applications, this method is a good fit due to the high adhesion of the temporary bonding adhesive to the wafers before the debonding process.

Optimized solution for FoWLP applications

UV lasers are advantageous for FoWLP processing due to their limited thermal input through the debonding process. The carrier wafer must be transparent to the UV laser’s wavelength to ensure efficient use of the laser energy and also ensure a higher lifetime of the carrier wafer. Two main types of UV lasers are available (solid-state laser and excimer laser), with each having several different wavelength options. Choosing a laser with a wavelength larger than 300nm is optimal for several reasons. First, commercially available laser debond materials effectively absorb and therefore debond at wavelengths higher than 300nm. Second, it allows a standard glass wafer to be used as the carrier since glass enables high transmission in this wavelength regime.

Solid-state lasers have the advantage of lower maintenance costs because they do not need halogen gas, which must be replaced on a regular basis. For solid-state lasers, the consumables are very low, and depending on the amount of power used by the laser there are examples of lasers used for laser debonding on a 24/7 basis that have required no laser consumables in the first five years of operation. Additionally, a smaller footprint can also be achieved due to a compact optical setup. Solid-state lasers typically have Gaussian beam profiles, pictured in FIGURE 3.

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UV laser debonding is a threshold process, meaning that debonding occurs above a certain value of radiant exposure. In Figure 3, the area with the blue criss-cross lines indicates the radiant exposure, which is used for the debonding process. The energy that is below or above that value (areas in red in the picture) cannot be used for debonding and is typically trans- ferred into heat, which can lead to carbonization and particle creation. Because of the lack of sufficient energy at the edge of the Gaussian laser beam profile, a certain overlap of the pulses is necessary, which is an additional variable that must be optimized in order to achieve successful debonding without carbonization. Additionally, the excess energy in the beam center can cause carbonization. A Gaussian beam profile is not suitable to limit thermal effects during debonding.

Gaussian beam profiles can be transferred into quasi top hat beam profiles by using a proprietary optical setup for beam shaping. By employing this optical setup, a highly reproducible beam for debonding (whereby the beam shape does not change over time) is achieved with constrained thermal input similar to what is seen in the “top hat” beam profile in FIGURE 4. This gives tighter process control, which in combination with the high pulse repetition rate of this laser type and the ability to scan across the surface of a fixed wafer leads to a well-controlled, high-throughput debonding process. The scanning process is pictured in FIGURE 5 where — in contrast to an excimer laser — the wafer is fixed on a static stage and the laser spot is controlled by a galvo scanner over the wafer. leads to a well-controlled, high-throughput debonding process.

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Screen Shot 2017-07-27 at 9.10.34 AM Screen Shot 2017-07-27 at 9.10.42 AMAs shown in FIGURE 6, a test wafer is used to determine the optimum radiant exposure for debonding. Even with a top hat beam profile, it is important to use a radiant exposure value close to the debonding threshold to minimize heat effects [3]. Small overlaps are necessary nonetheless because the adhesion between the temporary bonding material and the wafers is very high.

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Temporary bonding for future FoWLP

Ultrathin and stacked fan-out packages, also called Package on package (PoP), are already on several industry roadmaps due to their ability to enable higher device densities. However, the need for reconstituted wafers to become even thinner for PoP versus current FoWLP will give rise to more challenges for temporary bonding. For example, the bow of the temporary bonded wafer stack consisting of a molded wafer and a carrier wafer must be minimized to ensure uniform thinning. The maximum total thickness variation (TTV) will also become tighter depending on the final thickness. As for every 3D application, questions regarding interconnects, such as choosing via first or via last, also arises for PoP, where several processes are also available and where no standard process exists that is employed by all fan-out packaging houses.

Summary

UV laser debonding is a suitable method for both chip- first and chip-last/RDL-first FoWLP processes because it offers debonding at room temperature, and because chemically stable materials are available. The UV laser debonding solutions presented in this article combine the advantages of the solid-state laser with low mainte- nance, low consumables costs and high pulse frequencies combined with high spatial control due to the special beam-shaping optics.

Further Readings

1. Critical process parameters and failure analysis for temporary bonded wafer stacks. Karine Abadie, Elisabeth Brandl, Frank Fournel, Pierre Montméa, Wimplinger, Jürgen Burggraf, Thomas Uhrmann, Julian Bravin. Fountain Hills, Arizona: iMaps, 2016. iMaps Device Packaging Conference.

2. Temporary Wafer Carrier Solutions for thin FOWLP and eWLB-based PoP. Jose Campos, André Cardoso, Mariana Pires, Eoin O’Toole, Raquel Pinto, Steffen Kröhnert, Emilie Jolivet, Thomas Uhrmann, Elizabeth Brandl, Jürgen Burggraf, Harald Wiesbauer, Julian Bravin, Markus Wimplinger and Paul Lindner. San Jose, California : SMTA International, 2015. iWLPC (International Wafer Level Packaging Conference).

3. Key Criteria for Successful Integration of Laser Debonding. Elisabeth Brandl, Thomas Uhrmann, Jürgen Burggraf, Martin Eibelhuber, Harald Wiesbauer, Mariana Pires, Philipp Kolmhofer, Matthias Pichler, Julian Bravin, Markus Wimplinger and Paul Lindner. San Jose, California : SMTA Inter- national, 2016. iWLPC.

In its upcoming Mid-Year Update to The McClean Report 2017 (to be released later this week), IC Insights addresses the changing landscape for semiconductor industry mergers and acquisitions.

The historic flood of merger and acquisition agreements that swept through the semiconductor industry in the past two years slowed to a trickle in the first half of 2017, with the combined value of about a dozen transactions announced in 1H17 reaching just $1.4 billion.

In the first halves of 2016 and the record-high M&A year of 2015, the combined value of acquisition agreements in 1H16 and 1H15 totaled $4.6 billion and $72.6 billion, respectively (Figure 1).  Last year, M&A got off to a slow start—compared to the record-breaking pace in 1H15—but several large transactions announced in 3Q16 pushed the 2016 total value in semiconductor acquisitions to nearly $100 billion and within striking distance of the all-time high of $107.3 billion set in 2015.  A few major semiconductor acquisitions were pending or rumored to be in the works during July 2017, but it is unlikely that a 2H17 surge in purchase agreements will bring this year’s M&A total value anywhere close to those of 2016 and 2015.

The big difference between semiconductor M&A activity in 2017 and the prior two years has been the lack of megadeals.  Thus far, only one transaction in 2017 has topped a half billion dollars (MaxLinear’s $687 million cash acquisition of analog and mixed-signal IC supplier Exar announced in March 2017 and completed in May).  There were seven announced acquisitions with values of more than $1 billion in 2016 (three of which were over $10 billion) and 10 in 2015 (four of which were over $10 billion).  IC Insights’ M&A list only covers semiconductor suppliers and excludes acquisitions of software and systems businesses by IC companies (e.g., Intel’s planned $15.3 billion purchase of Mobileye, an Israeli-based provider of digital imaging technology for autonomous vehicles, announced in March 2017).

The 250+ page Mid-Year Update to the 2017 edition of The McClean Report further describes IC Insights’ updated forecasts for the 2017-2021 timeperiod.

Figure 1

Figure 1

As active-matrix organic light-emitting diode (AMOLED) displays quickly displace liquid crystal displays (LCDs) in smartphones, panel makers are rapidly adding new production capacity, accelerating the demand for the fine metal mask (FMM), a critical production component used to manufacture red-green-blue (RGB) AMOLEDs. The FMM market is forecast to grow at a compound annual growth rate (CAGR) of 38 percent from $234 million in 2017 to $1.2 billion in 2022, according to IHS Markit (Nasdaq: INFO).

 

AMOLED_FMM_revenue_forecast

In the AMOLED manufacturing process, FMM is a production component used to pattern individual red, green and blue subpixels. A heating source evaporates organic light-emitting materials, but vapor deposition can only be controlled precisely with the use of a physical mask. FMM — a metal sheet, only tens of microns thick, with millions of very small holes per panel — is the only production-proven method of accurately depositing RGB color components in high-resolution displays.

“FMM has become a bottleneck in the supply of AMOLED panels due to the manufacturing technology challenges posed by increasing resolutions and a limited supply base. As pixels per inch (PPI) increase, thinner FMMs with finer dimensions are required, which reduce mask production yield and useable lifetime,” said Jerry Kang, senior principal analyst of display research at IHS Markit.

Dai Nippon Printing (DNP) is the dominant FMM supplier, owing to its proprietary etching technology for very thin metal foils and mass production experience. Currently, DNP’s FMMs are used to fabricate the vast majority of AMOLED smartphone panels, and exclusively for high-end quad high definition (QHD) resolutions. “Most panel makers are now trying to procure DNP’s FMM in hopes of being able to quickly ramp new fabs to high yields,” Kang said.

The critical nature of FMM and rapid demand growth are encouraging a number of companies to develop alternative FMM technologies and enter the market. Panel makers are also encouraging new players as a second source to mitigate supply chain risk and create price competition. As the supply of FMM is a determinant factor in the AMOLED display market to meet its projected growth rates, and with the FMM market forecast to grow five times its current size by 2022, FMM is garnering intense interest from both set and panel makers alike and creating new opportunities for suppliers.

The AMOLED Shadow Mask Technology & Market – 2017 report from IHS Markit provides a comprehensive analysis of the latest technology and market trends for FMMs and open masks, as well as mask and panel supplier status updates, including forecasts of revenues, units, area and prices from 2014 to 2022.

 

In its upcoming Mid-Year Update to The McClean Report 2017 (to be released at the end of July), IC Insights addresses the amazing growth of the 2017 DRAM and NAND flash memory markets.

Sales of both memory types—DRAM and NAND—are expected to set record highs this year.  In both cases, the strong annual upturn in sales is being driven almost entirely by fast-rising average selling prices.  In the case of DRAM, unit shipments are actually forecast to show a decline this year.  Moreover, NAND shipments are forecast to increase only 2%, providing a small, added boost to the market growth in that segment. Prices for DRAM and NAND first began increasing in the second half of 2016, and continued with quarterly increases through the first half of 2017. Figure 1 plots the robust quarterly ASP growth rates, which, from 3Q16 through 2Q17, averaged 16.8% for DRAM and 11.6% for NAND.

Figure 1

Figure 1

With DRAM ASPs surging since the third quarter of 2016, DRAM manufacturers once again stepped up their spending for this segment.  However, the majority of this spending is going towards technology advancements and not toward capacity additions.

IC Insights believes that essentially all of the spending for flash memory in 2017 will be used for 3D NAND flash memory process technology as opposed to planar flash memory.  A big increase in NAND flash capital spending this year is expected from Samsung as it ramps 3D NAND production at its large, new fab in Pyeongtaek, South Korea.

Historical precedent in the memory market shows that too much spending usually leads to overcapacity and subsequent pricing weakness. Samsung, SK Hynix, Micron, Intel, Toshiba/SanDisk, and XMC/Yangtze River Storage Technology each plan to significantly ramp up 3D NAND flash capacity over the next couple of years (with additional new Chinese producers possibly entering the market).  The likelihood of overshooting 3D NAND flash capacity over the next few years is very high.

IC Insights shows the DRAM quarterly ASP growth rate peaked in 4Q16 but continued a strong upward trend through 2Q17. IC Insights forecasts the DRAM ASP to increase (though marginally) into 3Q17 before edging slightly negative in 4Q17, signaling the end of another cyclical upturn.

Even though DRAM ASP growth is forecast to slow in the second half of the year, the annual DRAM ASP growth rate is still forecast to be 63%, which would be the largest annual rise for DRAM ASPs dating back to 1993 when IC Insights first started tracking this data.  The previous record-high annual growth rate for DRAM ASP was 57% in 1997.  For NAND flash, the 2017 ASP is forecast to increase 33%, also a record high gain. (In the year 2000, the predominantly NOR-based flash ASP jumped 52%).

The 250+ page Mid-Year Update to the 2017 edition of The McClean Report further describes IC Insights’ updated forecasts for DRAM and NAND flash memory for 2017-2021 and includes a refreshed outlook on its semiconductor capital expenditure forecast.

In its upcoming Mid-Year Update to The McClean Report 2017 (to be released at the end of July), IC Insights forecasts that the 2017 global electronic systems market will grow by only 2% to $1,493 billion while the worldwide semiconductor market is expected to surge by 15% this year to $419.1 billion. Moreover, IC Insights forecasts that the total semiconductor market will exceed $500.0 billion four years from now in 2021.  If the 2017 forecasts come to fruition, the average semiconductor content in an electronic system will reach 28.1%, an all-time record (Figure 1).

Figure 1

Figure 1

Historically, the driving force behind the higher average annual growth rate of the semiconductor industry as compared to the electronic systems market is the increasing value or content of semiconductors used in electronic systems.  With global unit shipments of cellphones (0%), automobiles (2%), and PCs (-2%) forecast to be weak in 2017, the disparity between the slow growth in the electronic systems market and high growth of the semiconductor market is directly due to the increasing content of semiconductors in electronic systems.

While the trend of increasing semiconductor content has been evident for the past 30 years, the big jump in the average semiconductor content in electronic systems in 2017 is expected to be primarily due to the huge surge in DRAM and NAND flash ASPs and below average electronic system sales growth this year. After dipping slightly to 28.6% in 2020, the semiconductor content figure is expected to climb to 28.9% in 2021, an average yearly gain over the 2016-2021 timeperiod of about 0.8 percentage points.

Of course, the trend of increasingly higher semiconductor value in electronic systems has a limit. Extrapolating an annual increase in the percent semiconductor figure indefinitely would, at some point in the future, result in the semiconductor content of an electronic system reaching 100%.  Whatever the ultimate ceiling is, once it is reached, the average annual growth for the semiconductor industry will closely track that of the electronic systems market (i.e., about 4% per year).  In IC Insights’ opinion, the “ceiling” is at least 30% but will not be reached within the forecast period.

The 250+ page Mid-Year Update to the 2017 edition of The McClean Report further describes IC Insights’ IC market forecast data for 2017-2021.

By Lynnette Reese

On Wednesday, Intel Corporation’s Katherine Winter, Vice President of the Automated Driving Group, delivered a keynote that many would think is off-topic from the usual at SemiCon West: ”Big Data in Autonomous Driving.” She revealed that autonomous driving will shift the semiconductor industries’ focus to processing terra flops of data at blinding speeds with low latency. Winter stated, “A lot of the testing that’s going on today is to find what is the right level of MIPS to have the safest possible drive.” Winter addressed the need for computing power by the semiconductor industry to meet the challenges that autonomous driving for the passenger economy will pose. Intel, in working with Strategy Analytics, finds that the Passenger Economy may be worth $7 trillion by 2050. The largest factor holding this new business space back may very well be consumer acceptance.

The burden on semiconductor processors and supporting ICs will be driven part by data. Massive amounts of data will be driven by multiple sensors, “so that you, if you are riding in it, you trust that the vehicle knows what it’s doing…you want to know that it can handle snow and ice.” The sensors complement each other. “As we go through more and more testing, and there’s more of those vehicles out there, we are learning about the combinations, how much redundancy, things like that, that you actually need in the vehicle.” Emerging pedestrians, variable weather conditions, and myriad navigation issues from differing state regulations to undocumented construction and potholes also contribute to the need for data from differing variables aimed at every possibility.

Such enormous amounts of data come not only as technical data from sensors on the car and from infrastructure, but from crowd-sourced data as well as personal data for drivers and passengers. Crowd-sourced data might include reporting new obstacles or construction to be incorporated into the AV’s navigating knowledge. The autonomous learning cycle continues as cars upload data to the cloud, which shares and uses the data to train other vehicles on the new information. Personal data gathered from within the car includes information about the passengers which will be critical to the new passenger economy as AVs become the foundation for new markets for services formed for passengers within the vehicle. New applications like robo-taxis, managing fleets of delivery trucks, and crowd-sourcing data for navigation and finding parking are within reach.

Challenges translate to the semiconductor industry as we try and solve associated problems. How do we store and share the data? What do we do with the data, and what data is saved? Areas of focus in this developing economy will be the speed of critical information and processing workload. Security is also a critical part of the AV vision. Both privacy and overall resistance to cyberattacks are of genuine concern. “How do we keep it secure? How do we make sure that there’s not a way for cyberattacks once those vehicles are out there?” posed Winter. In short, how do we trust autonomous vehicles in every way?

As we get to thousands and millions of autonomous vehicles, we will also need to understand how many we want to manage at one time. At scale, we can share safety data, create standards, and even promote an industry platform. Winter acknowledged that the semiconductor industry is not new to challenges, but indicated that the landscape will change, “We think we know what the sensors are, we think we know that kind of data is generated, but we can’t imagine what we are going to know in two years based on the speed of acceleration that we have seen so far developing in this space.”

The “Passenger Economy,” a term coined by Intel CEO Brian Krzanich, is estimated at $7 trillion by 2050. (Source: Strategy Analytics).

The “Passenger Economy,” a term coined by Intel CEO Brian Krzanich, is estimated at $7 trillion by 2050. (Source: Strategy Analytics).

By Pete Singer

At a SEMICON West press conference yesterday, SEMI released its Mid-year Forecast. Worldwide sales of new semiconductor manufacturing equipment are projected to increase 19.8 percent to total $49.4 billion in 2017, marking the first time that the semiconductor equipment market has exceeded the market high of $47.7 billion set in 2000. In 2018, 7.7 percent growth is expected, resulting in another record-breaking year ─ totaling $53.2 billion for the global semiconductor equipment market.

Figure 1 copy

“It’s really an exciting time for the industry in the terms of technology, the growth in information and data and that’s all going to require semiconductors to enable that growth,” said Dan Tracy, senior director, IR&S at SEMI.

The average of various analysts forecast the semiconductor industry in general 12% growth for the year. “It’s a very good growth year for the industry,” Tracy said. “In January, the consensus was about 5% growth for the year and with the improvement in the market and the firmer pricing for memory we see an increase in the outlook for the market.”

The SEMI Mid-year Forecast predicts wafer processing equipment is anticipated to increase 21.7 percent in 2017 to total $39.8 billion. The other front-end segment, which consists of fab facilities equipment, wafer manufacturing, and mask/reticle equipment, will increase 25.6 percent to total $2.3 billion. The assembly and packaging equipment segment is projected to grow by 12.8 percent to $3.4 billion in 2017 while semiconductor test equipment is forecast to increase by 6.4 percent, to a total of $3.9 billion this year.

“Based on the May outlook, we are looking at a record year in terms of tracking equipment spending. This is for new equipment, used equipment, and spending related to the facility that installed the equipment. It will be about a $49 billion market this year. Next year, it’s going to grow to $54 billion, so we have two years in a row of back to back record spending,” Tracy said.

In 2017, South Korea will be the largest equipment market for the first time. After maintaining the top spot for five years, Taiwan will place second, while China will come in third. All regions tracked will experience growth, with the exception of Rest of World (primarily Southeast Asia). South Korea will lead in growth with 68.7 percent, followed by Europe at 58.6 percent, and North America at 16.3 percent.

SEMI forecasts that in 2018, equipment sales in China will climb the most, 61.4 percent, to a total of $11.0 billion, following 5.9 percent growth in 2017. In 2018, South Korea, Taiwan, and China are forecast to remain the top three markets, with South Korea maintaining the top spot to total $13.4 billion. China is forecasted to become the second largest market at $11.0 billion, while equipment sales to Taiwan are expected to reach $10.9 billion.

Figure 2

By Pete Singer

Luc Van den Hove, president and CEO of imec

Luc Van den Hove, president and CEO of imec

Speaking at imec’s International Technology Forum USA yesterday afternoon at the Marriott Marquis, Luc Van den Hove, president and CEO of imec, provided a glimpse of society’s future and explained how semiconductor technology will play a key role. From everything the IoT to early diagnosis of cancer through cell sorters, liquid biopsies and high-performance sequencing, technology will enable “endless complexity increase,” he said.

Other developments, almost all of which are being worked on at imec, include self-learning neuromorphic chips, brain implants, artificial intelligence, 5G, IoT and sensors, augmented and virtual reality, high resolution (5000 ppi) OLED displays, EOG based eye tracking and haptic feedback devices. He also acknowledged the critical importance of security issues, but suggested a solution. He noted that each chip has its own fingerprint due to nanoscale variability. That’s been a problem for the industry but we could “turn this limitation into an advantage,” he said, with an approach called PUFs — Physical Unclonable Functions (Figure 1).

Figure 1. Nanoscale variability has been a problem for the industry but we could be turned into an advantage with PUFs -- Physical Unclonable Functions.

Figure 1. Nanoscale variability has been a problem for the industry but we could be turned into an advantage with PUFs — Physical Unclonable Functions.

At the forum, imec also announced that its researchers, in collaboration with scientists from KU Leuven in Belgium and Pisa University in Italy, have performed the first material-device-circuit level co-optimization of field-effect transistors (FETs) based on 2D materials for high-performance logic applications scaled beyond the 10nm technology node. Imec also presented novel designs that would allow using mono-layer 2D materials to enable Moore’s law even below 5nm gate length. Additionally, imec announced that it demonstrated an electrically functional 5nm solution for Back-End-of-Line interconnects.

FETs based on 2D materials

2D materials, a family of materials that form two-dimensional crystals, may be used to create the ultimate transistor with a channel thickness down to the level of single atoms and gate length of few nanometers. A key driver that allowed the industry to follow Moore’s Law and continue producing ever more powerful chips was the continued scaling of the gate length. To counter the resulting negative short-channel effects, chip manufacturers have already moved from planar transistors to FinFETs. They are now introducing other transistor architectures such as nanowire FETs. The work reported by imec looks further, replacing the transistor channel material, with 2D materials as some of the prime candidates.

Figure 2. 2D materials, with the atomically-precise dimension control they enable, promise to become key materials for future innovations.

Figure 2. 2D materials, with the atomically-precise dimension control they enable, promise to become key materials for future innovations.

In a paper published in Scientific Reports, the imec scientists and their colleagues presented guidelines on how to choose materials, design the devices and optimize performance to arrive at circuits that meet the requirements for sub-10nm high-performance logic chips. Their findings demonstrate the need to use 2D materials with anisotropicity and a smaller effective mass in the transport direction. Using one such material, monolayer black-phosphorus, the researchers presented novel device designs that pave the way to even further extend Moore’s law into the sub-5nm gate length. These designs reveal that for sub-5nm gate lengths, 2D electrostatics arising from gate stack design become more of a challenge than direct source-to-drain tunneling. These results are very encouraging, because in the case of 3D semiconductors, such as Si, scaling gate length so aggressively is practically impossible.

“2D materials, with the atomically-precise dimension control they enable, promise to become key materials for future innovations. With advancing R&D, we see opportunities emerging in domains such as photonics, optoelectronics, (bio)sensing, energy storage, photovoltaics, and also transistor scaling. Many of these concepts have already been demonstrated in the labs,” says Iuliana Radu, distinguished member of technical staff at imec. “Our latest results presented in Scientific Reports, show how 2D materials could be used to scale FETs for very advanced technology nodes.”

5nm Solution for BEOL

The announced electrically functional solution for 5nm back-end-of-line (BEOL) is a full dual-damascene module in combination with multi-patterning and multi-blocking. Scaling boosters and aggressive design rules pave the way to even smaller dimensions.

As R&D progresses towards the 5nm technology node, the tiny Cu wiring schemes in the chips’ BEOL are becoming more complex and compact. Shrinking the dimensions also reduces the wires cross-sectional area, driving up the resistance-capacitance product (RC) of the interconnect systems and thus increasing signal delay. To overcome the RC delay challenge and enable further improvements in interconnect performance, imec explores new materials, process modules and design solutions for future chip generations.

One viable option is to extend the Cu-based dual-damascene technology – the current workhorse process flow for interconnects – into the next technology nodes. Imec has demonstrated that the 5nm BEOL can be realized with a full dual-damascene module using multi-patterning solutions. With this flow, trenches are created with critical dimensions of 12nm at 16nm. Metal-cuts (or blocks) perpendicular to the trenches are added in order to create electrically functional lines and then the trenches are filled with metal. Area scaling is further pushed through the introduction of fully self-aligned vias. Moreover, aggressive design rules are explored to better control the variability of the metal tip-to-tips (T2Ts).

Figure 3. Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

Figure 3. Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

Beyond 5nm, imec is exploring alternative metals that can potentially replace Cu as a conductor. Among the candidates identified, low-resistive Ruthenium (Ru) demonstrated great promise. The imec team has realized Ru nanowires in scaled dimensions, with 58nm2 cross-sectional area, exhibiting a low resistivity, robust wafer-level reliability, and oxidation resistance – eliminating the need for a diffusion barrier.

“The emergence of RC delay issues started several technology nodes ago, and has become increasingly more challenging at each node. Through innovations in materials and process schemes, new BEOL architectures and system/technology co-optimization, we can overcome this challenge as far as the 5nm node”, said Zsolt Tokei, imec’s director of the nano-interconnect program. “Imec and its partners have shown attainable options for high density area scaled logic blocks for future nodes, which will drive the supplier community for future needs.”

For the longer term, imec is investigating different options including but not limited to alternative metals, insertion of self-assembled monolayers or alternative signaling techniques such as low-energy spin-wave propagation in magnetic waveguides, exploiting the electron’s spin to transport the signal. For example, the researchers have experimentally shown that spin waves can travel over several micrometers, the distance required by short and medium interconnects in equivalent spintronic circuits.

CMOS image sensor sales are on pace to reach a seventh straight record high this year and nothing ahead should stop this semiconductor product category from breaking more annual records through 2021 (Figure 1), according to IC Insights’ 2017 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes.

After rising 9% in 2017 to about $11.5 billion, worldwide CMOS image sensors sales are expected to increase by a compound annual growth rate (CAGR) of 8.7% to $15.9 billion in 2021 from the current record high of $10.5 billion set in 2016, based on the five-year forecast in the 360-page O-S-D Report, which covers more than 40 different product categories across optoelectronics, sensors and actuators, and discrete semiconductors.

Figure 1

Figure 1

After strong growth from the first wave of digital cameras and camera-equipped cellphones, image sensor sales leveled off in the second half of the last decade.  However, another round of strong growth has begun in CMOS image sensors for new embedded cameras and digital imaging applications in automotive, medical, machine vision, security, wearable systems, virtual and augmented reality applications, and user-recognition interfaces.

Competition among CMOS image sensor suppliers is heating up for new three-dimensional sensing capability using time-of-flight (ToF) technology and other techniques for 3D imaging and distance measurements.  ToF determines and senses the distance of faces, hand gestures, and other things by measuring the time it takes for light to bounce back to sensors from emitted light (often an infrared laser or LED).  CMOS technology has progressed to the point of supporting integration of ToF functions into small chip modules and potentially down to a single die.  Sony, Samsung, OmniVision, ON Semiconductor, STMicroelectronics, and others have rolled out and developed 3D image sensors. Infineon has also jumped into the image sensor arena with a 3D offering that is built in ToF-optimized CMOS technology.

Automotive systems are forecast to be the fastest growing application for CMOS image sensors, rising by a CAGR of 48% to $2.3 billion in 2021 or 14% of the market’s total sales that year, says the 2017 O-S-D Report.  CMOS image sensor sales for cameras in cellphones are forecast to grow by a CAGR of just 2% to $7.6 billion in 2021, or about 47% of the market total versus 67% in 2016 ($7.0 billion).  Smartphone applications are getting a lift from dual-camera systems that enable a new depth-of-field effect (known as “bokeh”), which focuses on close-in subjects while blurring backgrounds—similar to the capabilities of high-quality single-lens reflex cameras.