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By Pete Singer, Editor-in-Chief

Last year, Rudolph Technologies, Inc. announced the widespread adoption and success of its newest macro defect inspection tool, the NSX® 330 Series. The NSX 330 Series provides high-speed macro defect inspection with 2D\3D metrology for advanced packaging applications, which are being developed primarily to support mobility. The company said it had been “quickly and enthusiastically adopted,” garnering repeat orders from top foundries, integrated device manufacturers (IDMs) and outsourced assembly and test (OSAT) manufacturers.

The NSX 330 Series offers an array of metrology capabilities for both 2D and 3D metrology applications, including 100 percent bump height and coplanarity measurements. The NSX 330 series has now been further improved by incorporating a high speed bump laser triangulation sensor and the highly accurate VT-SS distance and thickness sensor. “We specifically offer these capabilities on a single platform because they improve total measurement accuracy on complex materials which have troubled the industry for some time,” said Scott Balak, director, inspection product management, Rudolph Technologies Inc. (Bloomington, MN).

Figure 1 illustrates the problem. The goal is to measure the actual bump height and overall coplanarity from bump top to polyimide (PI) surface. If one or more bumps are too high or too low, the other bumps won’t connect. A high-speed laser triangulation sensor attempts to see through the polyimide (PI) layer, which is typically 3-6 microns thick. “The problem is that polyimide isn’t completely transparent, so when the triangulation sensor attempts to detect the bottom of this PI layer, it is actually finding it somewhere in the middle. The current industry’s work around is to assume a PI thickness and apply a PI layer offset; however, PI thickness variation limits the accuracy of this approach,” Balak explained.

Figure 1

Figure 1

Inaccurate measurements create unnecessary review work. Because bumps may have acceptable coplanarity, but they are incorrectly flagged for further evaluation. “Customers use the review mode to determine if the bump is actually too big, or too small” Balak said.

Enter Rudolph’s Visible Thickness and Shape Sensor (VT-SS) sensor, which can concurrently measure the transparent layer thickness as well as the metal feature step height above the surface of the transparent layer. This is achieved through the integration of reflectometry and visible light interferometry principles. The direct reflection from the transparent layer provides direct thickness measurement of the transparent material, while the interferometry captures topography (distance from the sensor), allowing the system to measure the thickness of the opaque metals by scanning over the edge of the feature.

“Rudolph samples multiple bumps with both the laser triangulation and VT-SS sensors to accurately obtain a measurement average of wafer PI thickness while simultaneously calibrating the triangulation sensor with an accurate PI offset for the specific wafer being measured.,” Balak said. “The properly calibrated triangulation sensor then quickly and accurately measures millions of bumps per wafer correctly flagging bad bumps and eliminating the need to review good product. Wafer results are then sent to our Discover Analysis solution where customers can analyze correlations between defectivity and process metrology to improve the overall process. Whether it is understanding wafer and lot level trends or specific individual bumps; Discover provides the drill down capability required for root cause analysis.”

By Ed Korczynski, Sr. Technical Editor

Medical and health/wellness monitoring devices provide critical information to improve quality-of-life and/or human life-extension. To meet the anticipated product needs of wearable comfort and relative affordability, sensors and signal-processing circuits generally need to be flexible. The SEMICON West 2016 Flexible Electronics Forum provided two days of excellent presentations by industry experts on these topics, and the second day focused on the medical applications of flexible circuits.

Flexible ultra-thin silicon

While thin-film flexible circuits made with printed thin-film transistors (TFT) have been developed, they are inherently large and slow compared to silicon ICs. Beyond dozens or hundreds of transistors it is far more efficient to use traditional silicon wafer manufacturing technology…if the wafers can be repeatedly thinned down below 50 microns without damage.

Richard Chaney, general manager of American Semiconductor, presented on a “FleX Silicon-on-Polymer” approach that provides a replacement polymer substrate below <1 micron thin silicon to allow for handling and assembly. Processed silicon-on-insulator (SOI) wafers are front-side temporarily bonded to a “handle-wafer”, then back-side grinded to the buried oxide layer, then oxide chemically removed, and then an application-specific polymer is applied to the backside. After removing the FleX wafer from the handle-wafer, the polymer provides physical support for dicing and the rest of assembly.

For the last few years, the company has been doing R&D and limited pilot production by shipping lots of wafers through partner applications labs, but in the second-half of 2015 acquired a new manufacturing facility in Boise, ID. Process tools are being installed, and the first product dice are “FleX-OPA” operational amplifiers. Initial work was supported by the Air Force Research Laboratory (AFRL), but in the last 12-18 months the company has seen a major increase in sample requests and capability discussions from commercial companies.

Printed possibilities

Bob Street of Xerox’s Palo Alto Research Center (PARC) presented on “Printed hybrid arrays for health monitoring.” There are of course fundamentally different sensor needs for different applications, and PARC is working on many thin-film transducers and circuits:

Gas sensing – outer environment or human breath,

Optical sensing – monitoring body signals such as blood oxygen,

Electrochemical sensing – detect specific enzymes, and

Pressure/Accelerometers – extreme physical conditions such as head concussions

“There are many and various ways that you can do health monitoring,” explained Street. “There will be sensors, and local electronics with amplifiers and logic and switches. One of the prime features of printing is that it is a versatile system for depositing different materials.”

PARC has built an amazing printing system for R&D that includes different functional dispense heads for ink-jet, aerosol, and extrusion so that a wide varieties of viscosities can be handled. The system also include integrated UV-cure capability. Printing tends to have the right spatial resolution on the scale of 50-100 microns for the target applications spaces.

PARC worked on an early system to monitor for head concussions and store event information. They used printed PVDF material to print accelerometers and pressure sensors, as well as ferroelectric analog memory. Various commercially available materials are used to print organic thin-film transistors (OTFT) for digital logic. For complementary digital logic, different metals would conventionally be needed for contacts to the n-type and p-type TFTs, but PARC found an additive layer that could be applied to one type such that a single metal could be used for both.

A gas sensor prototype that can can detect 100-1000ppm of carbon-monoxide was printed using carbon nano-tubes (CNT) as load resistors. They printed a 4-stage complementary inverter to provide gain, using 7 different materials. “This is a case where a very simple device uses many layers,” explained Street. “Four drops of one materials does it, so you wouldn’t look at using a subtractive process for this.”

Rigid/flex integration

Dr. Azar Alizadeh, GE Global Rsearch, presented on “Manufacturing of wearable sensors for human health & performance monitoring.” Wearables in healthcare applications include medical, high exertion, occupational, and wellness/fitness. The Figure shows a flexible blood pressure-sensor that measures from a finger-tip. Future flexible devices are expected to provide more nuanced biometric information to enable personalized medicine, but any commercially viable disposable device will have to cost <$10 to drive widespread adoption. Costs must be limited because just in the US alone the annual amount spent to serve ~50M patients in hospitals is >$880B.

Finger-tip optical blood-pressure sensor created with printed photodetector by GE Corp.

Finger-tip optical blood-pressure sensor created with printed photodetector by GE Corp.

200mm fabs reawakening


July 13, 2016

By David Lammers, Contributing Editor

Buoyed by strong investments in China, 200mm wafer production is seeing a re-awakening, with overall 200mm capacity expected to match its previous 2006 peak level by 2019 (Figure 1).

Figure 1. By 2019, 200mm fab capacity should be close to the previous peak seen in 2006, according to SEMI. Several new 200mm fabs are expected to open in China. (Source: SEMICON West presentation by Christian Dieseldorff).

Figure 1. By 2019, 200mm fab capacity should be close to the previous peak seen in 2006, according to SEMI. Several new 200mm fabs are expected to open in China. (Source: SEMICON West presentation by Christian Dieseldorff).

Speaking at a SEMI/Gartner market symposium at SEMICON West, SEMI senior analyst Christian Dieseldorff said over the next few years “we don’t see 200mm fabs closing, in fact we see new ones beginning operation. To me, that is just amazing.”

The numbers back up the rebound. Excluding LEDs, the installed capacity of 200mm fabs will reach about 5.3 million wafers per month (wspm) in 2018, almost matching the 2007 peak of 5.6 million wspm. As shown in Figure 1, By 2019 as new 200mm fabs start up in China, 200mm wafer production will surge beyond the previous 2007 peak, a surprising achievement for a wafer generation that began more than 25 years ago. Figure 2 shows how capacity, which held steady for years, is now on the increase.

Figure 2. 200mm fab capacity, which remained relatively constant for years, is now increasing.

Figure 2. 200mm fab capacity, which remained relatively constant for years, is now increasing.

Case in point: On the opening day of Semicon West, Beijing Yangdong Micro announced a new OLED 200mm fab that will be opening in the second half of 2018 to make OLED drivers, according to Dieseldorff.

Over the past few years, Japan-based companies have closed 10 200mm fabs, mostly outdated logic facilities, while expanding production of discrete power and analog ICs on 200mm wafers. But with China opening several new 200mm fabs and the expansions of existing 200mm fabs worldwide, SEMI sees an additional 274,000 wafer starts per month of 200mm production over the 2015-2018 period, adding expansions and additional fabs, and subtracting closed facilities.

“One message from our research is that we believe the existing 200mm fabs are full. Companies have done what they can to expand and move tools around, and that is coming to an end,” he said. SEMI reckons that 19 new 200mm fabs have been built since 2010, at least six of them in China.

SEMI’s Christian Dieseldorff.

SEMI’s Christian Dieseldorff.

Dieseldorff touched on a vexing challenge to the 200mm expansion: the availability of 200mm equipment. “People have problems getting 200mm equipment, used and even new. The (200mm) market is not well understood by some companies,” he said. With a shortage of used 200mm equipment likely to continue, the major equipment companies are building new 200mm tools, part of what Dieseldorff described as an “awakening” of 200mm manufacturing.

 

China is serious

Sam Wang, a research vice president at Gartner who focuses on the foundry sector, voiced several concerns related to 200mm production at the SEMI/Gartner symposium. While SMIC (which has a mix of 200mm and 300mm fabs) has seen consistently healthy annual growth, the five second-tier Chinese foundries – — Shanghai Huahong Grace, CSMC, HuaLi, XMC, and ASMC — saw declining revenues year-over-year in 2015. Overall, China-based foundries accounted for just 7.8 percent of total foundry capacity last year, and the overall growth rate by Chinese foundries “is way below the expectations of the Chinese government,” Wang said.

The challenge, he said, is for China’s foundries which rely largely on legacy production to grow revenues in a competitive market. And things are not getting any easier. While production of has shown overall strength in units, Wang cautioned that price pressures are growing for many of the ICs made on 200mm wafers. Fingerprint sensor ICs, for example, have dropped in price by 30 percent recently. Moreover, “the installation of legacy nodes in 300mm fabs by large foundries has caused concern to foundries who depend solely on 200 mm.”

But Wang emphasized China’s determination to expand its semiconductor production. “China is really serious. Believe it,” he said.

New markets, new demand

The smart phone revolution has energized 200mm production, adding to a growing appetite for MEMS sensors, analog, and power ICs. Going forward, the Internet of Things, new medical devices, and flexible and wearable products may drive new demand, speakers said at the symposium.

Jason Marsh, director of technology for the government and industry-backed NextFlex R&D alliance based in San Jose, Calif., said many companies see “real potential” in making products which have “an unobtrusive form factor that doesn’t alter the physical environment.” He cited one application: a monitoring device worn by hospital patients that would reduce the occurrence of bed sores. These types of devices can be made with “comparatively yesteryear (semiconductor) technology” but require new packaging and system-level expertise.

Legacy devices made on 200mm wafers could get a boost from the increasing ability to combine several chips made with different technologies into fan out chip scale packages (FO CSPs). Bill Chen, a senior advisor at ASE Group, showed several examples of FO CSPs which combine legacy ICs with processors made on leading-edge nodes. “When we started this wafer-level development around 2000 we thought it would be a niche. But now about 30 percent of the ICs used in smart phones are in wafer-level CSPs. It just took a lot of time for the market forces to come along.”

More coverage from this year’s SEMICON West can be found here.

By Pete Singer, Editor-in-Chief

On Monday, imec – the Leuven Belgium-based research consortium – hosted its annual imec Technology Forum (ITF) USA, a half-day conference at the Marriott Marquis. With the theme ‘Towards the Ultimate System’, imec’s speakers and industrial keynote speakers looked at the co-optimization of design and new technology, and how technology innovation can deliver the right building blocks to build these systems.

Delivering the keynote address at the event was Luc Van den hove, President and CEO of imec. He talked about how the world was in the middle of a decade of digital disruption brought about by integrated circuit innovation. He then provided an outlook of how the industry could continue to stay on the path defined by Moore’s Law by moving to nanowires and the 3rd dimension.

Luc van den hove, president and CEO of imec, tipped his hat to Gordon Moore, showing a short video clip and describing a future where Moore’s Law will live on through 3D integration.

Luc van den hove, president and CEO of imec, tipped his hat to Gordon Moore, showing a short video clip and describing a future where Moore’s Law will live on through 3D integration.

Van den hove noted what he said were obvious example of disruption today: Uber, the world’s largest taxi company that doesn’t own any taxis. Airbnb, the world’s largest accommodation provider that doesn’t own any real estate. Facebook, the world’s largest media provider, that doesn’t generate any media content.

“These are just a few examples, but we will see this kind of disruption everywhere, in every market and every segment,” he said. “Companies will have to adapt. They will have to reposition themselves in the value chain and come up with new business models. This is just the beginning.”

What’s made this disruption possible is IC technology and ubiquitous mobile computing. What’s been particularly beneficial over the last 50 years is that, in addition to the increased functionality that comes with scaling, there were advantages of faster operation at lower power. “This combination of effects that occurs simultaneously with scaling has resulted in the phenomenal evolution,” he said.
After a short video clip of Gordon Moore talking about the benefits of microprocessors, Van den hove give a realistic view of the future.

“Today, there is a lot of debate about the continuity of Moore’s Law. Yes, we’re faced with several tradeoffs. It’s getting harder and harder (to scale) and when we scale down our transistors we do not automatically the performance improvement that we used to with previous generations,” he said. “But we are sure there are sufficient solutions out there that will allow us to continue Moore’s legacy for several more decades. I am convinced that scaling will not only continue, it has to continue. If you want to enable the IoT wave, we will have to succeed in extending Moore’s law to generate the required compute power and storage capacity.”

Van den hove added that Moore’s Law is on the verge of morphing. “We will need other techniques in order to realize this complexity increase,” he said. “We will continue 2D scaling. It will evolve from the FinFET that is in mass production today towards horizontal nanowires, towards most likely vertical nanowires. This will bring us to at least the 3nm generation if not one or two generations more. This will keep us busy for the next 10-15 years.”

He stood by his past comments on the production-worth status of EUV. “To enable this, we will need a cost-effective lithography. We absolutely need EUV lithography to make this happen. I’m sure, based on the progress I’ve seen over the last 12 months, that EUV is ready to enter manufacturing. But we have to be realistic. Eventually, 2D scaling will slow down. I’m not saying it’s going to stop. But it’s getting harder and harder and hence it will require more time to transition from one geometry-based node to the next geometry node. We will need other ways to compensate for this gradual slowdown. One of the obvious ways to do so is to start using more extensively the third dimension, as the memory guys have started to do already,” he said.

Van den hove presented a future where devices are stacked on top of one another like Lego blocks. “Once we are using these vertical nanowires, it’s not so difficult to imagine that we may be stacking those transistors on top of each other – stack an n-FET on top of a p-FET and realize an SRAM cell. It’s obvious that such a 3D version of an SRAM cell has a much smaller footprint than its 2D equivalent. Once we can do that, we can even imagine that we may start stacking some of these building blocks on top of each other,” he said.

“It’s more straightforward to imagine that this can be done with a regular structure such as an SRAM design, but also FPGAs are very regular structures. We can even imagine that we could design random logic and design standard cells within the constraints of such a 3D Lego block and build up a logic circuit with these Lego blocks in a 3D fabric,” he continued.

Heterogeneous integration with photonics is also on the drawing board. “We will combine this also with 3D heterogeneous integration where we will be using chip stacking technology with high bandwidth, high density through silicon vias. We can then combine all these layers with 3D stacking and through-silicon vias, integrate all of this on an interposer, which can also be the substrate to integrate these 3D cubes,” he said. “By adding also photonics on such an interposer, we can also realize optical IOs. This is just another rendition of Moore’s Law which will allow more complexity in a smaller form factor.”

The 2015 market for semiconductor silicon wafers fell 5.3% to $7.2B on a record 10.4 BSI Si shipped, according to a new report, “Silicon Wafers Market & Supply Chain 2016, a TECHCET Critical Materials Report.” The silicon demand outlook for 2016 is expected to increase 6.8% to 11.1 BSI, largely due to the strength of the memory market. Issues with wafer supply will likely continue, as demand for 300mm polished wafers increases beyond capacity. Certain 200mm wafers are also in a tight supply situation given strong demand growth from the discrete device fabs coupled with limited supplier capacity, as explained in TECHCET’s report. Declining ASPs are expected as competition for China’s 200mm wafer demand increases and the 300mm market continues its evolution toward polished wafer usage.

Although shipments of silicon by area recovered after 2009, prices have still not recov- ered to 2008 (pre-US housing / WW credit crisis) levels. TECHCET expects aggregate Si ASPs to fall slightly in 2016 before firming or modestly increasing in 2017.

SOI wafer price increases, which started in 2014 due to a temporary supply-demand im- balance, have stabilized as new capacity has come online. Some pricing pressure is anticipated in 2016 as new players vie for market share.

The timeline for 450mm wafer piloting has been pushed out to 2019 with a ramp in 2020. While Intel remains bullish, TSMC, Samsung and Global Foundries have not yet joined the 450mm investment track. As a result, only Shin Etsu Handotai (S.E.H.) and SUMCO have invested in 450mm wafer development to date.

The top 5 silicon wafer producers account for roughly 97% of 300mm polished and epi- taxial wafers sales (by revenue). S.E.H. and SUMCO together account for over 55% of that 300mm revenue and more than 60% of the top 5’s total sales. China has no appreciable market share in the wafer market however, although acquisitions could change this in the future.

For more information on the wafer market, including details on the SOI market, please see TECHCET’s Critical Materials Report on Wafers, at https://techcet.com/product/silicon-wafers/.

By Douglas G. Sutherland and David W. Price

Author’s Note: The Process Watch series explores key concepts about process control—defect inspection and metrology—for the semiconductor industry. Following the previous installments, which examined the 10 fundamental truths of process control, this new series of articles highlights additional trends in process control, including successful implementation strategies and the benefits for IC manufacturing.

In the early stages of development, having more process control can help reduce both the number and duration of cycles-of-learning (the iterations required to solve a particular problem). In high volume manufacturing a well-thought-out process control strategy can increase baseline yield and, at the same time, limit yield loss due to excursions. At all stages, an effective process control strategy is required to ensure that the fab is operating at its lowest possible cost. In addition to minimizing production costs, adding process control steps can, counterintuitively, also minimize cycle time.

Figure 1 shows a conceptual plot of how cycle time would vary as a function of the number of process control steps. On the left hand side of the chart where there are no metrology and inspection (M&I) steps in place, the cycle time is effectively infinite. If a lot reaches the end of the line and has zero yield there is no way to isolate the problem. Theoretically one could isolate the problem by trial and error, but with only 100 process steps and only two parameters each, there would be 2100 (1.3 x 1030) possible combinations. Even testing one parameter per second, it would take much longer than the age of the universe to exhaust all possible combinations of the parameter space.

Figure 1. Cycle Time (CT) versus the number of process control (metrology and inspection) steps. In zone 1, the fab is information starved and unable to find yield excursions and isolate the underlying problems. In zone 3, the fab is getting more information than it can use. In zone 2, the fab has achieved balance – with a number of process control steps that minimizes the cycle time.

Figure 1. Cycle Time (CT) versus the number of process control (metrology and inspection) steps. In zone 1, the fab is information starved and unable to find yield excursions and isolate the underlying problems. In zone 3, the fab is getting more information than it can use. In zone 2, the fab has achieved balance – with a number of process control steps that minimizes the cycle time.

As process control steps are added the cycle time comes down from an effectively infinite value to some manageable number. At some point the cycle time will reach a minimum value. Beyond this point, adding in further process control steps will actually cause the cycle time to increase linearly with the number of added steps. The optimal amount of process control will always be a trade-off between minimizing cycle time, minimizing excursion cost, and maximizing baseline yield. The latter two usually have a much greater financial impact.

Adding process control steps can reduce a fab’s cycle time, but how does that work? A full treatment of cycle time (Queuing Theory) is far beyond the scope of this article, however at a high level, it can be broken down into a few manageable components. The total cycle time (CT) is the sum of the queue time (the time a lot spends waiting for a process tool to become available) and the processing time itself. Since the processing time is fixed, the only way to reduce CT is to concentrate on the queue time (Q). From Queueing Theory it can be shown that Q can be expressed by the product of three separate functions4,

Q = f(u) f(a) f(v)                                                                                           eqn 1

where f(u), f(a) and f(v) are, respectively, functions of utilization, availability and variability. The first two functions will always be finite, therefore it becomes clear that Q = 0 only when f(v) = 0. Put another way, reducing variability in the fab reduces the queue time, and if we remove all variability from the system the queue time will drop identically to zero and the CT will be equal to just the processing time.

Figure 2 shows a plot of CT as a function of utilization for three different levels of variability: zero, medium and high. The Y-axis measures cycle time in units of total processing time called the X-factor. When the variability is zero all the lots move through the fab in lock-step; there is no increase in CT with increasing utilization and all tools could be run, theoretically, at 100 percent utilization. In this case the queue time is zero and the CT is equal to the total processing time for all the steps (CT=1). As soon as some variability is introduced, the CT starts to increase exponentially with utilization and the more variability there is, the more dramatic the increase becomes.

Figure 2. Cycle time versus Utilization for three different levels of variability: High, Medium and Zero.

Figure 2. Cycle time versus Utilization for three different levels of variability: High, Medium and Zero.

Variability in the fab comes from many sources: in the lot arrival rate, in the frequency of maintenance requirements, and in the time required for that maintenance to be performed are just a few of the sources. An excursion—a lot that is out of control—affects all of the above.

Having more process control points will not immediately change the number of excursions in a fab but it will immediately improve the efficiency with which the fab reacts to them.

In fact, over time, having more process control points can also reduce the number of excursions because it increases a fab’s rate of learning.

Consider a lot that has been flagged for having a defect count that was beyond the control limit for process step N. If, as shown in figure 3a, there was another inspection point between process steps N and N-1, then the problem can be immediately isolated. Only the tool at step N (the process tool the offending lot went through) needs to be put down and only the lots that went through that tool since the last good inspection need to be put on hold for disposition.

By contrast, consider what would happen in figure 3b where the last inspection point was five steps ago at process step N-5. Practices differ from fab to fab, however in the worst case scenario, all ten tools that the lot went through would be put down and all lots that went through any of those tools would have to be put on hold. Instead of a minor disruption involving a single process tool and a few lots, entire modules and dozens of lots can be directly affected. Indirectly, it affects the entire fab.

Figure 3. (a) One process step between inspection points. (b) Five process steps between inspection points.

Figure 3. (a) One process step between inspection points. (b) Five process steps between inspection points.

Figure 3 shows that implementing fewer inspection steps has a threefold impact on cycle time:

  1. More process tools are involved and must be taken offline
  2. Each process tool is down for a much longer period of time because it takes longer to isolate the problem
  3. More wafers are in the impacted section of the production line. These wafers must be dispositioned

The variability introduced by these three impacts will also propagate through the fab; they constrict the flow of work in progress (WIP) through the fab, creating a WIP bubble that affects the lot arrival rate (increased variability) at every station downstream. All of these factors contribute to fab-wide variability and because of the re-entrant nature of the process flow, they add to the cycle time of every single lot in the fab.

When an excursion occurs, the resulting disruption impacts the cycle time of every lot in the fab and it quickly becomes a vicious cycle. The more excursions that happen during a given lot’s cycle time, the longer that cycle time will be. And the longer the cycle time is, the more likely it is that that lot will be in the fab when the next excursion occurs.

Adding inspection steps will add a small, known amount of cycle time to those lots that get inspected, but due to sampling (not every lot gets inspected) it will have a much smaller impact on the average. When an excursion does occur, comparatively few process tools will have to be put down and the module owner will be able to isolate the problem much sooner. The total disruption to the fab (the variability) will be reduced and the cycle time of all lots will be improved.

This counter-intuitive concept has been borne out by several fabs that have both added inspection steps and reduced cycle time simultaneously. Adding process control steps contributes to fab efficiency on several levels: accelerating R&D and ramp phases, increasing baseline yield, limiting the duration of excursions, and reducing cycle time. In short, a better-controlled process is a more efficient process.

The next article in this series will discuss the impact of process control to cycle time on so-called “hot lots” typically run during early ramp.

References:

  • “Process Watch: Fab Managers Don’t Like Surprises,” Solid State Technology, December 2014.
  • “Process Watch: Time is The Enemy of Profitability,” Solid State Technology, May 2015.
  • “Economic Impact of Measurement in the Semiconductor Industry,” Planning Report 07-2, National Institute of Standards and Technology, U.S. Department of Commerce, December 2007.
  • Hopp, W. J., and Spearman, M. L. Factory Physics (2nd). (New York: Irwin, McGraw-Hill, 2001), 325.

About the Authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

Each year at SEMICON West, the “Best of West” awards are presented by Solid State Technology and SEMI. More than 700 companies exhibit at SEMICON West and 26,000+ professionals attend, from the electronics manufacturing supply chain. The “Best of West” award was established to recognize new products moving the industry forward with technological developments in the electronics supply chain.

The Best of West 2016 Finalists will be displaying their products on the show floor at Moscone Center from July 12-14:

  • Coventor: SEMulator3D – A 3D semiconductor process modeling platform that can predicatively model any fabrication process applied to any semiconductor design. Starting from a “virtual” silicon wafer, the product performs a series of unit processes like those in the fab to create highly accurate 3D computer models of the predicted structures on wafer. (Facilities and Software category; Booth #2622)
  • CyberOptics: WaferSense® and ReticleSense® Auto Multi Sensors (AMS) – Wireless sensor devices capable of multiple measurements (leveling, vibration and relative humidity) to save time and expense while improving yields. WaferSense AMS travels through virtually any tool with its thin and light form factor, while ReticleSense AMSR has the same measurement capabilities in a reticle shaped form factor. (Metrology and Test category; Booth #2323)
  • Graphenea: Graphene Integration on CMOS-Fab – Allows large-scale manufacture of 200mm CMOS-compatible graphene wafers (SEMI Standards), with low metal contamination levels. The industrial production method will produce uniform, large-scale/high-performance graphene in high yields and a reliable manner. (Advanced Materials and Materials Management category; Booth #632)
  • Kulicke & Soffa Industries: IConn MEM PLUS High Performance Wire Bonder for Memory Devices – A new high-performance memory device bonder for gold and silver alloy wire bonding. With its advanced process, looping, overhang control and ease of use capabilities, it delivers high quality and productivity benefits in complex multi die stack package applications. (Assembly/Packaging Solutions category, Booth #6060)
  • Rorze Automation: Rorze N2 Purged LP – Maintains low humidity during critical steps. A typical bottom purged LP can only offer control of an average of 30 percent RH. However, N2 purge LP from Rorze (patent pending) can offer a humidity control that is better than 5 percent. (Components and Subsystems category; Booth #1613)
  • SPTS Technologies (an Orbotech company): Rapier-300S – A production silicon DRIE module, designed specifically for dicing of 300mm  wafers mounted on 400mm frames. It builds on SPTS experience in plasma singulation of framed 150mm and 200mm wafers, and employs patent-protected end-pointing and process control techniques, critical to delivering stronger die than traditional dicing methods. (Assembly/Packaging Solutions category; Booth #1417)

The Best of West Award winner will be announced during SEMICON West (www.semiconwest.org) on Wednesday, July 13, 2016.

Today, SEMI announced that 19 new fabs and lines are forecasted to begin construction in 2016 and 2017, according to the latest update of the SEMI World Fab Forecast report. While semiconductor fab equipment spending is off to a slow start in 2016, it is expected to gain momentum through the end of the year. For 2016, 1.5 percent growth over 2015 is expected while 13 percent growth is forecast in 2017.

Fab equipment spending ─ including new, secondary, and in-house ─ was down 2 percent in 2015. However, activity in the 3D NAND, 10nm Logic, and Foundry segments is expected to push equipment spending up to US$36 billion in 2016, 1.5 percent over 2015, and to $40.7 billion in 2017, up 13 percent. Equipment will be purchased for existing fabs, lines that are being converted to leading-edge technology, as well as equipment going into new fabs and lines that began construction in the prior year.

Table 1 shows the regions where new fabs and lines are expected to be built in 2016 and 2017. These projects have a probability of 60 percent or higher, according to SEMI’s data. While some projects are already underway, others may be subject to delays or pushed into the following year. The SEMI World Fab Forecast report, published May 31, 2016, provides more details about the construction boom.

new fab lines

Breaking down the 19 projects by wafer size, 12 of the fabs and lines are for 300mm (12-inch), four for 200mm, and three LED fabs (150mm, 100mm, and 50mm). Not including LEDs, the potential installed capacity of all these fabs and lines is estimated at almost 210,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2016 and 330,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2017.

In addition to announced and planned new fabs and lines, SEMI’s World Fab Forecast provides information about existing fabs and lines with associated construction spending, e.g. when a cleanroom is converted to a larger wafer size or a different product type.

In addition, the transition to leading-edge technologies (as we can see in planar technologies, but also in 3D technologies) creates a reduction in installed capacity within an existing fab. To compensate for this reduction, more conversions of older fabs may take place, but also additional new fabs and lines may begin construction.

For insight into semiconductor manufacturing in 2016 and 2017 with details about capex for construction projects, fab equipping, technology levels, and products, visit the SEMI Fab Database webpage and order the SEMI World Fab Forecast Report. The report, in Excel format, tracks spending and capacities for over 1,100 facilities including over 60 future facilities, across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities.

Communication and computer systems are forecast to be two of the three largest system applications for IC sales in every global region—Americas, Europe, Japan, and Asia-Pacific—this year, according to data presented in the upcoming Update to the 2016 edition of IC Insights’ IC Market Drivers, A Study of Emerging and Major End-Use Applications Fueling Demand for Integrated Circuits. Communications applications are expected to capture nearly 43% of IC sales in Asia-Pacific and 39% of the revenue in the Americas region this year. Communications and computer applications are forecast to tie as the largest end-use markets in Japan while in Europe, communications apps are forecast to trail computer applications with 23.5% of ICs sales (Figure 1).

Figure 1

Figure 1

Consumer systems are forecast to be the third-largest end-use category for ICs in the Americas and Asia-Pacific regions in 2016. Automotive is expected to be the second-largest system application for ICs in Europe, which has been a bastion for automotive electronics systems development. Each of Europe’s three largest IC manufacturers—Infineon, ST, and NXP—is annually ranked among the top suppliers of automotive ICs. In addition, the automotive segment is forecast to edge ahead of the consumer segment in Japan in 2016 to become the third-largest end-use market for ICs in that country.

Collectively, communications, computers, and consumer systems are projected to account for 86.4% of IC sales in the Americas this year (an increase of half a percentage point from 2015) and 89.5% in Asia-Pacific (a decrease of half a percentage point from 2015). This year, communications, computer, and automotive applications are forecast to represent 73.5% of IC sales in Japan and 78.8% of IC sales in Europe, the same percentage as in 2015.

For more than three decades, computer applications were the largest market for IC sales but that changed in 2013 when the global communications IC market took over the top spot due to steady strong growth in smartphones and weakening demand for desktop and notebook personal computers. Figure 2 shows that globally, communications systems are now forecast to represent 39.3% of the $291.3 billion IC market in 2016 compared to 34.7% for computers, and 10.7% for consumer, which has gradually been losing marketshare for several years. IC sales to the automotive market are forecast to represent only about 7.4% of the total IC sales this year but from 2015-2019, this segment is projected to rise by a compound average growth rate (CAGR) of 8.0%, fastest among all the end-use applications.

Figure 2

Figure 2

Additional details on end-use markets for ICs are included in the 2016 edition of IC Insights’ IC Market Drivers—A Study of Emerging and Major End-Use Applications Fueling Demand for Integrated Circuits.