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Novati Technologies Inc., a global nanotechnology development center, today announced the availability of the industry’s most advanced Integrated Sensor Platform, placing a wide variety of sensors onto multi-layer stacks of wafers in order to consume less power and perform significantly faster while reducing overall footprint. Already proven for customer devices at Novati’s commercial development and manufacturing center, the platform paves the way for stacking single or multiple sensors with a broad selection of popular–as well as emerging–substrate materials, enabling new high-end applications for markets that include medical, semiconductors, photonics, security, and aerospace.

Demonstrating a version of this capability for high-performance computing, Novati last month jointly announced with Tezzaron Semiconductor the industry’s first eight-layer 3D IC wafer stack containing active logic, which controls the memory layers. The transistor and interconnect densities per cubic millimeter were far higher than achievable with 2D 14nm silicon fabrication, representing the densest 3D IC ever reported. Not limited to the high-end markets served by that achievement, Novati’s Integrated Sensor Platform also offers great promise as an enabler for the Internet of Things (IoT).

“Energy harvesting is one of the important capabilities needed for the broad set of markets that aim to utilize the integration of sensing and processing,” said Tony Massimini, Chief of Technology for Semico Research. “Novati’s platform offers technology for integrating this energy harvesting ecosystem that includes energy generator, converters, power management, MCUs, energy storage and connectivity for small, wireless autonomous devices, like those used in wearable electronics and wireless sensor networks.”

For the past three years, Novati has demonstrated wafer-to-wafer integration of up to eight wafers, as well as custom sensors integrated directly onto mainstream CMOS architectures. With 3D manufacturing options available on both 200mm and 300mm lines, Novati offers circuit designers an unprecedented degree of freedom to architect the smart sensors of the future.

“While the ability to create multi-chip devices has been around for decades, Novati’s innovative sensor platform can accelerate the Internet of Things by expanding the ways for devices to connect and interact with all types of environments,” said David Anderson, President and CEO of Novati. “Using this platform, the world can integrate novel sensor functionality to virtually any circuitry, including digital logic, analog, mixed signal and memory–and stacking multiple sensors will soon follow. This opens a new, unlimited landscape for designers to significantly improve functionality while reducing costs and time to market.”

As an example of Novati’s substrate integration, their nanomanufacturing site bonded Tezzaron’s wafers directly, wafer-to-wafer, producing devices that can be thinned and finished to the same thickness as conventional 2D dies. The result was excellent electrical, thermal and mechanical performance. Novati’s capability to integrate sensors with such a stacked platform already has led to novel, proprietary product development for several customers.

Building on its ability to provide the world’s most advanced Integrated Sensor Platform and other innovations for the microelectronics markets, Novati intends to open its next office in Europe, where site selection is underway. In order to jointly plan new devices using novel materials that enable micro- and nanoscale functions and analyses, the company will be meeting with companies from around the globe during its participation at SEMICON Europa electronics conference in Dresden for the week of October 6.

“Europe has always been an important market for us and we are excited to continue expansion in this area,” said Julian Searle, Director of Account Management for Novati. “As the innovation initiatives in Europe continue to progress, Novati’s commercialization services and solutions are often the first call for technical pioneers that need to transform great ideas into great products.”

To the growing list of two-dimensional semiconductors, such as graphene, boron nitride, and molybdenum disulfide, whose unique electronic properties make them potential successors to silicon in future devices, you can now add hybrid organic-inorganic perovskites. However, unlike the other contenders, which are covalent semiconductors, these 2D hybrid perovskites are ionic materials, which gives them special properties of their own.

Researchers at the U.S. Department of Energy (DOE)’s Lawrence Berkeley National Laboratory (Berkeley Lab) have successfully grown atomically thin 2D sheets of organic-inorganic hybrid perovskites from solution. The ultrathin sheets are of high quality, large in area, and square-shaped. They also exhibited efficient photoluminescence, color-tunability, and a unique structural relaxation not found in covalent semiconductor sheets.

“We believe this is the first example of 2D atomically thin nanostructures made from ionic materials,” says Peidong Yang, a chemist with Berkeley Lab’s Materials Sciences Division and world authority on nanostructures, who first came up with the idea for this research some 20 years ago. “The results of our study open up opportunities for fundamental research on the synthesis and characterization of atomically thin 2D hybrid perovskites and introduces a new family of 2D solution-processed semiconductors for nanoscale optoelectronic devices, such as field effect transistors and photodetectors.”

Yang, who also holds appointments with the University of California (UC) Berkeley and is a co-director of the Kavli Energy NanoScience Institute (Kavli-ENSI), is the corresponding author of a paper describing this research in the journal Science. The paper is titled “Atomically thin two-dimensional organic-inorganic hybrid perovskites.” The lead authors are Letian Dou, Andrew Wong and Yi Yu, all members of Yang’s research group. Other authors are Minliang Lai, Nikolay Kornienko, Samuel Eaton, Anthony Fu, Connor Bischak, Jie Ma, Tina Ding, Naomi Ginsberg, Lin-Wang Wang and Paul Alivisatos.

Traditional perovskites are typically metal-oxide materials that display a wide range of fascinating electromagnetic properties, including ferroelectricity and piezoelectricity, superconductivity and colossal magnetoresistance. In the past couple of years, organic-inorganic hybrid perovskites have been solution-processed into thin films or bulk crystals for photovoltaic devices that have reached a 20 percent power conversion efficiency. Separating these hybrid materials into individual, free-standing 2D sheets through such techniques as spin-coating, chemical vapor deposition, and mechanical exfoliation has met with limited success.

In 1994, while a PhD student at Harvard University, Yang proposed a method for preparing 2D hybrid perovskite nanostructures and tuning their electronic properties but never acted upon it. This past year, while preparing to move his office, he came upon the proposal and passed it on to co-lead author Dou, a post-doctoral student in his research group. Dou, working mainly with the other lead authors Wong and Yu, used Yang’s proposal to synthesize free-standing 2D sheets of CH3NH3PbI3, a hybrid perovskite made from a blend of lead, bromine, nitrogen, carbon and hydrogen atoms.

“Unlike exfoliation and chemical vapor deposition methods, which normally produce relatively thick perovskite plates, we were able to grow uniform square-shaped 2D crystals on a flat substrate with high yield and excellent reproducibility,” says Dou. “We characterized the structure and composition of individual 2D crystals using a variety of techniques and found they have a slightly shifted band-edge emission that could be attributed to structural relaxation. A preliminary photoluminescence study indicates a band-edge emission at 453 nanometers, which is red-shifted slightly as compared to bulk crystals. This suggests that color-tuning could be achieved in these 2D hybrid perovskites by changing sheet thickness as well as composition via the synthesis of related materials.”

The well-defined geometry of these square-shaped 2D crystals is the mark of high quality crystallinity, and their large size should facilitate their integration into future devices.

“With our technique, vertical and lateral heterostructures can also be achieved,” Yang says. “This opens up new possibilities for the design of materials/devices on an atomic/molecular scale with distinctive new properties.”

The research was supported by DOE’s Office of Science. The characterization work was carried out at the Molecular Foundry’s National Center for Electron Microscopy, and at beamline 7.3.3 of the Advanced Light Source. The Molecular Foundry and the Advanced Light Source are DOE Office of Science User Facilities hosted at Berkeley Lab.

Rectennas in Baratunde A. Cola's NEST (NanoEngineered Systems and Transport) lab

Rectennas in Baratunde A. Cola’s NEST (NanoEngineered Systems and Transport) lab

Using nanometer-scale components, researchers have demonstrated the first optical rectenna, a device that combines the functions of an antenna and a rectifier diode to convert light directly into DC current.

Based on multiwall carbon nanotubes and tiny rectifiers fabricated onto them, the optical rectennas could provide a new technology for photodetectors that would operate without the need for cooling, energy harvesters that would convert waste heat to electricity–and ultimately for a new way to efficiently capture solar energy.

In the new devices, developed by engineers at the Georgia Institute of Technology, the carbon nanotubes act as antennas to capture light from the sun or other sources. As the waves of light hit the nanotube antennas, they create an oscillating charge that moves through rectifier devices attached to them. The rectifiers switch on and off at record high petahertz speeds, creating a small direct current.

Billions of rectennas in an array can produce significant current, though the efficiency of the devices demonstrated so far remains below one percent. The researchers hope to boost that output through optimization techniques, and believe that a rectenna with commercial potential may be available within a year.

“We could ultimately make solar cells that are twice as efficient at a cost that is ten times lower, and that is to me an opportunity to change the world in a very big way” said Baratunde Cola, an associate professor in the George W. Woodruff School of Mechanical Engineering at Georgia Tech. “As a robust, high-temperature detector, these rectennas could be a completely disruptive technology if we can get to one percent efficiency. If we can get to higher efficiencies, we could apply it to energy conversion technologies and solar energy capture.”

The research, supported by the Defense Advanced Research Projects Agency (DARPA), the Space and Naval Warfare (SPAWAR) Systems Center and the Army Research Office (ARO), is reported September 28 in the journal Nature Nanotechnology.

Developed in the 1960s and 1970s, rectennas have operated at wavelengths as short as ten microns, but for more than 40 years researchers have been attempting to make devices at optical wavelengths. There were many challenges: making the antennas small enough to couple optical wavelengths, and fabricating a matching rectifier diode small enough and able to operate fast enough to capture the electromagnetic wave oscillations. But the potential of high efficiency and low cost kept scientists working on the technology.

“The physics and the scientific concepts have been out there,” said Cola. “Now was the perfect time to try some new things and make a device work, thanks to advances in fabrication technology.”

Using metallic multiwall carbon nanotubes and nanoscale fabrication techniques, Cola and collaborators Asha Sharma, Virendra Singh and Thomas Bougher constructed devices that utilize the wave nature of light rather than its particle nature. They also used a long series of tests–and more than a thousand devices–to verify measurements of both current and voltage to confirm the existence of rectenna functions that had been predicted theoretically. The devices operated at a range of temperatures from 5 to 77 degrees Celsius.

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Fabricating the rectennas begins with growing forests of vertically-aligned carbon nanotubes on a conductive substrate. Using atomic layer chemical vapor deposition, the nanotubes are coated with an aluminum oxide material to insulate them. Finally, physical vapor deposition is used to deposit optically-transparent thin layers of calcium then aluminum metals atop the nanotube forest. The difference of work functions between the nanotubes and the calcium provides a potential of about two electron volts, enough to drive electrons out of the carbon nanotube antennas when they are excited by light.

In operation, oscillating waves of light pass through the transparent calcium-aluminum electrode and interact with the nanotubes. The metal-insulator-metal junctions at the nanotube tips serve as rectifiers switching on and off at femtosecond intervals, allowing electrons generated by the antenna to flow one way into the top electrode. Ultra-low capacitance, on the order of a few attofarads, enables the 10-nanometer diameter diode to operate at these exceptional frequencies.

“A rectenna is basically an antenna coupled to a diode, but when you move into the optical spectrum, that usually means a nanoscale antenna coupled to a metal-insulator-metal diode,” Cola explained. “The closer you can get the antenna to the diode, the more efficient it is. So the ideal structure uses the antenna as one of the metals in the diode–which is the structure we made.”

The rectennas fabricated by Cola’s group are grown on rigid substrates, but the goal is to grow them on a foil or other material that would produce flexible solar cells or photodetectors.

Cola sees the rectennas built so far as simple proof of principle. He has ideas for how to improve the efficiency by changing the materials, opening the carbon nanotubes to allow multiple conduction channels, and reducing resistance in the structures.

“We think we can reduce the resistance by several orders of magnitude just by improving the fabrication of our device structures,” he said. “Based on what others have done and what the theory is showing us, I believe that these devices could get to greater than 40 percent efficiency.”

Notes:

This work was supported by the Defense Advanced Research Projects Agency (DARPA), the Space and Naval Warfare (SPAWAR) Systems Center, Pacific under YFA grant N66001-09-1-2091, and by the Army Research Office (ARO), through the Young Investigator Program (YIP), under agreement W911NF-13-1-0491. The statements in this release are those of the authors and do not necessarily reflect the official views of DARPA, SPAWAR or ARO. Georgia Tech has filed international patent applications related to this work under PCT/US2013/065918 in the United States (U.S.S.N. 14/434,118), Europe (No. 13847632.0), Japan (No. 2015-538110) and China (No. 201380060639.2)

CITATION: Asha Sharma, Virendra Singh, Thomas L. Bougher and Baratunde A. Cola, “A carbon nanotube optical rectenna,” (Nature Nanotechnology, 2015). http://dx.doi.org/10.1038/nnano.2015.220

Samsung Electronics, a global producer of semiconductor and display solutions, formally opened the doors to its new Device Solutions America headquarters in San Jose, Calif., setting the stage for a new wave of innovation across the digital landscape.

Located on the same corner in San Jose’s tech corridor where Samsung’s original campus was first built more than 30 years ago, the new headquarters symbolizes both Samsung’s long heritage in Silicon Valley and the company’s focus on innovation and growth.

Samsung Electronics’ semiconductor operations’ has long been innovating and with the new America headquarters for its components business, Samsung’s R&D efforts will be bolstered substantially. Innovation and advanced technologies for next-generation devices generated at the new facility will help make a contribution to providing the critical competitive advantage that the company’s U.S. and global customers seek.

Speaking before an audience of more than 800 at the site’s grand opening ceremony, Oh-Hyun Kwon, Vice Chairman and CEO of Samsung Electronics, said “We are transforming Samsung into a world-class example of a truly market-focused technology company.” He further said that the company is “laying the groundwork for a more aggressive pace of growth over the next several decades.”

While Samsung Electronics’ Device Solutions Division has experienced growth since its arrival in Silicon Valley in 1983, it has created multiple organizations dispersed throughout the region. The move brings more than 700 employees together in one location, enhancing efficiency that is crucial in creating technologies and products at the cutting edge of technology. The 1.1-million-square-foot building will house various research labs dedicated to semiconductors, LEDs and displays, as well as staff in sales, marketing and other support areas.

Complete with gardens and open air space within the building, its new design increases collaboration by encouraging more spontaneous encounters between staff, while also bringing nature closer to the workplace to increase employees’ contentment and creativity.

Samsung’s President of its Device Solutions America operations, Jaesoo Han, said, “Today represents a major milestone as we open our most strategically important Samsung facility in the U.S. and also our biggest investment in Silicon Valley.” He went on to say that “Samsung’s goal is nothing less than to develop the best next-generation technologies for device solutions.”

Dignitaries in attendance at the grand opening for Samsung’s new headquarters included the current mayor of San Jose, the Honorable Sam Liccardo; former San Jose mayor, the Honorable Chuck Reed; State Senator Bob Wieckowski; San Jose State University President Susan Martin; and San Francisco Korean Consul General Dongman Han.

In keeping with the company’s corporate social responsibility (CSR) initiatives, Samsung announced a number of contributions to the Silicon Valley community. The company donated $100,000 to the Family Giving Tree and another $100,000 to the Second Harvest Food Bank.

Samsung Electronics has also established a $1 million STEM College Education Scholarship Fund to celebrate its latest expansion. Deserving university students who are currently enrolled in STEM-focused programs at a California State or University of California school will benefit from this program, beginning with a $50,000 gift to San Jose State University this year. Each scholarship will cover tuition and living expenses for one year.

The first all-optical permanent on-chip memory has been developed by scientists of Karlsruhe Institute of Technology (KIT) and the universities of Münster, Oxford, and Exeter. This is an important step on the way towards optical computers. Phase change materials that change their optical properties depending on the arrangement of the atoms allow for the storage of several bits in a single cell. The researchers present their development in the journal Nature Photonics.

Light determines the future of information and communication technology: With optical elements, computers can work more rapidly and more efficiently. Optical fibers have long since been used for the transmission of data with light. But on a computer, data are still processed and stored electronically. Electronic exchange of data between processors and the memory limits the speed of modern computers. To overcome this so-called von Neumann bottleneck, it is not sufficient to optically connect memory and processor, as the optical signals have to be converted into electric signals again. Scientists, hence, look for methods to carry out calculations and data storage in a purely optical manner.

Scientists of KIT, the University of Münster, Oxford University, and Exeter University have now developed the first all-optical, non-volatile on-chip memory. “Optical bits can be written at frequencies of up to a gigahertz. This allows for extremely quick data storage by our all-photonic memory,” Professor Wolfram Pernice explains. Pernice headed a working group of the KIT Institute of Nanotechnology (INT) and recently moved to the University of Münster. “The memory is compatible not only with conventional optical fiber data transmission, but also with latest processors,” Professor Harish Bhaskaran of Oxford University adds.

The new memory can store data for decades even when the power is removed. Its capacity to store many bits in a single cell of a billionth of a meter in size (multi-level memory) also is highly attractive. Instead of the usual information values of 0 and 1, several states can be stored in an element and even autonomous calculations can be made. This is due to so-called phase change materials, novel materials that change their optical properties depending on the arrangement of the atoms: Within shortest periods of time, they can change between crystalline (regular) and amorphous (irregular) states. For the memory, the scientists used the phase change material Ge2Sb2Te5 (GST). The change from crystalline to amorphous (storing data) and from amorphous to crystalline (erasing data) is initiated by ultrashort light pulses. For reading out the data, weak light pulses are used.

Permanent all-optical on-chip memories might considerably increase future performance of computers and reduce their energy consumption. Together with all-optical connections, they might reduce latencies. Energy-intensive conversion of optical signals into electronic signals and vice versa would no longer be required.

By Girolamo Di Francia, ENEA & EU-PVTP expert, Italy

Introduction

The photovoltaic (PV) sector has now reached a good maturity characterized by a worldwide installed capacity of 180 GWp, increasing at a constant rate of about 35 GWp/yr during the last three years and by an annual turnover of about 45 B$, a trend that also seems confirmed for the current year. More than 85% of all the PV plants are realized by means of PV modules based on crystalline and polycrystalline silicon (cSi solar cell technology), an industrial sector dominated by Chinese companies with a 60% of the market share. In comparison, less than 20% of the photovoltaic modules are produced in the European Union (EU) and the United States (US). Vice versa EU and US are the most relevant markets for photovoltaic products with almost 70% of the installed capacity being located in those areas (EPIA 2013, Eurobarometer 2015).

On the history and the development of such a strongly unbalanced situation, several papers have been published (see for instance: de la Tour, 2011). As a matter of fact, the question is not a minor one. Photovoltaic is indeed an important product segment of the semiconductor industry, accounting, in 2014, for about a 5% of the whole 300 B$ sales of this sector and, by now, rapidly becoming comparable to other more confirmed electronic device markets, such as those related to memories or analog devices. A very intense debate is, therefore, in progress focused on the possible strategies the US and EU should undertake in order to revitalize their photovoltaic industries so that a more suitable equilibrium between China and EU/US production is set. In this respect, it seems natural to try to learn from the historical development of the electronic industry, if similar problems have occurred in that case, and if the solutions they implemented could be transferred to the photovoltaic case.

Table 1. 2014 world leading photovoltaic manufacturers

Company Country Location of production lines
Trina Solar China China
Yingli Green Energy China China
Canadian Solar Canada, China Canada, China
Jinko Solar China China
JA Solar China China
Renesola China Poland, South Africa, India, Malaysia, South Korea, Turkey, Japan
Sharp Corporation Japan Japan, US
Motech Taiwan Taiwan, China, Japan, USA
First Solar US Malaysia, US
Sun Power US US, Philippines

Indeed, a similar situation occurred in the US semiconductor industry in the late 1980s, when it had become evident that the competition with Asian electronic chips manufacturers (memories and analog devices) was going to be lost. Most of the US electronic companies decided then to shift their production from that class of chips to new products (mainly microprocessors), also through the support of national governments initiatives. This change of approach was sustained by a growing demand for the new products that, in turn, supported the creation of a local industry of production equipment specialized for those kinds of applications (Pillai 2014). Product innovation was, therefore, in that situation, the solution to cope with the asian competition, at least temporarily.

Discussion

Whether this approach can be applied to the PV industry, as well, and innovation in solar cell technology be used to revitalize the US and EU photovoltaic industries is, however, a matter of debate. Before that paradigm can be adopted, it is important to understand the extent that the photovoltaic and the electronic sectors are similar and, in this respect, a few issues need to be more deeply discussed.

1. Technological issues

Although the basic material and processing technologies are similar, the actual fabrication processes for a cSi solar cell and an electronic chip are very different, as shown in Table 2. In the case of a solar cell, a single device is obtained out of the processing of a single silicon wafer (true large area devices) while in electronics, thousands of chips are fabricated on a single substrate (high volume production). Of course, device processing resolution requirements are also very different. For a solar cell, the minimum line to be processed is, at most, in the hundreds of microns range, while for a memory chip even less than 20 nm could be required. Both resolution and number of devices to be processed per single wafer change, in turn, the basic Fabrication Yield (FY) requirements for the two devices: for a solar cell, the FY is mainly limited by wafer handling failure, with less concern with the fabrication environment.

Table 2. A comparison of the main features of a solar cell and an electronic device

Photovoltaic Electronic
Basic Fab. Proc. = =
Large Area True large area High volume
Resolution 0.1 mm 20 nm
Reliability 25 yr/80% 5 yr (Memory card)
Operating Conditions -40 °C/+80 °C -10 °C/+50 °C
Fab. Yield Limit. Handling Wafer processing

For an electronic device, particle contamination control is critical, perhaps even more than wafer handling, and highly controlled environments (clean rooms ISO 1 and ISO 2) are mandatory. But it is, perhaps, in terms of device reliability that the two classes of devices mainly differentiate. A solar cell has to continuously work for at least 25 years in an operating temperature range that can change from – 40°C up to + 80°C, and with an end life efficiency that has to not be less than 80% of its starting one. On the contrary, an electronic device, a memory card for instance, is warranted to operate for about five years and in much less stringent operating conditions (-10 °C up to + 50 °C). It is worth noting, in this respect, that for many other electronic devices (mobile phones for instance) the full functionalities are assured for not more than two years.

2. Product innovation issues

In the electronic sector, the capacity a new product has to enter the market is, first of all, connected to its innovative performance, perhaps even more than to its cost. Let us, for instance, consider again the case of memory cards, one of the most reliable devices, as stated above. As shown in Figure 1, in the last 12 years the average product has increased its performance by a factor of 1,000, increasing its capacity from an average of 128 Mb in the year 2003, to today’s 128 GB.

Figure 1. The increase in size for an average memory card and the corresponding decrease of its cost/Mb, 2003-2014.

Figure 1. The increase in size for an average memory card and the corresponding decrease of its cost/Mb, 2003-2014.

Correspondingly, a twofold decrease in the cost/Mb has been observed, although in this same period a more limited decrease in the average product cost is actually observed (McCallum 2015).

On the contrary PV solar modules have experienced in the same period a one fold decrease (from 6 $/Wp to 0.6 $/Wp) in their average cost, but the conversion efficiency, the main technological characteristic fingerprint of the innovation for this sector, has only observed a modest 30% increase (see Figure 2).

Figure 2. The increase of the average cSi solar module conversion efficiency and the decrease of the cost/Wp, 2003-2014.

Figure 2. The increase of the average cSi solar module conversion efficiency and the decrease of the cost/Wp, 2003-2014.

Innovation, therefore, does not seem to have played a key role in the development of the photovoltaic sector and, effectively, it has been reported that the major role in PV cost reduction is due to economies of scale (ISE 2013, Goodrich 2012).

Conclusions

Sic reris stantibus, it is questionable to what extent innovation in the PV sector can effectively support the further diffusion of this form of energy and help the EU and US industries cope with the Chinese competition. Recently, for instance, it has been observed that while a certain level of product innovation can be necessary, excessive innovative technological scenarios could even be detrimental (Goodrich 2012) with respect to a more capillar photovoltaic diffusion.

The point that is important to keep in mind is that the end user of a PV module is an energy producer, and since the fuel (the solar radiation) is available at no cost, once the system used for the conversion is such that the cost of the electricity produced becomes competitive with that of other energy sources, as it is now effectively observed in several countries, the only other issue to be considered is the long-term system reliability. As the solar modules actually on the market have shown in the last 40 years, to fully comply with this requirement, it is difficult to conceive an innovative product capable of revitalizing the US or EU photovoltaic industries that is, at the same time, truly different from that classical, very sound, product. Finally, it is worth noting that it has also been demonstrated that there is no practical economical advantage in setting up a PV industry in China with respect to any other US or EU region (Goodrich 2013). This suggests that revitalizing the US or EU industries could be more a question of further supporting the diffusion of photovoltaic energy than of pushing too hard on the innovative character of the PV productions. In this respect, it is perhaps more urgent to find innovative financial schemes, sustainable from the point of view of public spending, and also capable of supporting the expansion of a sector that has become relevant for EU and US industrial and environmental policies, than to pay too much attention to the innovative characteristics of a product that seems, at present, to fully satisfy most market expectations.

References

de la Tour A., Glachant M., and Ménière Y. 2011. Innovation and international technology transfer: The case of the Chinese photovoltaic industry, Energy Policy 39 (2): 761-770.

EPIA Global market outlook for photovoltaics 2013-2017. Available at: http://www.epia.org/fileadmin/user_upload/Publications/GMO_2013_-_Final_PDF.pdf

Eurobarometer 2015. Barometre photovoltaique Eurobserver Avril 2015. Available at : http://eurobserv-er.info/photovoltaic-barometer-2015/

Goodrich A., Hacke P., Wang Q., Sopori B., Margolis R., James T.L., and Woodhouse M. , (2012) A wafer-based monocrystalline silicon photovoltaics road map: Utilizing known technology improvement opportunities for further reductions in manufacturing costs. Solar Energy Materials & Solar Cells 114: 110–135

Goodrich A., Powell D. M., James T. L., Woodhouse M. and Buonassisi T., (2013) Assessing the drivers of regional trends in solar photovoltaic manufacturing. Energy Environ. Sci., 6 : 2811-2821

ISE-Photovoltaic Report, Photovoltaic Report 2014, Ise Fraunhofer, 2014.

McCallum J.C. 2015 Flash Memory Prices (2003-2014). http://www.jcmit.com/index.htm (last accessed june 2015)

Pillai U., Querques N., and Haldar P. 2014 The U.S. Photovoltaic Manufacturing Consortium: Lessons from the Semiconductor Industry. InterPV.net – Global PhotoVoltaic Business Magazine. Available at: http://www.interpv.net/market/market_print.asp?idx=666&part_code=03

 

 

By Peter Connock, chairman of memsstar and co-chair of the European SEMI Secondary Equipment and Applications Special Interest Group

The dramatic shift from the trend for increasingly advanced technology to a vast array and volume of application-based devices presents Europe with a huge opportunity. Europe is a world leader in several major market segments – think automotive and healthcare as two examples – and many more are developing and growing at a rapid rate. Europe has the technology and manufacturing skills to satisfy these new markets but they must be addressed cost effectively – and that’s where the use of secondary equipment and related services comes in.

Secondary Equipment & Applications ─ Enabling the Internet of “Everything”

While Moore’s Law continues to drive the production of advanced devices, the broadening of the “More than Moore” market is poised to explode. All indicators are pointing to a major expansion in applications to support a massive increase in data interchange through sensors and related devices. The devices used to support these applications will range from simple sensors to complex packages but most can, and will, be built by “lower” technology level manufacturing equipment.

This equipment will, in many cases, be required to be “remanufactured” and “repurposed” but will allow semiconductor suppliers to extend the use of their depreciated equipment and/or bring in additional equipment, matched to their process needs, at reduced cost. In many cases this older equipment will need to be supported by advanced manufacturing control techniques and new test and packaging capabilities.

SEMI market research shows that investment in “legacy” fabs is important in manufacturing semiconductor products, including the emerging Internet of Things (IoT) class of devices and sensors, and remains a sizeable portion of the industries manufacturing base:

  • 150mm and 200mm fab capacity represent approximately 40 percent of the total installed fab capacity
  • 200mm fab capacity is on the rise, led by foundries that are increasing 200mm capacity by about 7 percent through to 2016 compared to 2012 levels
  • New applications related to mobility, sensing, and IoT are expected to provide opportunities for manufacturers with 200mm fabs

SEMI_Europe1

Out of the total US$ 27 billion spent in 2013 on fab equipment and US$ 31 billion spent on fab equipment in 2014, secondary fab equipment represents approximately 5 percent of the total, or US$ 1.5 billion, annually, according to SEMI’s 2015 secondary fab equipment market report. For 2014, 200mm fab investments by leading foundries and IDMs resulted in a 45 percent increase in spending for secondary 200mm equipment.

SEMI_Europe2

Establishing a Vibrant and Professional Secondary Equipment Industry in Europe

Secondary equipment will form at least part of the strategy of almost anyone manufacturing or developing semiconductors in Europe. In many cases, it is an essential capability for competitive production. As the secondary equipment industry increases its strategic importance to semiconductor manufacturers and researchers it is critical that the corresponding supply chain ensures a supply of quality equipment, support and services to meet rapidly developing consumer needs. Common challenges across the supply chain include:

  • How to generate cooperation across Europe between secondary equipment users and suppliers and what sort of cooperation is needed?
  • How to ensure the availability of sufficient engineering resource to support the European secondary installed base?
  • Are there shortages of donor systems or critical components that are restricting the use of secondary equipment and, if so, how might this be resolved

Join us at SEMICON Europa to find out more about Europe’s Secondary Industry

Europe’s secondary industry will be in the spotlight during two sessions at SEMICON Europa 2015:

The sessions are organized by the SEMI SEA Europe Group and are open to everyone associated with the secondary industry, be they device manufacturer or supplier, interested in the development of a vibrant industry providing critical support to cost effective manufacturing in Europe.

About the Secondary Equipment and Applications (SEA) Group

The SEA group in Europe is working on activities to:

  • Increase market knowledge
  • Create a European network of relevant customers, suppliers and representative organizations
  • Establish quality and standards in secondary equipment
  • Catalyze Engineering resource development
  • Understand key issues facing the European Secondary industry and any required project activity (e.g., impact of EU laws such as RoHS2, parts supply, etc.)

London, UK and San Jose, California – Dialog Semiconductor and Atmel Corporation announced today that Dialog has agreed to acquire Atmel in a cash and stock transaction for total consideration of approximately $4.6 billion. The acquisition creates a global leader in both Power Management (defined as power management solutions for mobile platforms including smartphones, tablets, portable PCs and wearable-type devices) and Embedded Processing solutions. The transaction results in a company that supports Mobile Power, IoT and Automotive customers. The combined company will address a market opportunity of approximately $20 billion by 2019.

Dialog will complement its position in Power Management ICs with a portfolio of proprietary and ARM (R) based Microcontrollers in addition to high performance ICs for Connectivity, Touch and Security. Dialog will also leverage Atmel’s established sales channels to diversify its customer base. Through realized synergies, the combination could deliver an improved operating model and enable new revenue growth opportunities.

“The rationale for the transaction we are proposing today is clear – and the potential this combination holds is exciting. By bringing together our technologies, world-class talent and broad distribution channels we will create a new, powerful force in the semiconductor space. Our new, enlarged company will be a diversified, high-growth market leader in Mobile Power, IoT and Automotive. We firmly believe that by combining Power Management, Microcontrollers, Connectivity and Security technologies, we will create a strong platform for innovation and growth in the large and attractive market segments we serve. This is an important and proud milestone in the evolution of our Dialog story,” said Jalal Bagherli, Dialog Chief Executive Officer.

“This transaction combines two successful companies and will create significant value for Atmel and Dialog shareholders, customers and employees. Adding Dialog’s world-class capabilities in Power Management with Atmel’s keen focus on Microcontrollers, Connectivity and Security will enable Dialog to more effectively target high-growth applications within the Mobile, IoT and Automotive markets,” said Steven Laub, Atmel President and Chief Executive Officer.

The transaction is expected to close in the first quarter of the 2016 calendar year. In 2017, the first full year following closing, the transaction is expected to be accretive to Dialog’s underlying earnings. Dialog anticipates achieving projected annual cost savings of $150 million within two years. The purchase price implies a total equity value for Atmel of approximately $4.6 billion and a total enterprise value of approximately $4.4 billion after deduction of Atmel’s net cash. Dialog expects to continue to have a strong cash flow generation profile and have the ability to substantially pay down the transaction debt approximately three years after closing.

The transaction has been unanimously approved by the boards of directors of both companies and is subject to regulatory approvals in various jurisdictions and customary closing conditions, as well as the approval of Dialog and Atmel shareholders. Jalal Bagherli will continue to be the Chief Executive Officer and Executive Board Director of Dialog. Two members of Atmel’s existing Board will join Dialog’s Board following closing. The transaction is not subject to a financing condition.

Process Watch: Risky business


September 18, 2015

By Douglas G. Sutherland and David W. Price

Authors’ Note: This is the ninth in a series of 10 installments that explore certain fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights its implications. Within this paper we will use the term inspection to imply either defect inspection or a parametric measurement such as film thickness or critical dimension (CD).

Previous installments have discussed many aspects of process control from general concepts to specific issues related to risk management (see below for links to previous Process Watch articles). In this article we will focus on strategies for managing risk associated with the most difficult steps in the process.

The ninth fundamental truth of process control for the semiconductor IC industry is:

High-Stakes Problems Require a Layered Process Control Strategy

In the IC manufacturing process there are a bewildering number of things that can go wrong and there is a tremendous amount of money at risk. As the margins of error steadily decrease with each new design node, the number of parameters that can wreak havoc on the process continues to rise. The increasing complexity of multiple patterning, pitch splitting and other advanced patterning techniques does nothing to mitigate this problem.

This increased process complexity drives the need for new process control strategies. For example, higher order overlay corrections that were largely unheard of above 45nm are now considered mandatory at 2Xnm and below. Similarly, wafer topography, something that historically was only measured during the manufacture of bare wafers, is now becoming a requirement in IC fabs to accommodate the shallower depth of focus in today’s scanners. For the same reasons, wafer backside and edge inspection are also becoming common practices. The difficulty of some process steps necessitates that they have more than just a single line of defense.

Figure 1 below shows the severity of a potential problem increasing in the horizontal direction and the probability of that problem actually occurring increasing in the vertical direction. In this figure the term “risk” can be thought of as the product of these two attributes – the amount of material impacted (severity) multiplied by the probability of it happening. The severity could increase for a number of reasons: the next inspection point could be many steps downstream from the current step, the process tools at the current step may have very high throughput so that by the time the problem is identified many lots have been exposed to it, or both.

Figure 1. Risk exposure chart with higher severity to the right and higher probability to the top. The problems that require a layered approach to risk management are those in the upper right hand corner where the probability of having a problem is high and the amount of material exposed to that problem is large.

Figure 1. Risk exposure chart with higher severity to the right and higher probability to the top. The problems that require a layered approach to risk management are those in the upper right hand corner where the probability of having a problem is high and the amount of material exposed to that problem is large.

Clearly the safest place to operate is in the lower left corner where both probability and severity are low. However, for process steps that are inherently closer to the upper right hand corner of the chart—high probability and high severity—it often makes sense to have a layered approach to process control in which there is a well thought out back-up plan if the problem is not immediately identified with the first inspection step. Sometimes there are aspects of the problem that are easier to detect later in the process than immediately after the problem step.

Consider the case of forming the first metal layer that wires together the individual transistors. This can be particularly difficult for a number of reasons. The CDs and pitches are aggressive—often at design rules similar to the gate layer. Also, the opportunity for built-in redundancy (multiple vias) is low because there is only one point of contact for each of the transistor connections (source, drain and gate), so every connection has to work.

In such a case it makes sense to have multiple layers of protection, each of which has unique capabilities. For instance, you might perform macro inspection after the photo step to discover any gross defects in the lithography process. There should also be inspection steps after oxide etch, barrier deposition and copper CMP. Having multiple inspection steps ensures the quality of the process throughout the formation of this layer and also helps ensure that you catch problems that originate at one step but may not become apparent until later in the process.

Simply waiting to do a final inspection at copper CMP is usually not sufficient. Doing so will pick up problems in the CMP process but may not allow for distinguishing these from issues that may have originated at an earlier step. Only by inspecting the same wafer at multiple steps are you able to subtract out previous-layer defects and isolate the problem.

Having multiple inspection points has several benefits. It helps identify problems early in the process flow, which significantly reduces the amount of material exposed. A device with 50,000 wafer starts per month has about 1,600 wafer starts per day. Identifying a problem one day sooner can save millions of dollars (depending on the yield loss and wafer cost). Multiple inspection points also help diagnose where the problem occurred and expedite the recovery procedure. Over time, they provide more information about the process allowing for continuous improvement plans that can help reduce not only the severity but also the frequency of problems.

Previous Process Watches:

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Drs. Price and Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

To advance research in nanoscale science, engineering and technology, the National Science Foundation (NSF) will provide a total of $81 million over five years to support 16 sites and a coordinating office as part of a new National Nanotechnology Coordinated Infrastructure (NNCI).

The NNCI sites will provide researchers from academia, government, and companies large and small with access to university user facilities with leading-edge fabrication and characterization tools, instrumentation, and expertise within all disciplines of nanoscale science, engineering and technology.

The NNCI framework builds on the National Nanotechnology Infrastructure Network (NNIN), which enabled major discoveries, innovations, and contributions to education and commerce for more than 10 years.

“NSF’s long-standing investments in nanotechnology infrastructure have helped the research community to make great progress by making research facilities available,” said Pramod Khargonekar, assistant director for engineering. “NNCI will serve as a nationwide backbone for nanoscale research, which will lead to continuing innovations and economic and societal benefits.”

The awards are up to five years and range from $500,000 to $1.6 million each per year. Nine of the sites have at least one regional partner institution. These 16 sites are located in 15 states and involve 27 universities across the nation.

Through a fiscal year 2016 competition, one of the newly awarded sites will be chosen to coordinate the facilities. This coordinating office will enhance the sites’ impact as a national nanotechnology infrastructure and establish a web portal to link the individual facilities’ websites to provide a unified entry point to the user community of overall capabilities, tools and instrumentation. The office will also help to coordinate and disseminate best practices for national-level education and outreach programs across sites.

Funding for the NNCI program is provided by all NSF directorates and the Office of International Science and Engineering.