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ConFab panelists discuss optimizing R&D in the changing semi landscape

June 24, 2014

By Shannon Davis, Web Editor

Overheard @The ConFab: “I feel the best I’ve felt about semi since 2009.” –Mike Noonen, Silicon Catalyst

Monday’s research and development panel discussion at The ConFab 2014 started on that optimistic note as Moderator Scott Jones of AlixPartners led a discussion on Optimizing R&D Collaboration. Panelists Chris Danely of JP Morgan, Lode Lauwers of imec, Rory McInerney of Intel and Mike Noonen of Silicon Catalyst discussed where the next big growth drivers will come from and the ability of the industry to continue scaling and remain on Moore’s Law through the introduction of new technologies such as EUV, Advanced Packaging and 450mm. The panel also touched on the role startups will play and how increased collaboration can benefit the industry.

Here are highlights from Monday’s discussion.

How do you feel about the semiconductor cycle – is that at a positive point for innovation and small, start-up companies?

Mike Noonen: I feel the best about I’ve felt about semi since 2009. Without a doubt. When you combine that situation that we’re in with a couple driving forces, all of that has fundamental benefits to the semiconductor business at large. You take those mega trends that are not leading edge applications with the challenge of Moore’s Law – those are developing a whole host of innovation. We think this is a great time to think about how to reinvigorate startups – this is the best time to think about innovation.

From left to right: Panelists Chris Danely of JP Morgan, Mike Noonen of Silicon Catalyst, Lode Lauwers of imec, and Rory McInerney of Intel

Consolidation is a big theme right now. Is this something that’s holding us back the industry?

Rory McInerney: I don’t think the industry is consolidating for us as much as we think. The big players are still HP, Lenovo, etc. The new players are Google, Facebook, Amazon, etc. – many didn’t exist 10 years ago. Within our world, there’s the traditional space, but there’s a ton of new stuff in the cloud and server segment.

Tell us some of the most exciting areas Intel is participating in.

Rory McInerney: On the data center side, we do want our 10 and 7nm, but one of the drivers of our business is the massive amount of data being generated around the world. There are tens of billions of devices that will be connected to the Internet in the few years. The only commonality in the [IoT] numbers is that they go up. All of them will have some element of connectivity and with that comes data. And that drives a virtual cycle. In our business, we love this – my point is, there’s a huge room for innovation. The innovation isn’t just the device but the software and application side.

How do investors view the emerging markets and trends? Do they see the opportunities or are they still focusing on traditional markets?

Chris Danely: From a broad perspective, the thing that an analyst looks at – are they playing to their strengths? You might have a company that starts out very successful, but they don’t play to their strengths and start to waste money. For example, Texas Instruments has taken their R&D down, but still outgrow the industry, because they play to their strengths. Another example is Intel – in the last 3 years, they were in the foundry business – we see a lot of potential to upset the apple cart in the foundry business. Nobody else could do this, but this is an area where we see them exploiting their strengths. Is the company playing to its strengths? We also look at ARM on servers – we don’t know if this is going to work or not, but I don’t think this changing the landscape of the industry. There’s still a bright future with semiconductor stocks.

How can executives communicate their R&D strategy better?

Chris Danely: I’ll use my personal experience – you want to keep that message very simple. Identify the growth trends. Make sure the message goes out continuously. Don’t be afraid to use a few buzz words/charts.

Lode Lauwers: If I may, Wall Street is looking in the short term. Time scale [for R&D] is close to 15 years. I don’t know if Wall Street has that visibility. I think a company should consider R&D as a long term investment. We go for long term engagements.

Rory McInerney: It’s a portfolio question in terms of R&D – you’re going to have your short term and your long term investments. I don’t think Wall Street is looking at all the details of investments. I think that our investments on the product side go out 10 years, but they’re small compared to our other investments.

Chris Danely: Wall Street has to consider about things on a six month basis.

Mike Noonen: Biotech, which has a very long time to market, is the second largest venture capital in the US. Biotech has remained lucrative and interesting in the US. In this area, companies go after a single application or problem, and it’s a vibrant and healthy investment. The take away is – it’s all about the economics. It might enable small start ups to innovate and then be acquired.

How should the industry leverage a company like imec?

Lode Lauwers: More than ever, you need to build partnerships. In this industry, we used to say, “Our company can work on its own.” Now, your ecosystem needs to become wider. Ten years ago, people were still sponsoring R&D. Now we are assessed in every individual area, deliverable by deliverable, on does it benefit, is there ROI. You need to be able to deliver relevant work. A company on its own doesn’t always have these abilities in house. Using imec, it’s like building on competences.

Do you see differences in how you approach partnerships?

Chris Danely: The CEOs and CFOs of semi companies are under pressure to not increase expenses, and that’s stifled risk-taking. Some are now approaching R&D through acquisition of startups with personnel – rather than partnerships.

Do you think these companies are larger – semi is a part of a much larger landscape – do you think this might drive the industry/change the landscape?

Rory McInerney: About 70-80 percent of cloud computing today is driven by the social media. That didn’t exist 5 years ago. There is a direct link between that and the changing semi landscape.

What is the biggest risk in the industry right now?

Chris Danely: Saturation. Semi companies are profitable, but we’re starting to see a lot of them, especially as fablite and fabless models are catching on.

Moderator Scott Jones of AlixPartners

GS Nanotech pioneers 3D packaging technology in Russia

June 19, 2014

GS Nanotech, microelectronics products development and manufacture center, plans to launch mass assembly of 3D stacked TSV (through-silicon via) microcircuits in next few years. The company does not disclose the total investments in the project, but it will include the cost of hardware, software, and staff training.

GS Nanotech is a part of Technopolis GS, a private innovation cluster of GS Group holding located in Kaliningrad region, Russia. Launched in 2012, it is the only back-end facility in Russia that performs mass packaging and testing of integrated circuits, including multi-chip units built using the SiP (System-in-Package) technology. The production capacity of the plant is enough for GS Nanotech to become the first in Russia to run its services in the global mass market.

Microcircuits, assembled at the facilities, could be used in any consumer or industrial electronics devices. In particular, the GS Lanthanum chip, designed and issued by GS Nanotech, is implemented in GS U510 digital set-top box under the General Satellite brand. U510 became the first mass consumer electronics product with a Russian-made microprocessor built in.

3D packaging would bring the Russian company to the next technological level. It will allow the facility to provide its customers highly integrated chips, packaged with advanced technology that is widely used today by the world leaders of the microelectronics industry. Within 3D TSV integration technology, dice are placed one above another with vertical interconnections between them.

“This method provides such advantages as smaller size of the system, power consumption reduction, and heat dissipation improvement,” noted Sergei Belyakov, GS Nanotech senior marketing manager.

According to the Yole Development forecast, all TSV packaged devices market value will represent nine percent of the total semiconductor value by 2017, hitting almost 39 billion US dollars.

A business model for microcircuits packaging is at an early stage in Russia. Even large Russian microelectronics enterprises assemble chips in small amounts just for domestic needs specializing on the metal-ceramic cases only. Yet the costs of the packaging services contribute a significant share in the microcircuit prime cost. Development of the 3D TSV packaging will open wide opportunities for a new leap of modern technology in Russia. Mass and high quality 3D packaging by local Russian manufacturers will allow using the technology not only for civil, but military and space applications as well. Chips packaging in Russia will simplify logistics, reduce expenditures for the components transportation, so that the Russian customers could get the parts faster and easier. Integrated circuits, packaged in Russia, will become cheaper and more qualitative alternative to Asian components for European customers as well. All these factors combined contribute to the development of Russian electronics as a modern high-tech industry competitive in the global market.

Miniaturization of manufactured consumer electronics devices is a global trend today, and 3D TSV technology development in Russia will allow the domestic industry keep up with the world technological tendencies. The technology will also foster Russian design and production market development of microelectromechanical systems (MEMS), optoelectronics, hybrid power modules, LED, and other innovative products in the electronics industry.

Want more information on these packaging trends? Register for our free Trends in Packaging webcast.

Industry sustainability efforts mount with III-Vs and other advanced technologies

June 12, 2014

By Debra Vogler, SEMI

The introduction of new materials, such as III-Vs, into high-volume manufacturing of semiconductors, likely will occur sometime around the 7nm and/or 5nm nodes. III-V’s introduction, along with the potential transition to 450mm wafers, and the increasing expansion of global regulatory requirements, will heighten environmental, health and safety (EHS) concerns that must be addressed as the industry goes forward. The Sustainable Manufacturing Forum to be held in conjunction with SEMICON West 2014, will feature experts in the manufacture of semiconductors, microelectronics, nanoelectronics, photovoltaics, and other high-tech products.

One of the Sustainable Manufacturing Forum speakers, Richard Hill, Technology Infrastructure manager at SEMATECH, will discuss how the addition of III-V materials into the high-volume manufacture of semiconductors will bring sustainability issues to the forefront, primarily driven by the toxicity of arsenic that is used in much greater quantities in III-V production. Challenges include wastewater treatment, toxic gas detection control and abatement, and the need for robust protocols to ensure operator and maintenance personnel safety. Hill will speak at the Next Generation Eco Fab session on July 9 at SEMICON West.

SEMATECH recently completed a joint study of III-V EHS challenges with the College of Nanoscale Science and Engineering (SUNY CNSE). The assessment consisted of running 300mm wafers through a representative 5nm III-V process flow (Figure 1). (Many semiconductor industry experts agree that III-V materials will enter the process flows in high volumes at 5nm.) Among the processes that will pose the greatest challenges with respect to III-V materials are MOCVD, CMP, wet etch/clean, dry etch, and film deposition. The project was heavily focused on understanding the levels of arsenic that would be present in wastewater, as well as loading of other III-V materials. The impact of III-V outgassing that could occur during processing and the amounts of gases that could be released when a tool is opened for maintenance were of particular interest in the project.

Figure 1. Example 5nm III-V flow: key ESH challenges. SOURCE: SEMATECH

Among the high-level challenges associated with wet etch are the potential for arsine and phosphine outgassing (during processing).

“Wet etch tools are designed to have a controlled environment,” said Hill, “but they are not like high-vacuum systems that are designed to contain toxic gases.” Hill told SEMI that if the exhaust system fails during the processing of a wafer, it is critical to know the risks and ensure mitigation. The SEMATECH/CNSE project looked at a range of different chemistries and identified those that are low risk for arsine and phosphine generation (and therefore, a low risk of outgassing) and those that had a high risk of outgassing. The low risk chemistries are, naturally, the ones that the industry should try to design into a III-V flow.

The joint project also evaluated the III-V loading in wastewater from the wet etch process. “There were measurable quantities of arsenic in the waste stream,” said Hill. Though he added that while the levels weren’t significantly high, some treatment of the waste water would have to be done depending on what’s allowable within local discharge limits and permits. With the industry looking ahead to 5nm and already designing the fabs of the future, Hill believes that these results will be important for specifying wastewater treatment.

The joint SEMATECH/CNSE project also evaluated the wastewater stream from the burn wet scrubber when III-V materials are used in a contact etch (dry) process. The study found measurable arsenic in the wastewater. “Fabs of the future will need wet treatment facilities for arsenic and indium,” Hill told SEMI. “In recent years, concerns about indium have been elevated, and we believe that tighter restrictions on it will be introduced in the future.” Chamber clean is also critical when etching (dry) III-V materials. “If you don’t do the right type of cleaning regimen, you could have next-wafer contamination.” Additionally, without the proper protocol, maintenance personnel could be exposed to arsine or phosphine when the chamber is opened, depending on the process. The cleaning protocol is highly dependent on the type of etch being done, and each type could have different requirements.

For Hill, the key takeaway from the joint evaluation was that, while there are risks when processing III-V materials, there are no showstoppers — solutions can be engineered. “People should take these risks seriously, but they shouldn’t be scared off by them,” said Hill.

Sustainability and the Role of Collaboration and Standards

Steve Moffatt, CTO, Front-end Equipment at Applied Materials (also a speaker at the Next Generation Eco Fab session at the Sustainable Manufacturing Forum at SEMICON West), told SEMI that many established procedures for dealing with arsine and phosphine already exist. He views the efforts by the industry going forward as one of accurately quantifying the size and scope of the problem. “The methods are in place, but the absolute quantities of III-Vs will be substantially higher,” said Moffatt.

Additionally, other emissions (e.g., PFCs) that are well regulated and generally understood, will see an increase in the quantities as a result of more layers being processed for 3D chips. Even the potential transition to 450mm wafers will figure into the industry’s need for a more accurate scope of the EHS challenges involved. The increase in wafer size will naturally lead to larger manufacturing equipment noted Moffatt and that, in turn, will drive increases in energy, water, and process chemical consumption at both the tool and fab levels.

As regulatory pressure increases on a global scale, the situation also becomes more complex. Beyond the use of new materials such as III-Vs and nanomaterials, Moffatt commented that new methods of energetics (i.e., ways of putting energy into a processing system) will require very careful and close assessment of the risk control measures. Another sustainability issue arises from the basic fact that, as opposed to the highly prevalent element of silicon in the earth’s crust, many of the newer materials being used in higher quantities for semiconductor manufacturing (e.g.,Ga, As, etc.) are much less abundant. These exotic materials, of necessity, must be handled in the most efficient of ways.

Going forward, there will be increased regulatory pressure to reduce a fab’s carbon footprint and produce more sustainable products. Moffatt says the industry can expect more pressure to reduce greenhouse gas (GHG) emissions along with adhering to conflict minerals regulations and managing EHS concerns throughout the entire life-cycle of a product (Figure 2). “One company can’t do it on its own, it’s a life-cycle consideration,” said Moffatt. “If we have the right collaboration together, we have a greater probability with the right kinds of standards of bringing good, effective green chemistry solutions to high-value problems.”

Figure 2. Consensus building in multi-stakeholder life-cycle risk assessment of manufacturing technology and products. SOURCE: Applied Materials (used with permission of ITRS)

Regarding standards activities on energetics, Moffatt pointed to ongoing collaboration and hazard assessment between SEMI, SEMATECH and other industry groups.

“We will need to continually evaluate the need for additional standards activities — both new and updates — in addition to industry collaboration on “Green” chemistry,” said Moffatt. “As a starting point, sustainability concerns could be built into the initial assessment of new chemicals and processes, which will begin the discussion and raise awareness of these issues.”

Hill (SEMATECH) and Moffatt (Applied Materials) will be joined by speakers from IMEC, Intel, Samsung, Air Products, and MW Group at the “Next Generation Eco Fab” session of the Sustainable Manufacturing Forum at SEMICON West 2014, July 7-10 in San Francisco, Calif. For more information, visit: http://www.semiconwest.org.

SID announces winners of 2014 Display Industry Awards

June 4, 2014

Yesterday, the Society for Information Display (SID) unveiled the winners of its prestigious 19^th annual Display Industry Awards. These are the display industry’s most coveted awards, and the honorees will be recognized during a special luncheon tomorrow, Wed., June 4, as part of Display Week 2014, which is taking place this week at the San Diego Convention Center.

Research and innovation continue to be alive and well, and this past year was no exception given the caliber of nominated candidates. The six winners, two in each of three main categories, were chosen by a distinguished panel of experts who evaluated the nominees for their degree of technical innovation and commercial significance, in addition to their potential for positive social impact.

It is notable that three of this year’s winners are curved devices, and two of the winners are materials that support flexible devices, signaling that the “flat” in flat panel displays may be a thing of the past. Four of the six winners are also OLED-based, while the debut of the internet giant, Google, in this year’s award race reminds that LCDs are still here to stay. The winning products and a brief description of each are listed below. A more comprehensive description of the award winners is included in the Display Week 2014 Show Issue of Information Display magazine.

Display of the Year: Granted to a display with novel and outstanding features such as new physical or chemical effects, or a new addressing method

Gold Award Winner: Samsung Display’s 5.68-in. Curved (Flexible) AMOLED Display

The Samsung 5.68-in. FHD curved AMOLED display represents a major milestone for the entire display industry, as it’s the world’s first truly flexible full-fidelity display technology to be mass produced and adapted for use in a mass-market product. Now being produced on a plastic substrate, the new Samsung display panel enables smartphones such as the Samsung Galaxy Round to be curved, significantly improving a user’s grip. Smartphone users will be able to comfortably hold a larger-screen version of the panel with just one hand. The smartphone has a curvature of 400 mm, while human hands have a natural curvature of about 300-500 mm. Also, the display enables a more visually immersive mobile experience with a “landscape” view aspect ratio of 1.88:1, comparable to the Vista Vision technology (1.83:1) now used in most movie theaters. In addition, the curved screen is more readable thanks to a significant reduction in light reflectance. Samsung’s new curved display will later evolve into bendable and foldable displays that will further revolutionize the use of smartphones and other mobile-product form factors.

Silver Award Winner: LG Display’s 55-in. FHD Curved OLED TV Panel

LG’s 55-in. FHD curved OLED TV panel offers exceptionally vibrant imagery in a curved format that offers viewers a comfortably immersive environment. LG’s curved OLED TV was introduced last year, and uses the company’s WRGB OLED technology with an oxide TFT backplane, the company’s technical solution of choice for large-sized OLED panels. The panel is slim – only 4 mm thick with side bezel widths of 11 mm. At 19.2 pounds, the TV is also substantially lighter than competitive products. At the same time, it offers superior picture quality, achieving remarkably rich and natural colors. In addition to the vivid and enhanced picture-quality experience, the curved structure of the new OLED TV panel offers viewing comfort. The curvature mimics a human’s normal line of vision, which makes it more eye friendly and allows viewers to feel less fatigue even when watching the screen, while also allowing for a wider and brighter field of view.

Display Component of the Year: Granted for a novel component (sold as a separate part and incorporated into a display) that has significantly enhanced a display’s performance. A component may also include display-enhancing materials and/or parts fabricated with new processes

Gold Award: UDC’s Green Phosphorescent UniversalPHOLED Emitter Material

Universal Display Corporation’s (UDC’s) proprietary green phosphorescent OLED (PHOLED) emissive system can reduce an OLED display’s power consumption by approximately 25 percent, while providing excellent color in mobile displays. Adding green PHOLEDs to displays has increased OLED’s competitiveness with LCDs for mobile applications. This new material is expected to be a key driver in the commercialization of OLED TVs as well as OLED lighting. Through years of R&D work and achievements, UDC has produced UniversalPHOLED materials that provide record-breaking energy efficiencies, vibrant colors, long operating lifetimes and manufacturing versatility. The green PHOLED emitter builds on the successful commercialization of UDC’s red UniversalPHOLED emitter, first launched in commercial passive-matrix display products in 2003. PHOLED materials are expected to drive wider adoption of OLED technology and greater growth in the display and lighting markets because they significantly reduce power consumption and lower heat emission compared to prior fluorescent OLED materials.

Silver Award: Canatu Oy’s Carbon NanoBud (CNB) Film

Canatu Oy’s Carbon NanoBud (CNB) Film, made from carbon nanotubes and fullerenes, provides superior optical performance for flat, flexible, or formable touch screens, displays and touch-sensitive surfaces. This transparent conductive film is used in capacitive touch sensors for portable devices such as mobile phones, tablets, and digital cameras, and in automobiles that require excellent display readability in outdoor and bright indoor environments. CNB Films are also applied in capacitive touch sensors for flexible or formable devices such as smart watches, flexible and foldable mobile phones and tablets, and automobile center consoles.

Display Application of the Year: Granted for a novel and outstanding application of a display, where the display itself is not necessarily a new device

Gold Award: LG Display’s G Flex

LG Display’s G Flex smartphone incorporates a flexible OLED panel that is based on a plastic substrate instead of glass. By applying film-type encapsulation technology and attaching the protection film to the back of the panel, LG Display made the panel bendable and unbreakable. Compared to an OLED display panel based on glass, the flexible OLED panel is lightweight, thin and features design flexibility. This allows for a design that naturally fits the contour of a smartphone user’s face. What’s more, the panel is also the world’s lightest, weighing a mere 7.2 grams, even with a 6-in. screen, the largest among current smartphone OLED displays. In the future, LG plans to use this process applicable for the production of large-sized devices, including laptops, monitors and TVs, as well as eReaders and more.

Silver Award: Google Chromebook Pixel

Chromebooks are built for the way that people use computers and the web today. They make computing faster, simpler and more secure – for everyone. The LCD on the Chromebook Pixel is stunning, providing users with a rich, immersive experience. The 12.85-in. touch screen had, at launch, the highest pixel density of any laptop (239 ppi), and the 3:2 photographic format is specifically designed for using the web by reducing the need for scrolling. For users, text is crisp, colors are vivid, touch interactions are smooth – and each of the 4.3 million pixels seems to disappear into one spectacular picture. Google used amorphous silicon (a-Si) TFT technology for the pixel to reduce the cost of the glass panel. The transmissivity of its high-ppi a-Si TFT panel was lower than panels fabricated with oxide transistors or low-temperature polysilicon. To attain low-power consumption using a-Si, the company optimized the remaining components (including LEDs, optical films, and light pipe). The company’s goal is to continue to push the laptop experience forward, working with its entire ecosystem of partners to build the next generation of Chrome OS devices.

The 51^st SID International Symposium, Seminar and Exhibition, or Display Week 2014, will take place June 1-6, 2014 at the San Diego Convention Center in San Diego, Calif. Display Week is an international gathering of scientists, engineers, manufacturers and users in the field of electronic information displays.

Down to 5nm: Scaling with the usual suspects – performance, cost

May 29, 2014

By Debra Vogler, SEMI

The semiconductor industry never lacks for challenges and/or controversy as it forges ahead from one technology node to the next. “Lithography is always a challenge,” observes Dick James, senior technology analyst at Chipworks. While there may be a non-EUV roadmap to 7nm, what will happen by 5nm is not so clear, except “by the time the industry gets to 5nm, silicon will have run out of steam,” said James. His recitation of the coming mountains to climb is extensive: integration of new materials, contact resistance of ever-smaller contacts, pitch quartering, contact etch and self-aligned vias, shrinking the gate stack, and modifying work function materials. And that’s just the front-end!

“The big divide at the moment is FDSOI vs FinFET,” James told SEMI. “If IBM survives, I could see them following the FDSOI route, but the rest of the industry seems to be going FinFET. By the time we get to 7nm and 5nm it will likely be moot, we’ll have to do something else such as nanowires…in the end, it all boils down to performance vs. cost.”

With respect to performance and scaling, Soitec’s SVP of Digital Electronics Division and FDSOI guru Christophe Maleville, a clear proponent of SOI-based technology, told SEMI that a key challenge is delivering a worthwhile performance increase while allowing very low energy consumption. “In the PC era, performance was king,” observed Maleville, who will speak at SEMICON West 2014. “Although power consumption was obviously a concern, it was okay to trade GHz for high leakage current. With the advent of the mobile, always-on device era, the weights of priorities have shifted.” With mobile applications driving the industry, performance must also take into account low heat dissipation and battery life. “Delivering high drive current is one thing – and FinFET appears to be pretty good at that – but this has to be weighed against the other parameters that affect the actual in-application performance of the chip.”

Medium-term, i.e., down to the 10nm node, Maleville said that while there is a choice in transistor technology between FDSOI and FinFET, the latter has its challenges (Figure 1). At 14nm and below, particularly for bulk silicon, Maleville cites issues such as controlling substrate leakage and maintaining good variability. “In addition, because of its 3D architecture, parasitic capacitance of the FinFET device is relatively high and scaling means reducing the pitch into which FinFET transistors need to fit, which does not go in the direction of limiting (fringe) parasitic capacitance” said Maleville. “Beyond 14nm, these challenges will become even more pressing.” Doing FinFET on SOI can help alleviate some of these challenges because it offers intrinsic isolation under the fin, thereby removing the need for a complex-to-optimize punch-through stopper junction. “It also eliminates some variability associated with the doping this junction requires.” FinFET on SOI also aids in the manufacture of fins with well-defined height, “therefore, ensuring no excessive variability from fin geometry fluctuations.”

Fig. 1

FDSOI technology is not without its own set of challenges. “The electrostatic control of an FDSOI transistor is, in principle, not as good as that of a multi-gate device,” Maleville explained. “On the other hand, FDSOI is less subject to some of the pains associated with scaling FinFETs, such as keeping parasitic capacitance low enough, or keeping variability (including that originating from transistor geometry variations) under control.” Figure 2 illustrates the value that using SOI brings (for FD-2D technology) in terms of silicon geometry control and uniformity.

Fig. 2

With respect to scaling FDSOI technology to 14nm, Maleville noted that excellent results were reported at IEDM 2013 and that both Leti and STMicroelectronics are showing roadmaps to scale FDSOI down to 10nm, with introduction of Ge in the channel, along with further source/drain optimization and the option to use strained SOI. With respect to starting SOI wafers, the key areas of work already underway according to Maleville are: 1) ensuring excellent thickness uniformity of the thin silicon layer, which needs to be improved from one node to the next; 2) reducing the thickness of the buried oxide from one node to the next, and 3) continuing to provide ultra-thin layers of top silicon with state-of-the-art defectivity required at each node.

Industry experts interviewed on the topic of scaling are in agreement about new device architectures (e.g., gate-all-around, nanowires, tunnel FET, etc.) along with new materials (e.g., Ge and III-V compound semiconductors). Regarding the introduction of new materials, Maleville notes that the following will have to be considered: 1) demonstrating at the device level that there is a CMOS solution based on the new materials that deliver better results than silicon in the power supply and geometrical dimension ranges envisaged for the 7nm-5nm nodes, and 2) finding a way to implement Ge or a III-V material of suitable quality for good transistor behavior. “The Smart Cut layer transfer technology employed to fabricate SOI wafers has a role to play here,” said Maleville. “In particular, transferring germanium or III-V materials onto an oxidized silicon base (i.e., doing GeOI or III-V.OI) can be an interesting alternative to epitaxial growth of these materials on a bulk substrate.”

Because of lattice mismatch, Maleville further explained that epitaxial growth of Ge or III-V on silicon is challenging and achieving decent material quality is difficult. Though the alternative approach of Smart Cut-based layer transfer comes with its own set of challenges (defectivity, etc.), “it has the advantage of allowing the slice of a high-quality layer from a donor that can have defects outside the transferred layer, and the ability for this donor to be recycled multiple times.”

Enter CNTs

While the industry winds its way through the myriad choices of lithography technologies, transistor architectures, and materials choices, experts note that once the industry gets to 5nm, something new will have to happen. One technology getting close scrutiny is carbon nanotube (CNT) logic transistors. H.S. Philip Wong, the Willard R. and Inez Kerr Bell Professor in the School of Engineering and Professor of Electrical Engineering at Stanford University, told SEMI that transistors made with carbon nanotubes as the channel material hold special promise. The promise is due to the ultra-thin body of the carbon nanotube being only about one nanometer, while at the same time retaining excellent carrier transport properties. “No other bulk semiconductor has this unique advantage that allows the carbon nanotube transistor to scale to the shortest possible gate length,” said Wong (Figure 3).

Fig. 3

The key issues in bringing CNT logic transistors to the forefront, noted Wong, include: 1) contact resistance (reducing the transfer length of the contact); 2) maintaining good carrier transport while meeting electrostatic requirements; 3) having a coordinated effort in industry (as exemplified by how the semiconductor industry solved the high-k/metal gate problem); and 4) taking a practical approach and recognizing that exotic, non-FET-based devices will not meet the time line of the industry for the 5nm node.

Recent developments of CNT transistor technology for digital logic include the synthesis of fully aligned carbon nanotubes on a wafer scale, device fabrication of high-performance carbon nanotube transistors, 3D integrated carbon nanotube circuits, low voltage (0.2 V) operation of carbon nanotube transistors, and compact models for circuit simulation. Performance benchmarking of carbon nanotube transistors with conventional CMOS at the device and the full-chip processor level have also been accomplished, along with the demonstration of circuits and complete systems.

Interested in learning more about the industry getting down to the 5nm node? Come hear from Soitec, imec, Intermolecular, GLOBALFOUNDRIES, SEMATECH, Stanford University, and G450C at the SEMICON West 2014 Semiconductor Technology Symposium (STS) session titled “Getting to 5nm Devices: Evolutionary Scaling to Disruptive Scaling and Beyond.” For information about this program, the agenda or pricing, please visit www.semiconwest.org/sts. SEMICON West 2014 will be held July 8-10 at the Moscone Center in San Francisco.

Increase in first quarter 2014 silicon wafer shipments

May 20, 2014

Worldwide silicon wafer area shipments increased during the first quarter 2014 when compared to fourth quarter 2013 area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

Total silicon wafer area shipments were 2,364 million square inches during the most recent quarter, a 7.1 percent increase from the 2,208 million square inches shipped during the previous quarter. New quarterly total area shipments are 11.1 percent higher than first quarter 2013 shipments.

“Total silicon shipment volumes registered first quarter growth, with volumes also up relative to the same quarter last year,” said Hiroshi Sumiya, chairman of SEMI SMG and general manager of the Corporate Planning Department of Shin-Etsu Handotai Co., Ltd. “This growth at the start of the year is in-line with other semiconductor industry data showing improved conditions compared to the start of 2013.”

Quarterly Silicon Area Shipment Trends

	Millions Square Inches
	Q1 2013	Q4 2013	Q1 2014
Total	2,128	2,208	2,364

Semiconductor Silicon Shipments* — Millions of Square Inches

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers, epitaxial silicon wafers, and non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

The Silicon Manufacturers Group acts as an independent special interest group within the SEMI structure and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.

New policy helps combat counterfeit semiconductors

May 14, 2014

A newly finalized Department of Defense (DoD) rule reduces the risk of counterfeit semiconductor products being used by our military by implementing needed safeguards in the procurement of semiconductors and other electronic parts. The final DoD rule addresses contractor responsibilities for detection and avoidance of counterfeit electronic parts. Among other provisions, the rule implements section 818 of the National Defense Authorization Act (NDAA) for fiscal year 2012, which calls for DoD to utilize trusted suppliers to mitigate the risks of counterfeits.

“Counterfeit semiconductor products can end up in critical consumer, industrial, medical, and military devices, potentially undermining our public safety and national security,” said Brian Toohey, president and CEO, Semiconductor Industry Association. “The new Department of Defense rule will help stem the tide of dangerous counterfeit semiconductor products by mandating that DoD contractors purchase from original manufacturers or authorized sources. This rule represents a long fought victory for the semiconductor industry and a significant step toward ensuring the safety and security of semiconductor products used by our military.”

While the proposed rule issued last year contained numerous issues of concern for the semiconductor industry, the final rule incorporates many improvements called for by SIA in comments filed last year. The final rule requires contractors and their subcontractors to establish a counterfeit electronic part and avoidance system, subject to audit, that includes procedures to show their use of original manufacturers, authorized distributors, or authorized aftermarket distributors prior to turning to other outlets. Additionally, the rule further strengthens flowdown requirements to subcontractors called for by SIA and subjects violators of the requirements within the rule to disapproval of their purchasing system and/or potential withholding of payments by DoD.

SIA has long advocated for measures to stop the dangerous proliferation of counterfeit semiconductor products. Counterfeiters often “harvest” semiconductor components from old circuit boards and then re-mark them to indicate they are new or that they have better performance than the original components. These counterfeit semiconductors, which may be indistinguishable from authentic semiconductors, are then sold through a network of international brokers, posing a risk to critical end products. For more information, see SIA’s anti-counterfeiting whitepaper.

“By working together to implement common sense policies like this DoD rule, we can win the fight against counterfeit semiconductor products and help ensure the safety of technologies that are vital to America’s economic and national security,” said Toohey.

SEMATECH achieves breakthrough defect reduction in EUV mask blanks

May 6, 2014

SEMATECH announced today that researchers have reached a significant milestone in reducing tool-generated defects from the multi-layer deposition of mask blanks used for extreme ultraviolet (EUV) lithography, pushing the technology another significant step toward readiness for high-volume manufacturing (HVM).

Following a four-year effort to improve deposition tool hardware, process parameters and substrate cleaning techniques, technologists at SEMATECH have, for the first time, deposited EUV multilayers with zero defects per mask at 100nm sensitivity (SiO2 equivalent). Eliminating these large “killer” defects is essential for the use of EUV in early product development. These results were achieved on a 40 bi-layer Si/Mo film stack and measured over the entire mask blank quality area of 132×132 mm2.

In addition, by subtracting out incoming substrate defects, SEMATECH has demonstrated that the multilayer deposition process itself can achieve zero defects down to 50nm sensitivity. Coupled with novel improvements to the mask substrate cleaning process to remove incoming defects, this represents the capability to both extend EUV to future nodes by eliminating smaller “killer” defects, and as a step to reducing smaller defects (which can be mitigated) to a level where improved yield and mask cost make EUV a more cost-effective HVM technology.

“SEMATECH’s comprehensive programs continue to produce the results that our members and the industry need to show that EUV lithography is manufacturable,” said Kevin Cummings, SEMATECH’s Lithography manager. “Our Advanced Mask Development program continues to demonstrate practical results for mask blank defect reduction, more efficient deposition and cleaning, effective reticle handling, and other areas that the industry will need for successful EUV lithography manufacturing.”

Defects are generally created by the deposition process or formed by decoration of substrate defects during the multilayer deposition process. These types of defects have prevented the quality of mask blanks from keeping pace with roadmap requirements for the production of pilot line and high-volume manufacturing EUV reticles. Reducing defects in the EUV mask blank multilayer deposition system is one of the most critical technology gaps the industry needs to address to enable cost-effective insertion of this technology at the 16nm half-pitch.

“A low defect density reflective mask blank is considered to be one of the top two critical technology gaps for the commercialization of EUV,” said Frank Goodwin, manager of SEMATECH’s Advanced Mask Development program. “Through sophisticated defect analysis capabilities and processes, the goal of our work is to enable model-based prediction and data-driven analysis of defect performance for process improvement and component learning. We then use these models to feed into the new deposition tool design.”

Sensor hubs make big gains while enabling the future of sensing

April 30, 2014

Sensor hubs that offload tasks from power-hungry application processors and let mobile devices like smartphones and tablets run longer on a single battery charge are reaping gargantuan gains thanks to the global microelectromechanical systems (MEMS) market, with shipment growth this year alone in triple-digit territory, according to new analysis from IHS Technology.

Worldwide shipments of sensor hubs in 2014 will reach a projected 658.4 million units, up 154 percent from 259.6 million units last year. The market has been on a tear since 2011, when shipments first started from a low initial base. The 2012 growth rate, for instance, exceeded 2,000 percent.

From then until 2017, the market is pegged to increase 1,300 percent to shipments of 1.3 billion units, as shown in the figure below.

“A sensor hub is a low-power processor that can be used to perform calculations on data from sensors, the hub thereby saving power on a device by off-loading such tasks from the power-intensive application processor,” said Marwan Boustany, senior analyst for MEMS & sensors at IHS. “The use of sensor hubs is increasingly crucial because of the push for ‘always on’ sensors used for activity monitoring, voice-command operation and contextual awareness.”

Most of sensor processing today is performed by software running on an application processor, but this approach is too power hungry when sensor processing must continuously run in the background. With rising use by handsets and tablets of sensors—not just motion sensors but also microphones and light sensors—the need for a low-power solution becomes crucial.

By centralizing sensor processing in a more efficient way through sensor hubs, power usage and battery life are optimized, Boustany added.

These findings are contained in the report, “Motion Sensors Report – Handsets and Tablets – 2014,” from the Semiconductor & Components service of IHS.

Sensor formats vie to deliver maximum benefits

The centralized processing in a sensor hub is typically achieved via three different approaches, each with its own advantages along with specific tradeoffs in cost or performance.

One approach employs an external hub, typically a dedicated microcontroller (MCU), as offered by the likes of chip makers such as Atmel, STMicroelectronics, Texas Instruments and NXP Semiconductor. Recent smartphones that use this approach include the Apple iPhone 5s, Samsung Galaxy S5 and the Motorola Moto X.

Catching the (invisible) wave

April 11, 2014

In a feat that may provide a promising array of applications, from energy efficiency to telecommunications to enhanced imaging, researchers at UC Santa Barbara have created a compound semiconductor of nearly perfect quality with embedded nanostructures containing ordered lines of atoms that can manipulate light energy in the mid-infrared range. More efficient solar cells, less risky and higher resolution biological imaging, and the ability to transmit massive amounts of data at higher speeds are only a few applications that this unique semiconductor will be able to support.

“This is a new and exciting field,” said Hong Lu, researcher in UCSB’s Department of Materials and Department of Electrical and Computer Engineering, and lead author of a study that appears as a cover story of the March issue in the journal Nano Letters, a publication of the American Chemical Society.

[Right: Artist’s concept of nanometer-size metallic wires and metallic particles embedded in semiconductors, as grown by Dr. Hong Lu. Credit: Peter Allen, UCSB]

Key to this technology is the use of erbium, a rare earth metal that has the ability to absorb light in the visible as well as infrared wavelength — which is longer and lower frequency wavelength to which the human eye is accustomed — and has been used for years to enhance the performance of silicon in the production of fiber optics. Pairing erbium with the element antimony (Sb), the researchers embedded the resulting compound — erbium antimonide (ErSb) — as semimetallic nanostructures within the semiconducting matrix of gallium antimonide (GaSb).

ErSb, according to Lu, is an ideal material to match with GaSb because of its structural compatibility with its surrounding material, allowing the researchers to embed the nanostructures without interrupting the atomic lattice structure of the semiconducting matrix. The less flawed the crystal lattice structure of a semiconductor is, the more reliable and better performing the device in which it is used will be.

“The nanostructures are coherently embedded, without introducing noticeable defects, through the growth process by molecular beam epitaxy,” said Lu. “Secondly, we can control the size, the shape and the orientation of the nanostructures.” The term “epitaxy” refers to a process by which layers of material are deposited atom by atom, or molecule by molecule, one on top of the other with a specific orientation.

“It’s really a new kind of heterostructure,” said Arthur Gossard, professor in the Materials Department and also in the Department of Electrical and Computer Engineering. While semiconductors incorporating different materials have been studied for years — a technology UCSB professor and Nobel laureate Herbert Kroemer pioneered — a single crystal heterostructured semiconductor/metal is in a class of its own.

The nanostructures allow the compound semiconductor to absorb a wider spectrum of light due to a phenomenon called surface plasmon resonance, said Lu, and that the effect has potential applications in broad research fields, such as solar cells, medical applications to fight cancer, and in the new field of plasmonics.

Optics and electronics operate on vastly different scales, with electron confinement being possible in spaces far smaller than light waves. Therefore, it has been an ongoing challenge for engineers to create a circuit that can take advantage of the speed and data capacity of photons and the compactness of electronics for information processing.

The highly sought bridge between optics and electronics may be found with this compound semiconductor using surface plasmons, electron oscillations at the surface of a metal excited by light. When light (in this case, infrared) hits the surface of this semiconductor, electrons in the nanostructures begin to resonate — that is, move away from their equilibrium positions and oscillate at the same frequency as the infrared light — preserving the optical information, but shrinking it to a scale that would be compatible with electronic devices.

In the realm of imaging, embedded nanowires of ErSb offer a strong broadband polarization effect, according to Lu, filtering and defining images with infrared and even longer-wavelength terahertz light signatures. This effect can be used to image a variety of materials, including the human body, without the risk posed by the higher energies that emanate from X-rays, for instance. Chemicals such as those found in explosives and some illegal narcotics have unique absorption features in this spectrum region. The researchers have already applied for a patent for these embedded nanowires as a broadband light polarizer.

“For infrared imaging, if you can do it with controllable polarizations, there’s information there,” said Gossard.

While infrared and terahertz wavelengths offer much in the way of the kind of information they can provide, the development of instruments that can take full advantage of their range of frequencies is still an emerging field. Lu credits this breakthrough to the collaborative nature of the research on the UCSB campus, which allowed her to merge her materials expertise with the skills of researchers who specialize in infrared and terahertz technology.

“It’s amazing here,” she said. “We basically collaborated and discovered all these interesting features and properties of the material together.”

“One of the most exciting things about this for me is that this was a ‘grassroots’ collaboration,” said Mark Sherwin, professor of physics, director of the Institute for Terahertz Science and Technology at UCSB, and one of the paper’s co-authors. The idea for the direction of the research came from the junior researchers in the group, he said, grad students and undergrads from different laboratories and research groups working on different aspects of the project, all of whom decided to combine their efforts and their expertise into one study. “I think what’s really special about UCSB is that we can have an environment like that.”

Since the paper was written, most of the researchers have gone into industry: Daniel G. Ouelette and Benjamin Zaks, formerly of the Department of Physics and the Institute for Terahertz Science and Technology at UCSB, now work at Intel and Agilent, respectively. Their colleague Justin Watts, who was an undergraduate participant is now pursuing graduate studies at the University of Minnesota. Peter Burke, formerly of the UCSB Materials Department, now works at Lockheed Martin. Sascha Preu, a former postdoc in the Sherwin Group, is now assistant professor at the Technical University of Darmstadt.

Researchers on campus are also exploring the possibilities of this technology in the field of thermoelectrics, which studies how temperature differences of a material can create electric voltage or how differences in electric voltages in a material can create temperature differences. Renowned UCSB researchers John Bowers (solid state photonics) and Christopher Palmstrom (heteroepitaxial growth of novel materials) are investigating the potential of this new semiconductor.