July 18, 2012 — Semiconductor packaging company STATS ChipPAC Ltd. (SGX-ST:STATSChP) presented its annual Supplier Awards to its top supplier partners for their excellent performance and outstanding support in 2011. Supplier partners are scored on technology, quality, delivery, responsiveness, service, and cost competiveness criteria.
More supplier awards from 2011:
Texas Instruments (TI, TXN) names top suppliers
July 17, 2012 — Sonoscan unveiled its Lab Model 9600 C-SAM acoustic micro imaging system to serve laboratory/failure analysis applications and for use in low-volume semiconductor production inspection.
Model 9600 incorporates advanced Sonolytics software with a graphical user interface (GUI). PolyGate analysis software for multilayer or bulk materials analysis is standard. PolyGate permits the user to set up to 100 individual gates per channel for a sample. During a single scan, PolyGate produces a separate acoustic image for each gate. Depending on the material, each gate may be as thin as 20µm.
The 9600 is tailored for high-performance laboratory acoustic microscopy for budget-conscious users.
The 9600 uses a linear motor for X-axis scanning, a tower-mounted scan reference platform, and is rated for Class 1000 cleanroom operation. It has a portfolio of optional features available.
Also read: Sonoscan software enables acoustic imaging of 3D IC and die stacks
Sonoscan makes acoustic microscopes and sophisticated acoustic micro imaging systems, widely used for nondestructive analysis of defects in industrial products and semiconductor devices. Internet: www.sonoscan.com.
July 16, 2012 — Since the early 19th century, quartz crystals have been the core frequency reference for oscillators. However, due to the manufacturing complexity and reliability challenges posed by crystal oscillators, a great deal of work is going on in the industry and academia to find alternate frequency reference solutions. To overcome the known technical challenges for quartz crystals, including limitations on higher native frequencies, activity dips, aging, vibration sensitivity, etc., IDT recently introduced piezoelectric micro electro mechanical system (pMEMS) resonator-based oscillators. pMEMS resonators have a higher native frequency (~100 MHz) than quartz crystals and enable better-performing MEMS oscillators (sub-ps jitter), especially for high-performance communications, consumer, cloud, and industrial applications.
As part of higher reliability over quartz, MEMS oscillators demonstrate semiconductor-grade shock and vibration resistance. Standard quartz devices are fragile, since the crystal is housed within a metal or a ceramic package, allowing the crystal to be fractured by a shock of 50-100g. Manufacturers have to implement specific storage, packing, and shipping protocol for crystal devices to avoid damage. MEMS oscillators, on the other hand, sport a 50,000g shock resistance without special construction, packaging, and transportation techniques.
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| Figure 1. Wafer level packaged pMEMS die stacked on an IC Die in a plastic QFN package. |
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| Figure 2. A typical quartz oscillator in a ceramic package. |
Since the MEMS resonators are wafer-level packaged, these oscillators can use low-cost plastic packages, which provide an economical yet reliable timing component.
Another known issue for crystal oscillators — activity dips — can cause intermittent failures. These failures affect both the frequency and the resistance (i.e., the Q) of crystal resonators. Activity dips are usually caused by interfering modes (e.g., by high overtone flexure modes) and are strongly influenced by the crystal’s drive level and load reactance. These activity dips are not present with MEMS oscillators since the resonators are designed to suppress undesired modes over these temperature and process variations that can impair crystal-based oscillators.
pMEMS oscillators have also demonstrated aging comparable with crystal oscillators at room temperature (25°C) and significantly better aging than crystal oscillators under burn-in conditions (125°C).
Other advantages of MEMS-based products include natural compatibility with surface-mount assembly processes and short lead times; this enables suppliers and users (electronic manufacturers) to maintain a smaller device inventory with reduced risk of supply shortages.
IDT’s MEMS oscillators support low-voltage differential signaling (LVDS) and low-voltage positive emitter-coupled logic (LVPECL) outputs at frequencies of up to 625MHz, which is required in most communications, networking and high-performance computing applications.
Conclusion
There have been a lot of improvements in MEMS oscillators over the years, and the recent upgraded products, like IDT’s 4M MEMS oscillators, are ready to provide the performance and accuracy required in the high-performance communications, consumer, cloud computing, and industrial applications. In the foreseeable future, researchers, designers, an
d manufacturers will continue to work together to enhance the MEMS oscillators to deliver more accurate, cost-effective, and higher performance frequency reference products.
Harmeet Bhugra, managing director, Integrated Device Technology Inc., is responsible for the vision, growth and general management of the MEMS business. Bhugra holds a Bachelor of Engineering degree from University of Victoria, Canada, Masters in Systems Engineering and MBA degrees (Magna Cum Laude) from San Jose State University and Managing Technical Organization certifications from MIT.
Visit the MEMS Channel of Solid State Technology, and subscribe to our MEMS Direct e-newsletter!
July 16, 2012 — The price of a light-emitting diode (LED) bulb will fall by about half by 2020, hitting $11.06, according to Lux Research. With the LED chip package seeing 70%+ cost reduction, technology innovation will shift to the surrounding “balance of system” elements — thermal management, drivers and optics — to push costs lower.
Costs of the central LED chip package will fall by more than 70% to $2.14 in the next decade, but this makes up just 19% of the bulb costs in 2020. To drive overall costs lower, the related system elements will need to see similar cost reductions.
Read about blogger Dr. Phil Garrou’s costs saving analysis of an LED bulb in Bidding Adieu to Lester Lightbulb and Lester the Lightbulb vs CFL and LED : the Saga Continues
“We find that today’s balance of system technology solutions fall short of the dramatic cost reductions needed to mirror the LED package,” said Pallavi Madakasira, Lux Research Analyst, adding that existing alternatives are ineffective and uneconomical.
Lux Research analysts studied the key LED cost stack components of a 60 W incandescent equivalent LED bulb as well as the technologies available to accelerate cost cuts in order to understand the true pathways to LED bulbs’ potential. “LED lighting is by no means standardized, and potential disruptions to the component stack abound,” Madakasira said.
Thermal management is the biggest target for cost reduction past the package. Active thermal management technologies such Nuventix’s SynJet will lead to cost savings over aluminum-based solutions, but only from 2017 on.
Dimmable drivers are priced at a premium to non-dimmable ones because they enable precise control of the light output and lead to energy savings. Innovation in this area will bring about a 1% cost saving in 2020, boosting the performance of the LEDs overall.
Secondary optics account for about 5% of the total cost of a 60 W equivalent LED bulb. The field is dominated by specialists such as Ledil, Khatod, and Fraen, and innovation lies in improving the shape of the beam and the ability to collect more light from primary optics.
The report, Cheaper, Brighter, Cooler: The Need for Cost Reduction Past the Package, is part of the Lux Research Energy Electronics Intelligence service. Lux Research provides strategic advice and intelligence for emerging technologies. Visit www.luxresearchinc.com for more information.
SEMICON West took place July 10-12 in the Moscone Center, San Francisco, CA.
July 16, 2012 — The buzz at SEMICON West 2012 was all about the exciting future of 450mm wafer inspection systems. In the midst of the talk about these technological successes, a quieter, yet persistent, trend in Moscone Center
In a session at Semicon West 2012, Intel’s Alan Allan, International Roadmap Committee (IRC) discussed the evolution of the International Technology Roadmap for Semiconductors (ITRS) front-end process section. “The overriding message for 2012 is that the roadmap has been largely stabilized with the significant changes that were input last year in the 2012 publication,” said Allan, who is part of the committee that puts together the Overall Roadmap Technology Characteristics (ORTC) chapter and the Executive Summary. Large changes are 2013, however, are expected. “In the case of logic, a fairly a significant update and presentation of models has resulted in a structure that drives grand challenges and solutions. That was stabilized in the 2008/2009 timeframe and has served us well for the last couple of cycles. That will be evaluated this year for possibilities of adjustment in 2013,” he said.
More from the ITRS updates:
2012 ITRS update: Back-end packaging and MEMS
Roadmapping More than Moore: When the application matters
He noted that, for the most part, the targets for dimensional scaling and the power/performance management of leading devices, are set primarily by gate length in conjunction with equivalent scaling – things like strain, high-k metal gate and now the new multi-gate FET – which work in combination to manage power and performance.
iSimilarly, In the case of dynamic RAM, aggressive changes were made last year to take into account rapid acceleration of technology in DRAM and flash. “We do a survey every year amongst the members to check on the status as well as the long range driver outlook,” Alan said. “This year, the big change in looking out in time has to do with the 3D layers (i.e., 3D NAND). “We’re stacking up chips inside devices, so there’s 3D mechanical stacking that’s occurring in chips today. What we’re looking for in 2016 is actually the layer stacking of manufactured flash layers that will be as many 8-16 layers of those bits that will begin to be stacked in a process at the chip level. In the future, that’s projected to go up to 128 and 256 layers. You can imagine the ability to have a very high equivalent density in storage on a flash device in that timeframe,” he said. Further work on that is in the roadmap now and options are presented, but that will also be examined going forward for possible changes in 2013. “You can imagine the number of masks increase dramatically and the costs associated with that increase dramatically,” Allan said.
The 450mm transition is also being examined, not only in the domestic USA side with the work in Albany, but the work underway in Europe at imec, to do their similar pathway of 450mm. Allan also emphasized the importance of More-than-Moore, showing a “shopping list” of the things that will be worked on this year that will be delivered at the December Hsinchu Taiwan public conference that kicks off the work for the 2013 roadmap.
Overall, expected changes will be based on work in the logic area, but the surveying and updating of memory and the progress of lithography, which Allan described as significant and progressing. He also noted new work to address max on-chip frequency, which has to be addressed with intrinsic transistor modeling. “Work with Purdue University this year to go from static modeling into the realm of dynamic TCAD modeling that will also be represented publicly,” he said.
One notable change in the roadmap relates to how it is determined that a given technology is in volume production. “The whole point (of the ITRS) is to guide the research and development that prepares suppliers to deliver the early tools, early materials, that can get us into the early production level,” Allan said. “Sometimes a company will be ahead of others in a particular advancement, and they’ll be following a different pathway. That has caused us to rethink the requirement for two companies to be out within a couple of months or six months of each other (to defined HVM). A leading company can be in production with significant volume, and we use that now as the timing, even if the fast followers come along a year or two later, because the supply chain can still count on significant manufacturing opportunity sales for those technologies,” Allan said.
July 12, 2012 — There’s no doubt that fabless semiconductor companies are taking a keen interest in the semiconductor manufacturing supply chain and processes. To that end, SEMICON West’s Day 2 keynote speaker represented a fabless company: Ivo Bolsens, PhD, SVP and CTO of Xilinx presented on how programmable chips and innovative packaging can advance semiconductors.
Check out insights on the Day 1 keynote from Intel here.
There’s nothing new about the goals of semiconductor designers and manufacturers, Bolsens said, sharing some decade-old slides to make his point. Power density, Moore’s Law, and lowering costs have always been important, and innovation in technology and business models has always generated solutions.
The fabless semiconductor company’s goal is to add value to the system-level design. To do this, Xilinx has taken the approach of device flexibility, paired with 3D interconnection for higher performance/lower power/higher reliability. Bolsens notes that the company is collaborating much earlier with the supply chain and in a much broader fashion than ever before to achieve these goals.
Programmable chips offer flexibility, even while they may appear to have a higher cost than dedicated products. The ability to customize a chip for your functions, and use the same chip across various system-level configurations, leads to costs savings, Bolsens said, referring to time savings as a direct benefit. Logic can also be tuned to accelerate some functions, boosting performance. To save energy, FPGAs offer “fine-grain” programmability.
On the 3D and 2.5D packaging front, Bolsens shared the benefits of using multiple smaller die integrated in one package. Interconnect innovations increase the bandwidth/Watt consumed, and chip yields go up compared to fabricating one large die. When small FPGA die replace a large monolithic die, designers can use “best of breed” die for different functions. Isolation of different blocks also improves.
3D integration and other technology answers for the semiconductor industry’s challenges are in place, summarized Bolsens. Now, the supply chain must build up around them, with supporting information like process development kits (PDKs), design for manufacturing (DFM) rules, and other standardization efforts.
Bolsens recommends creating a continuous supply chain feedback loop while in the early ramp-up of a product, harkening back to his earlier points about collaborating early and often with the ecosystem that will enable your chip to reach market.
Check out Ivo Bolsens’ biography here, courtesy of SEMI.
Check out Solid State Technology’s coverage of SEMICON West 2012!
July 12, 2012 — Day 2 of Semicon West 2012 began a bit earlier than usual with the Sokudo Lithography Breakfast Forum, which focused on directed self-assembly (DSA). The first question was anticipated by Atsushi Yasue, emcee and CTO of Sokudo, who opened his remarks with “Is DSA just an interesting science project?” Given that Sokudo is introducing its Duo dual track product for DSA, I suspect he believes it is more than that.
Michael Garner, chairman of the ITRS emerging nanotechnology group, opened the technical sessions with the ITRS view of DSA. DSA was first identified as a potential lithography extension in 2007; in 2011, SPIE conferences included several presentations on evidence of DSA defect reduction. Progress has been made, though defects are still unacceptable at the 100ppm level. A brainstorming session at SPIE 2012 recommended specific topics for university and consortium pre-competitive research activity.
Yoshi Hishiro of JSR Micro has been working on DSA polymer blends and applications for several years already, both block copolymers and polymer blend systems. One specific application is contact hold shrink, which includes one method that can be used in combination with EUV. Contact hole repair, making features uniform and round, is another activity with strong customer pull. A patterning doubling method allows extension of a rectilinear grid of contact holes to a staggered grid with twice the density. Clearly, design objectives are constrained to a menu of what DSA is capable of delivering.
Serge Tedesco of CEA Leti described the IDeAL program at Leti, opening his presentation that included the characterization of DSA for microelectronics using block copolymers as an “easy process” with “low cost.” The number of SPIE DSA papers grew from 5 to 25 to 55 in 2010-2011-2012. The Leti 300mm pilot line has demonstrated 100nm contact hole shrink to 15nm, but CD and defect metrology is a challenge. He believes DSA could be inserted as a complementary lithography technique as early as the 14nm node.
Steve Renwick of the Imaging Solutions Technology Development group at Nikon gave a hardware perspective on DSA with 193nm immersion lithography. From his world view, these DSA materials actually want to do what we want them to do, irrespective of the hardware optics. Rather than a competitor, DSA is a high potential complement to 193i litho. Demonstrations have been executed showing that DSA is capable of healing print defects in the pattern, because DSA wants to form the target structures. Because of the commercial implementation of double patterning, litho tools are already capable of meeting the overlay requirements of 2-3 nm required for some DSA applications. Given the successes already demonstrated, he believes DSA will indeed fly as a complement to 193i.
Charles Pieczulewski of Sokudo spoke on the path to defect free manufacturing with DSA. Pilot development activity began five years ago on the existing RF3 track, and has evolved to the new Duo track that is designed specifically for DSA. Development studies included work to determine the pre-pattern CD range that was required to reduce the DSA defect density, those defects ranging from single dislocations to gross pattern randomization. One study on defect characterization for a contact hole shrink application encompassed 550,000,000 vias; this is why we have graduate students. They found 22 missing vias, 8 due to particle contamination and only 14 due to poor DSA phase separation. The student’s leopard hallucinations are subsiding. Additional DSA tracks will move into pilot production now through 2013, with HVM tools to start shipping in 2014.
Linda He Yi of Stanford U (student of H.-S. Phillip Wong) opened her remarks with the observation that long-range order is not required for chip manufacturing. Rather, the objective can be altered to place specific patterns in specific locations of limited area. One can create a template for each individual feature to be created with DSA; or in this approach, multiple DSA features can be fabricated with a library of templates that can be used repeatedly to generate, in effect, ‘random’ design features. The benefit of such a library is a relaxation of resolution requirements for the template patterning. Once again, DSA is found to heal defects in the litho patterns. By the way, Linda is the lucky grad student who got to inspect the 550,000,000 vias cited above.
The NCCAVS CMPUG staged its 5th annual meeting concurrent with Semicon West, this year returning to a separate room rather than being held on the show floor where the seats are too few and the decibels are too many. As always, the CMPUG presentations will be posted on the NCCAVS CMPUG website in the coming week or so.
The first speaker was yours truly, Michael Fury of the Techcet Group, providing the annual CMP consumables market update. Pad & Slurry revenues are up 3% over 2010, with a 2012 forecast up 5.7% to $1.73B. Combined with pad conditioners, PCMP cleaners, PVA brushes and slurry filters, the CMP consumables business achieved a $2.04B milestone in 2011.
Iqbal Ali of SEMATECH @ Albany updated us on the status of CMP’s role in 3D TSV activities there. The TSV story remains primarily a copper CMP market from this group’s perspective, but the demands for removal rate of thick copper, planarity of large features (compared to on-chip interconnects), and selectivity to different materials demands unique CMP products and processes if TSV is to be successful in HVM. SEMATECH has been working with Cabot Micro and Air Products to develop a working backside reveal process for copper CMP and alkaline post-clean (CP98-D) that keeps cross-contamination of the exposed silicon under control, as quantified by the Qcept ChemetriQ tool.
Paul Feeney of Axus Technology took us back to the future with a discussion of polishing non-uniformity, beginning with the use of multi-wafer templates by the Cro-Magnon. Polishing heads are currently being designed with 8 zone control and ≤2mm edge exclusion. Migration to 450mm will exacerbate the center-to-edge depletion of slurry reactants and the temperature differential between the wafer leading and trailing edge, which drives reaction kinetics. The 54nm Cu line widths scheduled for production in 2013 will struggle with Cu losses due to the combined effects of non-uniformity, imperfect selectivity, and edge roll-off. Polishing head upgrades for 200mm and even 150mm wafer polishers are still in demand by smaller fabs and research labs for achieving state-of-the-art performance on retro platforms. You know, the kind found in cave drawings.
Mike Corbett of Linx Consulting talked about the impact of the now-inevitable 450mm conversion on CMP consumables. CMOS wafer starts drive the CMP market, and this segment is lagging the overall chip market. The Linx slurry & pad market estimate is $1.615B for 2011. The supplier consolidation index used by the US Department of Justice indicates that confirms the expectation that tungsten slurry is highly consolidated, though not to the extent of monopoly, while the other slurry segments are well diversified with a balance between suppliers from the US and Japan. Fab projections foretell a peak in 300mm wafer production in 2021, with 450mm starting to scale to high volume production in 2018. By 2025, the MSI (millions of square inches) of silicon processed in 450mm will cross over and exceed the 300mm production. Slurry & pad costs are projected to increase 35-50% per wafer, depending on the actual increase in slurry flow rate (used 1.2x to 1.5x) needed to achieve process specs.
Michael Fury, speaking this time as Vantage Technology, presented several tales from the sub-fab, describing the kinds of anomalies that have been observed in customer slurry distribution lines around the world using the continuous monitoring capability of the SlurryScope. Monitoring large particle counts for post-mortem diagnosis of wafer scratching incidents is useful for understanding and for future-looking corrective actions, but that is only part of the story. Monitoring particle behavior continuously teaches the patterns of drifts and spikes in the slurry supply, making it possible to learn the special causes associated with each type of behavior observed, eliminate those causes, and actually prevent slurry-induced scratching incidents with stable line performance.
Bruce Kellerman of MEMC talked about the 450mm transition from the wafer manufacturers’ point of view. The arguments supporting the 450mm transition parallel those for the 300mm transition, though the number of players that are both able and willing to afford it is dwindling. Siltronic, Sumco and MEMC have all announced workforce and facility reductions in the past 8 months. From over 20 wafer producers at 150mm, we are down to 6 suppliers at 300mm; Bruce used “?” for the count at 450mm, but all presently have active 450mm programs in place. That doesn’t mean all will remain viable, especially given the small number of fab customers. Intel, Samsung and TSMC are pretty much guaranteed customers, but even they have divergent specs. To get costs in line, a greater degree of standardization across fab customers is required.
While I do appreciate the relative quiet and sanity of holding this CMPUG meeting in a separate room away from the show floor, I realize now that the penalty we paid is that we had no access to the Happy Hour that started on the show floor two hours before we concluded our business. When people talk about CMP placing unreasonable demands on people, this is what they’re talking about.
Michael A. Fury is director and senior technology analyst, Techcet Group and a regular contributor to Solid State Technology. Read his reports from the Gartner/SEMI forecast meetings, and from CEA-Leti’s research presentations.
July 11, 2012 — At the opening keynote of SEMICON West, Shekhar Borkar, Intel Fellow and director of extreme electronics for the company, presented on ubiquitous computing and the link from ultra high performance computing to handheld devices. He shared developments on power and energy reductions, coupled with increasing semiconductor performance.
In this video interview, Borkar shares some key topics from his presentation: Near-threshold voltage transistor designs, 3D integration for DRAM, unconventional interconnect, and more. Borkar speaks with digital media editor Meredith Courtemanche.
Get deeper into Borkar’s presentation topic in Courtemanche’s blog from the event, The energy behind energy at SEMICON West
July 11, 2012 — Day 1 of Semicon West 2012 opened under brighter skies than we had yesterday, when speakers at the SEMI/Gartner market symposium from Portland, of all places, made fun of the gloomy skies over my beloved San Francisco. I don’t think our skies will ever compare to Portland — and I mean that in a good way (for San Francisco…). The Semicon show floor is more spacious than it was a decade ago, with wider aisles, more presentation stages, and fewer pieces of large equipment. And for the first time in several years, Novellus is not doing its own thing in the Yerba Buena Center for the Arts, which still sports its permanent (so far…) Novellus Theater sign.
CEA Leti sponsored an early evening symposium at the W Hotel for almost 200 attendees. Among the fastest computers in the world is an installation in Berkeley that runs up to 16 PFLOPS/sec, requiring 8MW of power. Linear projections for a 1 EFLOP/sec system in the planning phase would require an unmanageable 600MW. Power management is becoming an industry in its own right. Several global data centers have been announced in Scandinavia to allow the climate to contribute to the cooling effort. I anticipate a shift for Santa from toys to virtual games in cloud computing.
Maud Vinet, one of Leti’s resident researchers at U Albany, gave the current status of their work in fully depleted SOI (FDSOI) device architecture, in which they have been engaged for 15 years since the spin out of SOITEC. This is being extended below 20nm, still in a planar device configuration.
A pair of talks reviewed Leti’s involvement in TSV and related 2.5D and 3D integration. One slide was shown with Leti’s first TSV demonstration in 1988, suggesting once again that nothing is new if you know who has the original photographs. While via-middle processing is the current norm, Leti believes that via-last with permanent bonding can be used to bring via diameter down to 3µm, though it may be limited to IDMs and memory applications due to its interdependence with design.
Integration of photonics on chip is another focus area for Leti, motivated by the fact that as much as 80% of the bottlenecks that the zettabytes (zetta = 1021) of data encounter every year occur within the data centers themselves. Since we’re expected to be into the yottabyte (1024) range by 2020, replacing electrons and copper with photons is an idea whose time is too close for comfort. We’re also going to need more prefixes for 1027 and beyond. The world runs on a lot of data, though I maintain that Fox News remains a notable exception.
The presentations were followed by hors d’oeuvres and a champagne bar stocked with — and this is the ironic part — California champagne. I sense a lost branding opportunity for our colleagues from Grenoble.
Best Semicon show give away ever: my sole nominee in this category is the Schott Glass shot glass, a very stylish piece of barware with a generous 2 ounce pour. Kudos!!
Michael A. Fury is a contributing blogger for Solid State Technology and director and senior technology analyst, Techcet Group.
Read his report from SEMI’s press conference and the SEMI/Gartner Market Symposium.
Read more about CEA-Leti’s talks in digital media editor Meredith Courtemanche’s The energy behind energy at SEMICON West