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By Emmy Yi, SEMI Taiwan 

Driven by emerging technologies like Artificial Intelligence (AI), Internet of Things (IoT), machine learning and big data, the digital transformation has become an irreversible trend for the electronics manufacturing industry. The global market for smart manufacturing and smart factory technologies is expected to reach US$250 billion in 2018.

“The semiconductor manufacturing process has reached its downscaling limit, making outstanding manufacturing capabilities indispensable for corporations to stay competitive,” said Ana Li, Director of Outreach and Member Service at SEMI. “Advances in cloud computing, data processing, and system integration technologies will be key to driving the broad adoption of smart manufacturing.”

ompany representatives shared insights and successes in manufacturing digitalization.

ompany representatives shared insights and successes in manufacturing digitalization.

To help semiconductor manufacturing companies navigate the digital transformation, SEMI recently held the AI and Smart Manufacturing Forum, a gathering of industry professionals from Microsoft, Stark Technology, Advantech, ISCOM, and Tectura to examine technology trends and smart manufacturing opportunities and challenges. The nearly 100 guests at the forum also included industry veterans from TSMC, ASE, Siliconware, Micron, and AUO. Following are key takeaways from the forum:

1)    Smart manufacturing is the key for digital transformation
Industry 4.0 is all about using automation to better understand customer needs and help drive efficiency improvements that enable better strategic manufacturing decisions. For electronics manufacturers, thriving in the digital transformation should begin with research and development focused on optimizing processes, developing innovative business models, and analyzing data in ways that support their customers’ business values and objectives. Digitization is also crucial for manufacturers to target the right client base, increase productivity, optimize operations and create new revenue opportunities.

2)    Powerful data analysis capabilities will enable manufacturing digitalization

As product development focuses more on smaller production volumes, companies need a powerful data analysis software to accelerate decision-making and problem-solving processes, enhance integration across different types of equipment, and improve management efficiency across enterprise resources including business operations, marketing, and customer service.

3)    The digital transformation will fuel revenue growth
Connectivity and data analysis, the two essential concepts of smart manufacturing, are not only essential for companies to improve facility management efficiency and production line planning but also key for maintaining healthy revenue growth.

“With our more than 130 semiconductor manufacturers and long fab history, Taiwan is in a strong position to help the industry evolve manufacturing to support the explosion of new data-intensive technologies,” said Chen-Wei Chiang, the Senior Specialist at the Taichung City Government’s Economic Development Bureau. “We look forward to working with SEMI to help manufacturers realize the full potential of smart manufacturing.”

With the advent of new data-intensive technologies including AI and IoT, advanced manufacturing processes that improve product yield rates and reduce production costs will become even more important for manufacturers to remain competitive. SEMI Taiwan will continue to assemble representatives from the industry, government, academia and research to examine critical topics in smart manufacturing. To learn more, please contact Emmy Yi, SEMI Taiwan, at
[email protected] or +886.3.560.1777 #205.

 

Year End Wow!


January 24, 2018

By Walt Custer, Custer Consulting Group

Strong year-end 2017 electronic equipment sales

2017 ended on a high note from an end market perspective thanks to:

  • Geographically broad economic strength and new products
  • Record high December electronic equipment production and shipments in China/Taiwan
  • Peak electronic equipment production in the Eurozone in November
  • A 4Q upturn in U.S. bookings and shipments of electronic equipment

Custer1-World-Electronic-Equipment-Monthly-Shipments

Based upon preliminary data, mobile phones including the Apple iPhone X were major contributors to the fourth-quarter 2017 strength in Asia/Pacific. Foxconn registered all-time record sales in December.

By comparison, personal computer sales were flat when adjusted for normal seasonality.

Early information indicates that December global equipment revenues were up almost 24 percent over December 2016 and up 3 percent sequentially over November 2017.

Resilient semiconductor supply chain

Semiconductors and SEMI equipment have a strong growth in this current business cycle (Chart 2), mainly due to strong memory demand and price increases for chips, and also robust capital equipment spending to increase memory chip capacity.

Custer2-World-Semiconductor-SEMI-Equipement-Shipments

 

By November this sales growth appeared to be plateauing (but at record levels).

On a 3/12 basis (Chart 3) world growth was:

Semiconductors +21.5% November
SEMI equipment +28.4% November
Taiwan Chip Foundries +6.1% December
Electronic Equipment +4.9% September

Custer3-Supply-Chain-Dynamics
Despite a likely moderation of the current SEMI equipment and chip growth rates, this current business cycle has been robust and prolonged. End market electronic equipment demand remains strong and new volume markets are emerging. However SEMI equipment and semiconductor sales are much more volatile than electronic equipment, so the current landscape could change quickly.

Looking forward

The global PMI is an excellent short-term leading indicator. It was at an all-time record high in December, pointing to an unseasonably strong first quarter of 2018. Keep watching the business cycles for any signs of abrupt change. Currently we are on a high plateau but conditions could change quickly.

Custer4-Purchasing-Managers-Index

Originally published on the SEMI blog.

The historic flood of merger and acquisition agreements that swept through the semiconductor industry in 2015 and 2016 slowed significantly in 2017, but the total value of M&A deals reached in the year was still more than twice the annual average in the first half of this decade, according to IC Insights’ new 2018 McClean Report, which becomes available this month.  Subscribers to The McClean Report can attend one of the upcoming half-day seminars (January 23 in Scottsdale, AZ; January 25 in Sunnyvale, CA; and January 30 in Boston, MA) that discuss the highlights of the report free of charge.

In 2017, about two dozen acquisition agreements were reached for semiconductor companies, business units, product lines, and related assets with a combined value of $27.7 billion compared to the record-high $107.3 billion set in 2015 and the $99.8 billion total in 2016 (Figure 1).  Prior to the explosion of semiconductor acquisitions that erupted several years ago, M&A agreements in the chip industry had a total annual average value of about $12.6 billion between 2010 and 2015.

Figure 1

Figure 1

Two large acquisition agreements accounted for 87% of the M&A total in 2017, and without them, the year would have been subpar in terms of the typical annual value of announced transactions.  The falloff in the value of semiconductor acquisition agreements in 2017 suggests that the feverish pace of M&A deals is finally cooling off.  M&A mania erupted in 2015 when semiconductor acquisitions accelerated because a growing number of companies began buying other chip businesses to offset slow growth rates in major end-use applications (such as smartphones, PCs, and tablets) and to expand their reach into huge new market opportunities, like the Internet of Things (IoT), wearable systems, and highly “intelligent” embedded electronics, including the growing amount of automated driver-assist capabilities in new cars and fully autonomous vehicles in the not-so-distant future.

With the number of acquisition targets shrinking and the task of merging operations together growing, industry consolidation through M&A transactions decelerated in 2017.  Regulatory reviews of planned mergers by government agencies in Europe, the U.S., and China have also slowed the pace of large semiconductor acquisitions.

One of the big differences between semiconductor M&A in 2017 and the two prior years was that far fewer megadeals were announced.  In 2017, only two acquisition agreements exceeded $1 billion in value (the $18 billion deal for Toshiba’s memory business and Marvell’s planned $6 billion purchase of Cavium).  Ten semiconductor acquisition agreements in 2015 exceeded $1 billion and seven in 2016 were valued over $1 billion.  The two large acquisition agreements in 2017 pushed the average value of semiconductor M&A pacts to $1.3 billion.  Without those megadeals, the average would have been just $185 million last year. The average value of 22 semiconductor acquisition agreements struck in 2015 was $4.9 billion.  In 2016, the average for 29 M&A agreements was $3.4 billion, based on data compiled by IC Insights.

A nanostructured gate dielectric may have addressed the most significant obstacle to expanding the use of organic semiconductors for thin-film transistors. The structure, composed of a fluoropolymer layer followed by a nanolaminate made from two metal oxide materials, serves as gate dielectric and simultaneously protects the organic semiconductor – which had previously been vulnerable to damage from the ambient environment – and enables the transistors to operate with unprecedented stability.

Image shows organic-thin film transistors with a nanostructured gate dielectric under continuous testing on a probe station. (Credit: Rob Felt, Georgia Tech)

Image shows organic-thin film transistors with a nanostructured gate dielectric under continuous testing on a probe station. (Credit: Rob Felt, Georgia Tech)

The new structure gives thin-film transistors stability comparable to those made with inorganic materials, allowing them to operate in ambient conditions – even underwater. Organic thin-film transistors can be made inexpensively at low temperature on a variety of flexible substrates using techniques such as inkjet printing, potentially opening new applications that take advantage of simple, additive fabrication processes.

“We have now proven a geometry that yields lifetime performance that for the first time establish that organic circuits can be as stable as devices produced with conventional inorganic technologies,” said Bernard Kippelen, the Joseph M. Pettit professor in Georgia Tech’s School of Electrical and Computer Engineering (ECE) and director of Georgia Tech’s Center for Organic Photonics and Electronics (COPE). “This could be the tipping point for organic thin-film transistors, addressing long-standing concerns about the stability of organic-based printable devices.”

The research was reported January 12 in the journal Science Advances. The research is the culmination of 15 years of development within COPE and was supported by sponsors including the Office of Naval Research, the Air Force Office of Scientific Research, and the National Nuclear Security Administration.

Transistors comprise three electrodes. The source and drain electrodes pass current to create the “on” state, but only when a voltage is applied to the gate electrode, which is separated from the organic semiconductor material by a thin dielectric layer. A unique aspect of the architecture developed at Georgia Tech is that this dielectric layer uses two components, a fluoropolymer and a metal-oxide layer.

“When we first developed this architecture, this metal oxide layer was aluminum oxide, which is susceptible to damage from humidity,” said Canek Fuentes-Hernandez, a senior research scientist and coauthor of the paper. “Working in collaboration with Georgia Tech Professor Samuel Graham, we developed complex nanolaminate barriers which could be produced at temperatures below 110 degrees Celsius and that when used as gate dielectric, enabled transistors to sustain being immersed in water near its boiling point.”

The new Georgia Tech architecture uses alternating layers of aluminum oxide and hafnium oxide – five layers of one, then five layers of the other, repeated 30 times atop the fluoropolymer – to make the dielectric. The oxide layers are produced with atomic layer deposition (ALD). The nanolaminate, which ends up being about 50 nanometers thick, is virtually immune to the effects of humidity.

“While we knew this architecture yielded good barrier properties, we were blown away by how stably transistors operated with the new architecture,” said Fuentes-Hernandez. “The performance of these transistors remained virtually unchanged even when we operated them for hundreds of hours and at elevated temperatures of 75 degrees Celsius. This was by far the most stable organic-based transistor we had ever fabricated.”

For the laboratory demonstration, the researchers used a glass substrate, but many other flexible materials – including polymers and even paper – could also be used.

In the lab, the researchers used standard ALD growth techniques to produce the nanolaminate. But newer processes referred to as spatial ALD – utilizing multiple heads with nozzles delivering the precursors – could accelerate production and allow the devices to be scaled up in size. “ALD has now reached a level of maturity at which it has become a scalable industrial process, and we think this will allow a new phase in the development of organic thin-film transistors,” Kippelen said.

An obvious application is for the transistors that control pixels in organic light-emitting displays (OLEDs) used in such devices as the iPhone X and Samsung phones. These pixels are now controlled by transistors fabricated with conventional inorganic semiconductors, but with the additional stability provided by the new nanolaminate, they could perhaps be made with printable organic thin-film transistors instead.

Internet of things (IoT) devices could also benefit from fabrication enabled by the new technology, allowing production with inkjet printers and other low-cost printing and coating processes. The nanolaminate technique could also allow development of inexpensive paper-based devices, such as smart tickets, that would use antennas, displays and memory fabricated on paper through low-cost processes.

But the most dramatic applications could be in very large flexible displays that could be rolled up when not in use.

“We will get better image quality, larger size and better resolution,” Kippelen said. “As these screens become larger, the rigid form factor of conventional displays will be a limitation. Low processing temperature carbon-based technology will allow the screen to be rolled up, making it easy to carry around and less susceptible to damage.

For their demonstration, Kippelen’s team – which also includes Xiaojia Jia, Cheng-Yin Wang and Youngrak Park – used a model organic semiconductor. The material has well-known properties, but with carrier mobility values of 1.6 cm2/Vs isn’t the fastest available. As a next step, they researchers would like to test their process on newer organic semiconductors that provide higher charge mobility. They also plan to continue testing the nanolaminate under different bending conditions, across longer time periods, and in other device platforms such as photodetectors.

Though the carbon-based electronics are expanding their device capabilities, traditional materials like silicon have nothing to fear.

“When it comes to high speeds, crystalline materials like silicon or gallium nitride will certainly have a bright and very long future,” said Kippelen. “But for many future printed applications, a combination of the latest organic semiconductor with higher charge mobility and the nanostructured gate dielectric will provide a very powerful device technology.”

By David W. Price, Douglas G. Sutherland and Jay Rathert

Author’s Note: The Process Watch series explores key concepts about process control—defect inspection, metrology and data analysis—for the semiconductor industry. This article is the first in a five-part series on semiconductors in the automotive industry. In this article, we introduce some of the challenges involved in the automotive supply chain. Future articles in the series will address specific process control solutions to those challenges.

In the 1950s less than 1% of the total cost of manufacturing a car was comprised of electronics. Today that cost can be more than 35% of the total and it is expected to increase to 50% by the year 2030.1 The rapid increase in the use of electronics in the automotive industry has been driven by four main areas:

  1. Systems monitoring and control (electronic fuel injection, gas-electric hybrids, etc.)
  2. Safety (anti-lock brakes, air bags, etc.)
  3. Advanced Driver Assistance Systems (lane departure warning, parking assist, blind spot monitoring, adaptive cruise control, etc.)
  4. Convenience (satellite navigation, infotainment, etc.)

Semiconductor components are at the core of the electronics integrated in cars, and depending on the make and model, a modern car may require as many as 8000 chips.2 This number will only increase as autonomous driving gains popularity – additional electronic subsystems with their underlying ICs will power the sensors, radar and AI needed for driverless cars.

With over 88 million cars and light trucks produced every year,3 each with thousands of chips, the influence of the automotive industry on semiconductor manufacturing is starting to take hold. There is one simple fact about these thousands of chips found in a car: they cannot fail. Reliability is absolutely critical for automotive semiconductor components. Any chip that fails in the field can result in costly warranty repairs and recalls, can damage the image of the automaker’s brand – or at the extreme, can result in personal injury or even loss of life.

If the average car contains 5000 chips and the automaker produces 25,000 cars per day, then even a chip failure rate at the parts per million (ppm) level will result in more than 125 cars per day that experience reliability issues as a result of chip quality. With semiconductors as the top issue on automakers’ failure Pareto,4 Tier 1 automotive system suppliers are now demanding parts per billion (ppb) levels of semiconductor quality with an increasing trend toward a maximum number of “total allowable failure events” regardless of volume. Current methods for finding reliability failures are overly dependent on test and burn-in, and as a result, the quality targets are missed by orders of magnitude. Increasingly, challenging audit standards are pushing for reliability failures to be found at their source in the fab, where costs of discovery and corrective action are the lowest. To enter this growing market segment – or simply maintain share – IC manufacturers must aggressively address this inflection in chip reliability requirements.

Fortunately for semiconductor manufacturers, chip reliability is highly correlated to something they know very well: random defectivity.5 In fact, for a well-designed process and product, early-life chip reliability issues (extrinsic reliability) are dominated by random defectivity.6-12 A killer defect (one that impacts yield) is a defect that causes the device to fail at time t = 0 (final test). A latent defect (one that impacts chip reliability) is a defect that causes the device to fail at t > 0 (after burn-in). The relationship between killer defects (yield) and latent defects (reliability) stems from the observation that the same defect types that impact yield also impact reliability. The two are distinguished primarily by their size and where they occur on the device structure. Figure 1 shows examples of killer and latent defects that result in open and short circuits.

Figure 1

Figure 1. The same defect types that impact yield also affect reliability. They are distinguished primarily by their size and where they occur on the device’s pattern structure.

The relationship between yield and reliability defects is not limited to a few specific defect types; any defect type that can cause yield loss is also a reliability concern. Failure analysis indicates that the majority of reliability defects are, in fact, process-related defects that originate in the fab. Because yield and reliability defects share the same root cause, increasing yield (by reducing yield-related defects) will have the additional benefit of improving reliability.

The yellow line in figure 2 shows a typical yield curve. If we only consider chip yield, then at some point, further investment in this process may not be cost-effective and thus the yield tends to level off as time progresses. The blue dashed line in figure 2 shows the curve for the same fab making the same product. However, if they want to supply the automotive industry then they must also account for the costs of poor reliability. In this case further investment is warranted to drive down defect density even further, which will both increase yield and deliver the improved reliability required for automotive suppliers.

Figure 2. Yield curves (Yield versus Time) for different fab types. The yellow line is for non-automotive fabs where the major consideration is fab profitability. At some point the yield is high enough that it is no longer practical to continue trying to drive down defectivity. The blue dashed line is the yield curve that also factors in reliability. For IC products used in the automotive supply chain additional investment must be made to ensure high reliability, which is strongly correlated to yield.

Figure 2. Yield curves (Yield versus Time) for different fab types. The yellow line is for non-automotive fabs where the major consideration is fab profitability. At some point the yield is high enough that it is no longer practical to continue trying to drive down defectivity. The blue dashed line is the yield curve that also factors in reliability. For IC products used in the automotive supply chain additional investment must be made to ensure high reliability, which is strongly correlated to yield.

The change from being a consumer-grade chip supplier to an automotive supplier requires a paradigm shift at the fab management level. Successful semiconductor manufacturers who supply the automotive industry have long adopted the following strategy: The best way to reduce the possibility of latent (reliability) defects is to reduce the fab’s overall random defectivity levels. This means having a world class defect reduction strategy:

  1. Higher baseline yields
  2. Lower incidence of excursions
  3. When excursions do occur, quickly find and fix them inline
  4. Ink out suspicious die using die-level screening

 

These and other strategies will be addressed in forthcoming articles in this Process Watch automotive series.

 

About the Authors:

 

Dr. David W. Price and Jay Rathert are Senior Directors at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 15 years, they have worked directly with over 50 semiconductor IC manufacturers to help them optimize their overall process control strategy for a variety of specific markets, including automotive reliability, legacy fab cost and risk optimization, and advanced design rule time-to-market BKMs. The Process Watch series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

 

References:

 

  1. https://www.statista.com/statistics/277931/automotive-electronics-cost-as-a-share-of-total-car-cost-worldwide/
  2. Senftleben and Froehlich, Aspects of Semiconductor Quality from an OEM Perspective, April 2017.
  3. http://www.businessinsider.com/2016-was-a-record-breaking-year-for-global-car-sales-and-it-was-almost-entirely-driven-by-china-2017-1
  4. https://www.consumerreports.org/car-reliability-owner-satisfaction/consumer-reports-car-reliability-survey-2017/
  5. Price and Sutherland, “Process Watch: The Most Expensive Defect, Part 2,” Solid State Technology, July 2015.
  6. Riordan et al., “Microprocessor Reliability Performance as a Function of Die Location for a .25um, Five Layer Metal CMOS Logic Process,” 37th Annual International Reliability Physics Symposium Proceedings (1999): 1-11. http://dx.doi.org/10.1109/RELPHY.1999.761584
  7. Barnett et al., “Extending Integrated-Circuit Yield Models to Estimate Early-Life Reliability,” IEEE Transactions on Reliability, Vol. 52, No. 3., 2003.
  8. Shirley, “A Defect Model of Reliability,” 33rd Annual International Reliability Symposium, Las Vegas, NV, 1995.
  9. Kim et al., “On the Relationship of Semiconductor Yield and Reliability,” IEEE Transactions on Semiconductor Manufacturing, Vol. 18, No. 3, 2005.
  10. Roesch, “Reliability Experience,” Published lecture #12 for Quality and Reliability Engineering ECE 510 at Portland State University, 2013. http://web.cecs.pdx.edu/~cgshirl/Quality%20and%20Reliability%20Engineering.htm
  11. Shirley and Johnson, “Defect Models of Yield and Reliability,” Published lecture #13 for Quality and Reliability Engineering ECE 510 course at Portland State University, 2013. http://web.cecs.pdx.edu/~cgshirl/Quality%20and%20Reliability%20Engineering.htm
  12. Kuper et al., “Relation between Yield and Reliability of Integrated Circuits: Experimental results and Application to Continuous Early Failure Rate Reduction Programs,” Proceedings of the International Reliability Physics Symposium (1996): 17-21.

The year-end update to the SEMI World Fab Forecast report reveals 2017 spending on fab equipment investments will reach an all-time high of $57 billion. High chip demand, strong pricing for memory, and fierce competition are driving the high-level of fab investments, with many companies investing at previously unseen levels for new fab construction and fab equipment. See figure 1.

Figure 1

Figure 1

The SEMI World Fab Forecast data shows fab equipment spending in 2017 totaling US$57 billion, an increase of 41 percent year-over-year (YoY). In 2018, spending is expected to increase 11 percent to US$63 billion.

While many companies, including Intel, Micron, Toshiba (and Western Digital), and GLOBALFOUNDRIES increased fab investments for 2017 and 2018, the strong increase reflects spending by just two companies and primarily one region.

SEMI data shows a surge of investments in Korea, due primarily to Samsung, which is expected to increase its fab equipment spending by 128 percent in 2017, from US$8 billion to US$18 billion. SK Hynix also increased fab equipment spending, by about 70 percent, to US$5.5 billion, the largest spending level in its history. While the majority of Samsung and SK Hynix spending remains in Korea, some will take place in China and the United States. Both Samsung and SK Hynix are expected to maintain high levels of investments in 2018. See figure 2.

Figure 2

Figure 2

In 2018, China is expected to begin equipping many fabs constructed in 2017. In the past, non-Chinese companies accounted for most fab investments in China. For the first time, in 2018 Chinese-owned device manufacturers will approach parity, spending nearly as much on fab equipment as their non-Chinese counterparts. In 2018, Chinese-owned companies are expected to invest about US$5.8 billion, while non-Chinese will invest US$6.7 billion. Many new companies such as Yangtze Memory Technology, Fujian Jin Hua, Hua Li, and Hefei Chang Xin Memory are investing heavily in the region.

Historic highs in equipment spending in 2017 and 2018 reflect growing demand for advanced devices. This spending follows unprecedented growth in construction spending for new fabs also detailed in the SEMI World Fab Forecast report. Construction spending will reach all-time highs with China construction spending taking the lead at US$6 billion in 2017 and US$6.6 billion in 2018, establishing another record: no region has ever spent more than US$6 billion in a single year for construction.

Throughout 2017, DRAM manufacturers faced pressure to boost output of their devices—particularly high-performance DRAM used in data center servers, and low-power high-density DRAM used in smartphones and other mobile products. Strong, ongoing demand put significant upward pressure on DRAM average selling prices.  This trend continued into 4Q17 and is expected to drive quarterly DRAM sales to an all time high mark of $21.1 billion (Figure 1), capping an incredible year of growth in which DRAM sales set a new all time high sales mark each quarter. The forecast $21.1 billion sales level in 4Q17 would be an increase of 65% compared to the $12.8 billion DRAM market of 4Q16.

Figure 1

Figure 1

Annual DRAM market growth of 74% is forecast for 2017, which would be the highest growth rate since the 78% increase in 1994—23 years ago—and 61 points more than the 13% average DRAM market growth rate from 1993-2017 (Figure 2).  The expected 74% DRAM market growth in 2017 will mark the fourth time since 1993 that the DRAM market has increased by more than 50%.  This near-historic high market spike in 2017 was brought on by several factors, including constrained supply attributed to a lack of major fab expansion plans, yield difficulties with leading-edge (≤20nm) processes, demand for high performance (graphics) DRAM from gaming systems and data center-based server applications, and increased average content for mobile DRAM used in smartphones.

Figure 2

Figure 2

There is an increasing need for high-speed but inexpensive data storage in smartphone handsets for multi-tasking, which is boosting the average DRAM content in a smartphone.  The Apple iPhone 8 features 2GB of DRAM and the iPhone X has 3GB of DRAM.  The Samsung Galaxy S8 is sold with 4GB of DRAM (6GB in China).  Huawei’s P10 Plus, and HTC’s U11 come with 6GB of DRAM.  The One Plus 5 model and the first smartphone from Razer, a Singapore-based company that is primarily known for its video game equipment, have 8GB of DRAM.

With virtual and augmented reality and artificial intelligence becoming prominent features on new smartphones and apps, DRAM content in high-end smartphones shows no signs of slowing.  Meanwhile, DRAM growth for smartphones is also stemming from less developed countries, where much of the population is moving from feature phones to their first smartphone—literally transitioning from zero to 1GB of mobile DRAM.

Based on historical trends, the DRAM industry will likely experience a decline (possibly a big market decline) in its growth rate in the not-too-distant future as prices begin to tumble with significant capacity additions and an increase in DRAM output expected over the next year or two.  Announcements by Samsung and SK Hynix in the second half of 2017 confirmed that new DRAM capacity is set to come online in 2018, which likely will ease the upward trend of DRAM ASPs next year.  Samsung has stated its semiconductor capital expenditure budget for 2017 will be an enormous $26.0 billion, and SK Hynix has announced plans to build a new manufacturing line at its massive facility in Wuxi, China.  Micron has gone on record as saying it doubts that it will ever need to build another new DRAM fab, but it is hard to imagine that Micron will sit still as its two fiercest rivals capture additional marketshare.  (For the record, Micron and Intel are developing Crosspoint memory as a potential replacement for DRAM).

Leti, a research institute of CEA Tech, has integrated hybrid III-V silicon lasers on 200mm wafers using standard CMOS process flow. This breakthrough shows the way to transitioning away from 100mm wafers and a process based on bulk III-V technology that requires contacts with noble metals and lift-off based patterning.

The project, carried out in the framework of the IRT Nanoelec program, which is headed by Leti, demonstrated that the hybrid device’s performance is comparable to the reference device fabricated with the current process on 100mm wafers. The fabrication flow is fully planar and compatible with large-scale integration on silicon-photonic circuits.

The results were reported Dec. 5 at IEDM 2017 in a paper titled “Hybrid III-V/Si DFB Laser Integration on a 200mm Fully CMOS-compatible Silicon Photonics Platform”.

CMOS compatibility with silicon photonics lowers fabrication costs, and provides access to mature and large-scale facilities, which enables packaging compatibility with CMOS driving circuits.

“Silicon-photonic technologies are becoming more mature, but the main limitation of these platforms is the lack of an integrated light source,” said Bertrand Szelag, a co-author of the paper. “This project showed that a laser can be integrated on a mature silicon-photonic platform with a modular approach that does not compromise baseline process performances. We demonstrated that the entire process can be done in a standard CMOS fabrication line with conventional process and materials, and that it is possible to integrate all the photonic building blocks at large scale.”

The integration required managing a thick silicon film, typically 500nm thick, for the hybrid laser, and a thinner one, typically 300nm, for the baseline silicon-photonic platform. This required locally thickening the silicon by adding 200nm of amorphous silicon via a damascene process, which presents the advantage of leaving a flat surface favorable for bonding III-V silicon. The laser can be integrated on a mature silicon photonic platform with a modular approach that does not compromise the baseline process performance.

The novelty of the approach also included using innovative laser electrical contacts that do not contain any noble metals, such as gold. The contacts also prohibit integration lift-off-based processes. Nickel-based metallization was used with an integration technique similar to a CMOS transistor technique, in which tungsten plugs connect the device to the routing metal lines.

Next steps include integrating the laser with active silicon-photonic devices, e.g. a modulator and photodiode with several interconnect metal levels in a planarized backend. Finally, III-V die bonding will replace III-V wafer bonding in order to process lasers on the entire silicon wafer.

Tilted scanning electron microscopy view of the III-V/Si DFB laser after the IIIV patterning steps.

Tilted scanning electron microscopy view of the III-V/Si DFB laser after the IIIV patterning steps.

Laser spectrum at 160 mA injection currents

Laser spectrum at 160 mA injection currents

A new illumination technology compares favorably to conventional bright field illumination.

BY GURVINDER SINGH, Director, Product Management, Rudolph Technologies, Inc., Wilmington, MA

A new optical technique can reveal defects and contaminants that escape conventional inspection technologies in many advanced packaging applications. As wafer level packaging (WLP), and especially fan-out wafer and panel level packaging (FOWLP/FOPLP), gains broader accep- tance, certain classes of defects that are characteristic of these processes present significant challenges to standard optical inspection tools. A new optical technology demonstrates increased sensitivity to transparent defects, such as residual dielectric films and photoresist, which are only marginally visible with conventional tools. At the same time, it is less sensitive to nuisance defects, such as those caused by the varying contrast and texture of grains in metal films, that should correctly be ignored.

Challenges in advanced packaging applications

Advanced packaging processes often involve the use of front-end-like technologies in back-end applications. Fan-out packaging is no exception, and, not surpris- ingly, it is following a similar development path, with increasing circuit complexity accompanied by shrinking circuit geometries. Redistribution layer (RDL) line widths, which were around 20μm in early implementations, will soon reach 2μm and are unlikely to stop there. Just as front-end processes placed increasing emphasis on enhanced process monitoring and control, advanced packaging processes will be forced to include more and better inspection and metrology capability at critical steps to maintain control and improve yields.

Advanced packaging processes, such as fan-out, face unique challenges that, for inspection systems, result in overcounting nuisance defects and undercounting yield-robbing critical defects. These advanced packaging techniques make extensive use of metal and organic polymers. Layers of metal are used to define conductive paths and organic polymer dielectric materials are used to provide insulation between conductors and planar surfaces between the layers. Dark field and bright field inspection results often include tens of thousands of nuisance defects. These occur because the inspection algorithms are designed to find random aberrations in highly repeatable patterns and the variable grain patterns of metal conductors appear as defects when are not. If not excluded, their large numbers can quickly overwhelm the real defects. Metal grain features can be as large as 50μm, much larger than RDL lines, which are currently as small as 2μm, and likely to reach 1μm in the near future.

Another class of defects that has proven difficult for conventional optical inspection techniques is caused by the presence of organic residues left after etching and descumming operations. They are hard to find because these materials tend to be transparent at visible wavelengths, yielding little signal in bright field and dark field inspection. They can be especially troublesome when they occur on contacts such as bumps and pillars. The new illumination method effectively eliminates nuisance noise from metal surface textures and enhances signal strength from organic defects.

ClearfindTM technology

The results presented here were all acquired using a FireflyTM inspection system (Rudolph Technologies) that incorpo- rates the new Clearfind (CF) illumination technology1. The new method takes advantage of the fact that many organic polymers exhibit distinctive optical properties that are not present in metals, silicon or other common inorganic materials used in semiconductor manufacturing. These properties tend to be unique to organic molecules displaying a high degree of conjugation, such as polycyclic aromatic hydrocarbons, and in linear or branched chain organic polymers with multiple regularly interspersed pi-bonds. This phenomenon results in the generation of a readily detectable, high color-contrast signal when the feature is appropriately illuminated against a metallic or other inorganic surface. The emission tends to be anisotropic and therefore less sensitive to surface topography that could potentially direct most ordinary bright field or dark field reflected light away from the detector. This results in increased sensitivity to organic residues and reduced sensitivity to interference from surrounding features. The method has the additional advantage of being relatively insensitive to signal variations caused by metal grains. FIGURE 1 presents a simplified illustration comparing the new technology to traditional white light inspection.

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The light source for the new technology is laser based, rather than the broadband source typically used in white light inspection systems. Thus, the light output is more stable in terms of both spectral range and output power. Autofocusing of the samples is accomplished using a patented high speed, near infrared-based laser triangulation system that maintains a constant distance between the imaging optics and the area being scanned. Images are acquired at high speed with a high-resolution camera. The result images compared in this article using bright field, dark field and CF technology were all acquired on the same inspection platform using different illumination techniques.

Through Silicon Via (TSV)

The sample is a 300mm silicon wafer with revealed TSV pillars2. TSV nail diameter is about 8μm and the distance between TSVs is about 56μm. The TSVs are on the backside of the wafer and the front side of the wafer is attached to a carrier.

In FIGURE 2a, the top shows a bright field image of two TSVs. The TSV on the left, circled in red, is covered with unetched organic residue and the TSV on the right, circled in green, is completely exposed. In the bright field image both TSVs look good and the residue is not visible. The images at the bottom left of figure 2 were acquired with CF technology and show the same TSVs. The TSV on the left, circled in red, has a bright blob while the one on the right, circled in green, is completely dark. The organic residue remaining on the left TSV now emits a readily detectable signal.

FIGURE 2b shows the inspection result from the full TSV wafer. The dots on the wafer map represent defect locations. There is a heavy concentration of organic residue on TSVs on the right side of the wafer. Metal pads approximately 35μm in diameter will be placed on top of the TSVs. Any organic residue between the TSV and the pad can cause deplanarization, which may result in connectivity issues when the die is stacked together. In addition, organic residue can increase the resistance of the contact when the die is stacked. If the defects are found before the next process step the wafer can be reworked.

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Under Bump Metal (UBM)

The sample is a 300mm wafer with RDL and under bump metallization (UBM). The UBM pads are about 50μm wide. In FIGURE 3a, the bright field image of two UBM pads shows the left pad is completely exposed and the right pad is covered with unetched organic film. However, the film is transparent and both pads look good in this image. Note the random metal texture visible in the bright field image, which adds noise and makes sensitive inspection for small defects more difficult. The image at lower left, acquired with CF technology, shows the same pads. The left pad, with no residue, appears black. The right pad, covered by residue, is significantly brighter. Also note that the metal texture seen in the bright field image with absent in CF illumination, permitting sensitive inspection for defects down to the pixel level.

FIGURE 3b shows a map of the full wafer where there is a heavy concentration of defects on UBM pads near the edge of the wafer. As in the TSV example, residue remaining on the UBM pads can cause increased resistance or loss of connectivity to a bump deposited on the pad. Bumps deposited on the residue are higher than normal bumps, leading to loss of coplanarity and connectivity issues. If the problem is found before starting the bump process, the wafer can be reworked and the residues removed.

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Redistribution Layer (RDL)

The sample is a 300mm molding compound wafer for fan-out packaging. FIGURE 4a shows a bright field image that includes a UBM pad and several RDL lines. The middle image shows the same area viewed with the new illumination technology. In the bright field image, the metal of the UBM pad and the RDL lines is very similar to the underlying metal visible through an interposed transparent film. The texture and graininess of the metals add noise to the image, increasing the difficulty of detecting small defects. Inspection with bright field illumination resulted in high nuisance defect counts without finding real process issues on the wafer. In FIGURE 4b, the top surface metal features, RDL and UBM, stand out against the background of the transparent film, while the underlying metal features are barely visible. FIGURE 4c shows a full wafer map acquired using CF technology and reveals a rectangular pattern that corresponds to the reticle of the lithography tool. The rectangular pattern was not visible in the bright field wafer map.

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FIGURE 5 shows additional RDL inspection results on the same wafer. CF technology revealed thinner lines toward the lower left corner of the reticle pattern. Ultimately, it was determined that these thinner lines were caused by a defect in the condenser lens of the lithography tool. The improved contrast between the first layer metal features in the underlying organic film, and the reduced noise, permitted more accurate and sensitive measurements using the new illumination technology. A bright field inspection of 20 wafers containing the same defect did not detect any thinner lines.

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Photoresist

The sample is a 300mm patterned silicon wafer from a large memory manufacturer3. It contains die approximately 11.7mm x 7.6mm in size, and containing arrays of about 9,000 metal pillars, each pillar approximately 22μm in diameter. The customer was interested to know if the new illumination technology would find defects not found by bright field inspection. FIGURE 6a shows a wafer map overlaying bright field defects (blue triangles) and CF defects (green triangles). In both cases the defects appear to be randomly distributed and not clustered. As depicted by the bar chart in FIGURE 6b, bright field illumination found 2,279 defects compared to 289 defects found by CF technology. Most interestingly, only 32 of the defects found by CF technology were also found with bright field inspection. 257 defects would have been missed by bright field inspection. The bar chart (FIGURE 6c) shows the size distribution of defects discovered by both techniques. Bright field inspection found a very large number of small defects (less than 5μm) and more defects larger than 25μm. Defects found by the CF technology were between 5-25μm in size.

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FIGURE 7 compares CF technology results (top) and bright field results (bottom). Each vertical pair shows a defect missed by bright field inspection and detected by CF technology. The enhanced brightness and circular shape of the defects detected by the new method strongly imply that they are associated with polymer residues. The enhanced brightness of the defects against the very black background is a unique and valuable feature of CF technology. Overall, these results demonstrate the value of supplementing bright field inspection with CF technology. All of the defects found by CF technology were of sufficient size to impact yield.

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Conclusion

Results shown here demonstrate the benefits of imaging with the new CF illumination technology when compared to conventional bright field illumination. The new technology allows detection of transparent organic residues that are not visible with bright field illumination.

It was also shown to detect types and sizes of defects that were not detected by bright field inspection. Equally important, its ability to reduce noise caused by metal texture and graininess significantly improves its sensitivity to small defects on metal features and dramatically reduces the detection of nuisance defects.

References

1. Gurvinder Singh, et al, “Advanced packaging lithography and inspection solution for next generation FOWLP-FOPLP processing”, IEEE Xplore, October 2016.
2. Woo Young Han, et al, “Inspection challenges in wafer level packaging”, International Wafer Level Packaging Conference, October 2017
3. Jonathan Cohen, et al, “Photoresist residue detection in advanced packaging”, International Wafer Level Packaging Conference, October 2017

The ConFab 2018, to be held at The Cosmopolitan of Las Vegas on May 21-23, is thrilled to announce the newest opening day Keynote speaker, Professor John M. Martinis. John is a Research Scientist who heads up Google’s Quantum AI Lab. He also holds the Worster Chair of Experimental Physics at the University of California, Santa Barbara. The lab is particularly interested in applying quantum computing to artificial intelligence and machine learning, and as one of Google’s quantum computing gurus, John shared the company’s “stretch goal”. That is to build and test a 49-qubit (“quantum bit”) quantum computer by the end of this year. The test will be a milestone in quantum computer technology.

The conference team is also very excited to have IBM distinguished Engineer, Rama Divakaruni – who is responsible for IBM Advanced Process Technology Research – present his Keynote Address: How Artificial Intelligence is driving the “New” Semiconductor Era. Both Keynotes, set for May 21, promise to be outstanding presentations.

Additional outstanding speakers at The ConFab 2018 include:

  • Dan Armbrust, CEO and Co-founder of Silicon Catalyst will present: “Enabling a Startup Ecosystem for Semiconductors” describing the current environment for semiconductor startups.
  • George Gomba, GLOBALFOUNDRIES VP of Technology Research will discuss the EUV lithography project with SUNY Polytechnic Institute now finding its way into advanced semiconductor manufacturing.
  • John Hu, Director of Advanced Technology for Nvidia – John heads up R&D of Advanced IC Process Technologies and programs, Design For Manufacturing, Testchips, and New technology/ IC product.
  • Tom Sonderman, President of Sky Water Technology Foundry will focus on smart manufacturing ecosystems based on big data platform, predictive analytics and IoT.
  • Kou Kuo Suu of ULVAC Japan will delve into manufacturing various types of NVM memory chips, including Phase-Change memory (PCRAM).

More industry experts adding to the conference will be announced soon.  Further event details are available at: www.theconfab.com.