As 3D NAND becomes the mainstream technology, its challenging roadmap poses opportunities for continued innovation.
BY HARMEET SINGH, Lam Research Corp., Fremont, CA
Since its introduction several years ago, 3D NAND has become a mainstream technology because of its ability to increase bit density in memory devices. Its adoption has been accelerated by advances in the underlying manufacturing processes that are enabling 3D architectures and lowering the cost per bit. With all its advantages, however, the overall complexity and capital intensity of 3D NAND manufacturing add significantly to the challenges fabs are facing in terms of process control, yield, and economics.
Market and technology drivers for 3D NAND
The main impetus for 3D NAND was the recognition that planar technology was approaching the end of its physical limits to deliver higher densities and a lower cost-per-bit. Past advances in conventional planar NAND technology have primarily been driven by physical scaling, where lithography capabilities determined just how many memory cells could fit within a given die size. Using multiple levels of charge within each cell by going from single- to multi-level cell designs has also enabled increased bit densities. However, these improvements typically have come at the expense of speed because of the need to differentiate between the multiple levels of charge. In addition, since the individual memory cells for these designs lie in a horizontal plane, scaling is still ultimately limited by lithography. Other challenges in scaling 2D NAND beyond the 15 nm node include cell-to-cell interference, unscalable dielectrics, and electron leakage [1].
To address these challenges, 3D NAND fundamentally changes the scaling paradigm. Instead of traditional X-Y scaling in a horizontal plane, 3D NAND scales in the Z-direction by stacking multiple layers of NAND gates vertically. This allows more cells to be packed into the same X-Y space (planar area) on the die without shrinking dimensions horizontally. By easing cell size requirements, triple- and even quadruple-level cell designs are possible. As such, 3D NAND offers a signif- icant increase in bit density over planar NAND.
Unlike planar NAND, where scaling is primarily driven by lithography, 3D NAND scaling is enabled by advances in deposition and etch processes. An incredible level of precision and repetition is required in defining complex 3D structures with extremely high aspect ratio (HAR) features. Achieving success with 3D NAND requires innovative deposition and etch solutions that minimize variability.
Overview of critical 3D NAND processes
The 3D NAND architecture requires advanced capabilities enabling HAR and complex structures (FIGURE 1). Critical processes involved include multilayer stack deposition, HAR channel etch, wordline metallization, staircase etch, HAR slit etch, and stair contacts formation. The following sections look at some of these areas in more depth and describe the most critical process parameters that must be controlled.
Film deposition
Creating stacked memory cells starts with depositing alternating layers of thin films. Unlike planar NAND, where cell pitch is defined by lithography, pitch in 3D NAND is determined by the film thickness. As such, precise control of layer-to-layer deposition uniformity is extremely important. Currently, commercial 3D NAND products in high-volume manufacturing have layers ranging from 32 to 48 pairs, while next-generation products with more than 60 pairs are now beginning high-volume ramps.
Critical requirements for depositing stacked films are the stress and uniformity of the individual layers within the overall stack. These requirements become more stringent and increasingly more challenging to meet as the number of layers grows. Wafer bow and local film stress (FIGURE 2) directly impact the ability to achieve precise lithog- raphy overlay. Film thickness and repeatability affects the active area of cell and consistency of the litho/etch performance. As a result, both film stress control and excellent uniformity are critical to wafer yields. To address these concerns, careful management of stress by tuning deposition conditions and optimizing integration is needed not only for the film stack deposition, but also throughout 3D NAND manufacturing.
High aspect ratio channel etching
HAR channel etch is the most critical and challenging step in 3D NAND because it is key to achieving uniform hole size through multiple layers to define the channel of memory cells. More than a trillion holes must be etched simultaneously and uniformly on every wafer, each with an aspect ratio of more than 40:1. For comparison, the highest aspect ratio structure that is etched in planar NAND is less than 15:1.
Deep etch on these multilayer stacks can push the limits of physics to achieve uniformity from top to bottom. As shown in FIGURE 3, the high aspect ratio of this etch leads to transport limitation challenges that can generate a range of problems. These include incomplete etch wherein some holes don’t reach the bottom, bowing, twisting, and CD variation between the top and bottom of the stack. Such defects can lead to shorts, interference between neighboring memory strings, and other perfor- mance issues. Solving these HAR-related transport issues requires precise control of high-energy ions during the etch process. Technologies that help deliver this capability include a symmetric chamber design for intrinsic uniformity, a proprietary high ion energy source with advanced plasma confinement and modulation, and orthogonal (independent) uniformity tuning knobs, such as multi-zone gas delivery and temperature control to achieve required uniformity across the wafer.
As the 3D NAND roadmap adds more layers to achieve higher bit density, channel hole etching becomes increasingly challenging due to higher aspect ratios. Managing the fundamental trade-offs among profile, selectivity, and CD requires continuous equipment innovation, not only to deliver HAR etching capabilities for more than 100 pairs, but also to do this at the productivity needed for volume manufacturing.
Wordline tungsten metal fill
For replacement-gate 3D NAND schemes, wordline tungsten fill provides the critical conductive links between individual memory cells within layers. This process is particularly challenging because of the need to achieve void-free fill of complex, narrow, lateral structures with minimal stress on the memory stack.
Due to the structural complexity, atomic-scale engineering is required for wordline fill. Traditional CVD tungsten films have inherent characteristics that limit capability for 3D NAND wordline fill. High tensile stress in CVD tungsten can lead to wafer bow, and fluorine in the process has been known to diffuse into adjacent layers where it can create yield-limiting defects. In addition, resistivity limits scaling: making each layer thinner would allow for more layers (more storage bits), but would also make wordline resistance too high. One approach to address these concerns is the use of a low-fluorine tungsten (LFW) ALD process. This has the ability to provide a smoother morphology that conforms better with the surface in each fill layer, thereby minimizing stress induced by the deposition process. Stress reduction by more than an order of magnitude has been demonstrated with LFW ALD technology. This approach has also been shown to lower fluorine content by up to 100x (FIGURE 4) and reduce resistivity by over 30% compared to conventional CVD tungsten.
Staircase etch
The staircase etch step creates the individual contact pads for each memory cell within the layers. A highly controlled etch process is used to define the size of each contact pad. To reduce the cost associated with lithography and improve productivity, repeated vertical etch and lateral trim etch processes are adopted to form the staircase instead of using numerous lithography steps. For each lithography pass, multiple staircase levels can be created by etching and trimming, as shown in FIGURE 5. The number of stairs that can be formed by this process is determined by the lateral-to-vertical (L/V) etch rate. Improving L/V etch selec- tivity can reduce the number of lithography steps needed.
Extreme accuracy is required to maintain the stair CD, thus avoiding misaligned contacts. If the CD for a pad is off by a few percent, that error will propagate through subsequent pads defined within the same lithography pass. Current technology can deliver uniform and repeatable stair CD precision of 1% (3-sigma) after more than five L/V trim processes. This is a critical factor for achieving high productivity and being able to scale to higher stacks with more layers economically.
Summary
Traditional planar scaling to increase NAND density is approaching its limits due to lithography and performance challenges. As 3D NAND becomes the mainstream technology, its challenging roadmap poses opportunitiesforcontinuedinnovation. Stress management throughout wafer processing is crucial, and significant innovations in both deposition and etch processes are essential in forming the HAR features that dominate 3D NAND architectures. Finally, reducing variability in every critical step is a must to meet performance, yield, reliability, and cost requirements.
3D NAND completely changes the scaling paradigm by going vertical. No longer limited by lithography capabilities, 3D NAND can achieve greater levels of integrity, perfor- mance, and reliability – while building vertically for higher bit density and a lower cost-per- bit – through relying on advances in deposition and etch processes.
References
1. Y.W. Park, Flash Memory, IEDM short course, 2015
