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By Jay Chittooran, Public Policy Manager, SEMI 

Two months after opposing $34 billion in U.S. trade tariffs on behalf of the U.S. semiconductor manufacturing industry, Jonathan Davis, global vice president of industry advocacy at SEMI, this week spoke out against an additional $16 billion duties on Chinese goods. Testifying before the same U.S. interagency panel mulling the merits of the tariffs, Davis called for the removal of 29 tariff lines covering items critical to semiconductor manufacturing including machines and spare parts used to make, wafers, flat panel displays and masks.

In his testimony to the panel, Davis stressed that while SEMI supports stronger protections against the theft of valuable intellectual property (IP), tariffs do little to address U.S. concerns over IP loss. Over the past month, SEMI has also submitted written comments and opposed the tariffs in public testimony. The panel includes representatives from the U.S. Trade Representative (USTR), Departments of Treasury, Commerce, State and Defense, and the Council of Economic Advisers.

Also testifying, Joe Pon, corporate vice president at Applied Materials, explained that the proposed tariffs will harm small and midsized companies and other U.S. business interests. Describing the tariffs as a tax on exports of high-value U.S. goods, Pon said the duties give non-U.S. firms an unfair competitive advantage.

In a parallel push to Davis’s testimony, SEMI, with more than 10 representatives from six member companies, met with 16 congressional offices this week to underscore the damage the tariffs would wreak on the U.S. semiconductor industry. The fallout would include higher operating costs, fewer exports and slower innovation. The tariffs would also curb industry growth and put thousands of high-paying, high-skill jobs at risk. SEMI pressed congressional leaders to reject the tariffs and support a push for congress to re-assert itself on trade policy.

Tariffs to cost U.S. SEMI members more than $500 million

SEMI estimates that the second list of proposed tariffs, covering about $16 billion in Chinese goods, will cost its 400 U.S. members more than $500 million annually in additional duties.

The tariffs on $34 billion in Chinese goods, which took effect July 6, impact products such as test and inspection equipment as well as spare parts that enter the U.S. from China. That round of tariffs will cost SEMI member companies and estimated tens of millions of dollars annually.

SEMI public policy team asks members to review tariff list

Looking ahead, SEMI encourages members to review the newly released $200 billion tariff list, determine any impact to their businesses and share their findings with SEMI’s public policy team.

The U.S. Trade Representative (USTR) has published the exclusion process for products subject to the China 301 tariffs. If your company’s products are subject to tariffs, you can request an exclusion.

In evaluating product exclusion requests, the USTR will consider whether a product is available from a source outside of China, whether the additional duties would cause severe economic harm to the requestor or other U.S. interests, and whether the product is strategically important or related to Chinese industrial programs (such as “Made in China 2025”).

The deadline for submitting product exclusion requests to USTR is October 9, 2018. Approved exclusions will be effective for one year upon approval and retroactive to July 6, 2018.

More information including the process for submitting the product exclusion request can be found here.

Any SEMI members with questions should contact Jay Chittooran, Public Policy Manager at SEMI, at [email protected].

After a quiet period due to the saturation of the mobile handset industry, the GaAs wafer market wakes up.  The technical choice made by Apple creates a real and vast enthusiasm for GaAs solutions. 3D sensing in mobile phone as well as LiDAR’s applications are giving a new breath for GaAs substrates suppliers.

Under its new technology & market report “GaAs Wafer & Epiwafer Market: RF, Photonics, LED and PV applications”, Yole Développement (Yole) announces a 15% CAGR between 2017 and 2023 (in volume), with an impressive 37%, especially for photonics applications (1).

GaAs analysis from Yole proposes a comprehensive overview of the GaAs wafer and epi wafer industry. This report outlines Yole’s understanding of the industrial landscape, its evolution as well as the technical challenges. The analysts are offering a relevant technical description of GaAs wafer and epiwafer growth. Market size and forecasts are also delivered in four big applicative markets: RF, Photonics, LED, and PV. Photonics applications are driving the GaAs wafer and epiwafer market into a new era. Yole’s analysts invite you to discover the latest GaAs technology and market trends.

Figure 1

 As one of the most mature compound semiconductors, GaAs has been ubiquitous as the building block of power amplifiers in every mobile handset. In 2018, GaAs RF business represents more than 50% of the GaAs wafer market. However, market growth has slowed down in the past couple years due to the handset market’s gradual saturation and shrinking die size. “At Yole, we expect GaAs to remain the mainstream technology for sub-6 GHz instead of CMOS, owing to GaAs’ high power and linearity performance as required by carrier aggregation and MIMO technology,” explains Dr. Hong Ling, Technology and Market Analyst at Yole.

Since 2017, GaAs wafer has been particularly notable in photonics applications. When Apple introduced its new iPhone X with a 3D sensing function using GaAs-based lasers, it paved the way for a significant boost in the GaAs photonics market. GaAs wafers market segment for photonics applications should reach US$150 million by 2023.

“GaAs-based ROY and infrared LED applications have also caught our attention”, asserts Dr. Ezgi Dogmus, Technology & Market Analyst at Yole. “We estimate, 2017-2023 CAGR achieves 21% (in units) for the total GaAs LED market, surpassing more than half of GaAs wafer volume by 2023.”

In terms of the wafer and epiwafer businesses, each application requires a different size and quality when determining wafer and epiwafer prices. As a new entrant, photonics applications will impose new specification requirements compared to the well-established RF and LED wafer and epiwafers, creating significant ASP diversity.

From a value chain point of view, the GaAs photonics market’s remarkable growth potential will offer plenty of opportunities for wafer, epiwafer, and MOCVD equipment suppliers, as well as for investors.
GaAs wafer supply: Sumitomo Electric, Freiberger Compound Materials, and AXT, involved in GaAs wafer supply, lead the market with about 95% of market share collectively. And since new laser applications have very high specification requirements for GaAs wafer that are constantly evolving, Yole analysts’ expect the top players to maintain their technical advantage for at least another 3 – 5 years.

Regarding GaAs epiwafer production, Yole’s analysts identified different business models. The GaAs LED market is principally vertically integrated, with very well-established IDMs like Osram, San’an, Epistar, and Changelight. In parallel, GaAs RF businesses outsource significantly from well-established epihouses.

Within the GaAs photonics market, the epi business is still applications-dependent. GaAs datacom market segment is mostly epi-integrated, with dominant IDMs like Finisar, Avago, and II-VI. For 3D sensing in smartphones, epi outsourcing is significant.

In 2017, Apple’s supplier Lumentum used IQE as its VCSEL epi supplier. This resulted in an almost 10x increase in IQE’s stock price. Other leading GaAs epihouses are in qualification or ramping up. Yole expects the photonic epiwafer market to behave similar to the GaAs RF epiwafer market.

By Pete Singer

In a keynote talk on Tuesday in the Yerba Buena theater, Dr. John E. Kelly, III, Senior Vice President, Cognitive Solutions and IBM Research, talked about how the era of Artificial Intelligence (AI) was upon us, and how it will dramatically the world. “This is an era of computing which is at a scale that will dwarf the previous era, in ways that will change all of our businesses and all of our industries, and all of our lives,” he said. “This will be another 50, 60 or more years of technology breakthrough innovation that will change the world.  This is the era that’s going to power our semiconductor industry forward. The number of opportunities is enormous.”

Dr. John E. Kelly, III, Senior Vice President, Cognitive Solutions and IBM Research

Kelly, with 40 years of experience in the industry, recalled how the first era of computing began with mechanical computers 100 years ago, and then transition into the programmable era of computing. In 1980, Kelly said “we were trying to stack two 16 kilobis DRAMs to get a 32 bit stack and we were trying to cram a thousand transistors into a microprocessor.” Microprocessors today have 15 billion transistors. “It’s been a heck of a ride,” he said.

IBM’s Summit is not only the biggest computer in the world, this is the smartest computer in the world, according to Kelly.

Kelly pointed to the power of exponentials, noting that Moore’s Law represented the first exponential and Metcalf’s Law — which says the value of the network increases as the square of the number of connected devices to the network – is the second exponential. Kelly said there’s no end to this second potential, as devices such as medical connected devices and Internet of thing devices get connected.

A third exponential is now upon us, Kelly said. “The core of this exponential is that data is doubling every 12 to 18 months. In fact, in some industries like healthcare, data is doubling every six months,” he said. The challenge is that the data is useless unless it can be analyzed. “Our computers are lousy in dealing with that large unstructured data and frankly there aren’t enough programmers in the world to deal with that explosion of data and extract value,” Kelly said. “The only way forward is through the use of machine learning and artificial intelligence to extract insights from that data.”

Kelly talked about IBM’s history of AI – teaching early system 600 machines to play checkers, beating chess grandmaster Gary Kasparov with Deep Blue, Watson’s Jeopardy wins and most recently, Watson Debater. That can “not only can answer questions but can listen to a person’s argument on something, reason and counter-argue in full natural language against that position in a full dialogue, continuously.”

What’s changed? “We continue to make advances in artificial intelligence, machine learning and deep learning algorithms that are just stunning,” Kelly said. “We are now able to learn over smaller and smaller amounts of data and translate that learning from one domain to another to another to another and start to get scale. Now is the time when this exponential is going to really explode.”

How does that equate to opportunity? Kelly said that on top of the existing $1.5-2B information technology industry, there’s another $2 trillion of decision support opportunity for artificial intelligence. “Literally every industry in the world, whether its industrial products, financial services, retail, every industry in the world is going to be impacted and transformed by this,” he said.

Quantum computing, which Kelly describe as a fourth exponential, is also coming which will in turn dwarf all of the previous ones. “Beyond AI, this is going to be the most important thing I’ve ever seen in my career. Quantum computing is a complete game changer,” he said.

The bad news? During his talk, Kelly sounded one cautionary note: “Companies that lead exponentials win. Companies that don’t lead, or even try to quickly follow, fail on exponential curves. Our industry is littered with examples of that,” he said.

Solid State Technology and SEMI today announced the recipient of the 2017 “Best of West” Award – BISTel for its Dynamic Fault Detection (DFD®) system. The award recognizes important product and technology developments in the electronics manufacturing supply chain. Held in conjunction with SEMICON West, the largest and most influential electronics manufacturing exposition in North America, the Best of West finalists were selected based on their financial impact on the industry, engineering or scientific achievement, and/or societal impact.

BISTel’s Dynamic Fault Detection (DFD®) system offers full trace data coverage and eliminating the need for timely and costly modeling and set up. DFD® is also a bridge to smart factory manufacturing because it integrates seamlessly to legacy FDC systems meaning customers can access the most comprehensive, and accurate fault detection system on the market. (South Hall Booth 1811).

“There’s a big emphasis in smart manufacturing at this year’s SEMICON West,” said Pete Singer, Editor-in-Chief of Solid State Technology. “The BISTel dynamic fault detection system is a great example of a fantastic smart tool now available to semiconductor manufacturers.”

About SEMI

SEMI® connects over 2,000 member companies and 1.3 million professionals worldwide to advance the technology and business of electronics manufacturing. SEMI members are responsible for the innovations in materials, design, equipment, software, devices, and services that enable smarter, faster, more powerful, and more affordable electronic products. FlexTech, the Fab Owners Alliance (FOA) and the MEMS & Sensors Industry Group (MSIG) are SEMI Strategic Association Partners, defined communities within SEMI focused on specific technologies. Since 1970, SEMI has built connections that have helped its members prosper, create new markets, and address common industry challenges together. SEMI maintains offices in Bangalore, Berlin, Brussels, Grenoble, Hsinchu, Seoul, Shanghai, Silicon Valley (Milpitas, Calif.), Singapore, Tokyo, and Washington, D.C.  For more information, visit www.semi.org and follow SEMI on LinkedIn and Twitter.

About Extension Media

Extension Media is a publisher of over 20 business-to-business magazines (including Solid State Technology), resource catalogs, newsletters and web sites that address high-technology industry platforms and emerging technologies such as chip design, embedded systems, software and infrastructure, intellectual property, architectures, operating systems and industry standards. Extension Media publications serve several markets including Electronics, Software/IT and Mobile/Wireless. Extension Media is a privately held company based in San Francisco, Calif. For more information, visit www.extensionmedia.com.

By Ed Korcynzski

Industry R&D consortium imec runs a series of technology forums around the world, starting in June in Antwerp, Belgium, and including a stop in July in San Francisco in coordination with SEMICON West. Greg McIntyre, imec Director of Advanced Patterning, discussed the state-of-the-art in Extreme Ultra-Violet (EUV) lithography technology with Solid State Technology during the Antwerp event. While still focusing on “path-finding” R&D for industry, the recent technology challenges associated with commercializing EUV lithography has pulled imec into work on patterning ecosystem materials such as resists and pellicles.

With each NXE:3400B model EUV stepper from ASML valued at US$125 million it costs $1 billion to invest in a set of 8 tools to begin high-volume manufacturing, and the entire lithography materials supply-chain is engaged in improving availability and throughput of this expensive tool-set. For high performance logic ICs we need EUV to reach the smallest and most powerful FETs possible, so EUV is in pilot production for logic chips at Samsung and TSMC this year, and will likely begin pilot ramps at Intel and GlobalFoundries next year.

The first use of EUV in IC HVM will be as “cut-masks” for use in self-aligned multi-patterning (SAMP) process flows that start with argon-fluoride-immersion (ArFi) deep ultra-violet (DUV) steppers. Such a first use allows for substitution of three ArFi “multi-color” cut-masks in place of the one EUV mask, in case there are unanticipated issues with the new EUV steppers. Second use in HVM will then happen using a single-exposure of EUV to pattern metal layers, but with no ability to use multiple ArFi exposure as a back-up.

“We will not put EUV in our critical path,” commented Dr. Gary Patton, GlobalFoundries’ CTO and SVP of Worldwide R&D, during a presentation in Antwerp, “But it’s clear that it’s coming and it will offer compelling advantages.” Patton said the company is experimenting with two of ASML’s EUV steppers in a New York fab, and will launch the company’s “7-nm-node” finFET production first with ArFi and then move to EUV when the throughput and uptime of the process make it affordable in their cost models.

Figure 1 shows the extremely small patterning process window around 18nm half-pitch line arrays (P36) using EUV lithography with Dipole source-mask optimization (SMO):  micro-bridging between lines starts below 15.5nm, while breaks within lines start above 18nm. These stochastic failures (Ref:  “Waddle-room for Black Swans:  EUV Stochastics”, SemiMD.com) are caused by variations in the photons absorbed by the resist (a.k.a. “shot noise”), the quantum efficiency of photo-acid generation (PAG) and diffusion, thequencher distribution,and optical and chemical interactions with under-layers for adhesion, anti-reflective coatings, and hardmasks.

Figure 1. Stochastic failures due to atomic-scale variability are shown in top-down CD-SEM images taken from 36-nm Pitch (P36) line/space arrays of post-etched photoresist that had been patterned using EUV lithography, which define the limits of the patterning process window when plotted as Percent Not-OK (%NOK) within an inspected area. (Source: imec)

Every nanometer of resolution is difficult to achieve when patterning below 20nm half-pitch, with many parameters contributing noise to the signal. For EUV lithography using reflective optics, the mask surface causes undesired “flare” reflections from the un-patterned area, such that bright-field masks inherently distort images more than dark-field masks. Since cuts typically only expose <20% of the field, these masks will be much less noisy as dark-fields.

Given the need for dark-field cut-masks, the ideal photoresist will be positive-tone (PT) which means that reformulations of Chemically-Amplified Resists (CAR) based on organic molecules can be used. Standard organic CAR tuned for ArFi lithography provides some sensitivity to EUV, and blends of standard CAR molecules can be tuned to improve trade-offs within the inherent Resolution, Line-Edge-Roughness (LER), and Sensitivity trade-off triangle. Consequently, all of the suppliers of ArFi CAR are capable of supplying some EUV CAR. Since stochastic effects are interdependent, resist vendors have to explore integration options within the entire stack of patterning materials.

JSR co-founded with imec the EUV Resist Manufacturing & Qualification Center NV (EUV RMQC) in Leuven, Belgium, where an EUV stepper at imec is available for experiments. “RMQC is running at full speed, and shipping out production lots,” said McIntyre. “Intel’s Britt Turkot mentioned at SPIE this year that the resist qualification work being done at IMEC has been very beneficial.”

ASML now owns the critical-dimension scanning-electron microscopy (CD-SEM) technology of Hermes Microvision Inc (HMI), and Neal Callan, ASML’s Vice President of Pattern Fidelity Metrology, spoke with Solid State Technologyabout controlling EUV patterning. Electron-beams cause shrinkage in organic films like CAR, and that shrinkage results in a CD bias that can be more than one nanometer. Different CAR formulations from different vendors shrink at different rates, and the effect is more difficult to model in 2D structures. ”We’re being pushed for accurate metrology in terms that can be quantified,” explained Callan. “The biggest issues are in terms of CD-bias with 2D features. We need to build more accurate models to create better data for OPC and for computational lithography, and also for our etch modeling peers.”

“Design rules for EUV need to be stochastically aware,“ confided McIntyre. “Designers need to know how much can be sacrificed in a design rule such as tip-to-tip spacing depending on the pattern pitch. There are different ways that we can think about minimizing stochastic effects.”

While stochastics and systematic yield losses increase in relative importance with decreasing device dimensions, losses due to random defects are also more difficult to control. Figure 2 shows second-generation EUV pellicles made from carbon nano-tubes (CNT) by imec to protect EUV masks from random particles while transmitting ~95%. First-generation pellicles reportedly transmit <90%.

Figure 2. Second generation EUV pellicles based on carbon nano-tubes (CNT) demonstrate increased transmission of ~95% while maintaining sufficient mechanical stability to protect reticles. (Source: imec)

“Today, new purity challenges are not only faced by the fab but also by their materials suppliers driving sharp increases in the use of filtration and purification systems to prevent wafer defects and process excursions,” explained Clint Harris, Senior Vice President and General Manager, Microcontamination Control Division, Entegris, to Solid State Technology.“The transition from 45nm- to 10nm-node has resulted in a 2.5x increase in the changeout frequency of filters as well as a 4x reduction of maximum allowable contaminant size. This trend is expected to continue as device parametric performance becomes more sensitive to particles, gels, metals, mobile ions, and other organic contaminants.”

[As a TECHCET Analyst, Ed Korczynski writes the TECHCET Critical Materials Report (CMR) on Photoresists & Ancillaries. https://techcet.com/product/photoresists-and-photoresist-ancillaries/]

Releasing its Mid-Year Forecast at the annual SEMICON West exposition, SEMI, the global industry association representing the electronics manufacturing supply chain, today reported that worldwide sales of new semiconductor manufacturing equipment are projected to increase 10.8 percent to $62.7 billion in 2018, exceeding the historic high of $56.6 billion set last year. Another record-breaking year for the equipment market is expected in 2019, with 7.7 percent forecast growth to $67.6 billion.

The SEMI Mid-Year Forecast predicts wafer processing equipment will rise 11.7 percent in 2018 to $50.8 billion. The other front-end segment, consisting of fab facilities equipment, wafer manufacturing, and mask/reticle equipment, is expected to jump 12.3 percent to $2.8 billion this year. The assembly and packaging equipment segment is projected to grow 8.0 percent to $4.2 billion in 2018, while semiconductor test equipment is forecast to increase 3.5 percent to $4.9 billion this year.

In 2018, South Korea will remain the largest equipment market for the second year in a row. China will rise in the rankings to claim the second spot for the first time, dislodging Taiwan, which will fall to the third position. All regions tracked except Taiwan will experience growth. China will lead in growth with 43.5 percent, followed by Rest of World (primarily Southeast Asia) at 19.3 percent, Japan at 32.1 percent, Europe at 11.6 percent, North America at 3.8 percent and South Korea at 0.1 percent.

SEMI forecasts that, in 2019, equipment sales in China will surge 46.6 percent to $17.3 billion. In 2019, China, South Korea, and Taiwan are forecast to remain the top three markets, with China rising to the top. South Korea is forecast to become the second largest market at $16.3 billion, while Taiwan is expected to reach $12.3 billion in equipment sales.

The following results are in terms of market size in billions of U.S. dollars:

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market. A subscription includes three reports: the monthly SEMI Billings Report, which offers an early perspective of the trends in the equipment market; the monthly Worldwide Semiconductor Equipment Market Statistics (SEMS), a detailed report of semiconductor equipment bookings and billings for seven regions and over 22 market segments; and the SEMI Mid-year Forecast, which provides an outlook for the semiconductor equipment market. For more information or to subscribe, please contact SEMI customer service at 1.877.746.7788 (toll free in the U.S.). For more information online, visit: http://info.semi.org/semi-equipment-market-data-subscription

By Paula Doe

Chip testing is becoming smarter and more complex, creating growing requirements to stream data in real time and ensure it is ready to use for analysis, regardless of the vendor source.

Adaptive testing using machine learning to predict die performance in a downstream test can reduce the number of cycles by as much as 40 per cent without compromising test performance, notes Dan Sebban, VP of data analysis, OptimalPlus, who’ll speak on machine learning challenges at SEMICON West’s Test Vision 2020 program. “As devices and their test requirements grow in complexity, the motivation for automating adaptive test greatly increases,” he states, adding that characteristics such as die location on the wafer, defects on neighboring die, condition of the tester, and test values near the specification limits can help predict which die are likely to be good.

“The big issue we see is that while everyone likes the idea of machine learning, it remains a black box model, with little visibility into why it makes the decisions it does,” adds Sebban. In addition, a suitable infrastructure to run, deploy and assess a machine learning model in real time is required. “There is still some hesitation to adopt machine learning. It’s a big change of mindset. While building the confidence to use machine learning will take time and experience, using the technology to automate big data analysis with the relevant infrastructure may be our best alternative to reduce test cost.”

Systems test and parts-per-billion quality become the rule

Systems test will continue to become more prominent and more complex as chips and packages shrink, affirms Stacy Ajouri, Texas Instruments system integration engineer and Test Vision 2020 event chair. “Even IC makers now need to start doing more systems test.” And as more ICs are used in automotive applications, the distinction between consumer and automotive requirements is blurring, driving demand in other markets for higher precision test with parts-per-billion defectivity requirements.

“Intelligent test gets increasingly challenging as devices become more complex and as testing moves from distinguishing good from bad devices to figuring out how to repair and trim marginal devices to make them good,” adds Derek Floyd, Advantest director of business development, this year’s program chair.

“We’re highlighting efforts to create the infrastructure the industry needs to manage big data for machine learning with test platforms from different vendors,” says Ajouri, citing work on new standards for streaming data from the testers and labeling critical steps in consistent language to simplify the use of data from different platforms in real time. “I have 10 platforms from multiple vendors, and I need them to mean exactly the same thing by ‘lot’ so I don’t have to sort it out before I can use the data,” she says.

Are devices becoming too complicated to test at the required price point?

Can testing be economical with up to a million die per wafer, 50 data points per die, a requirement for parts-per-billion accuracy, and the need to identify parts that test good now but that might fail in the future? Organizers of the event invite chipmakers and test suppliers to debate the issue. “The speed of innovation in the semiconductor industry challenges test to keep pace,” notes Floyd. “The product we’re testing is always ahead of the product we have to test it with.”

The two-day event features sessions on automotive test; big data and machine learning for adaptive test; handling and interface issues such as over-the-air testing;  and a general session covering memory and RF test.

Global semiconductor industry revenue declined 3.4 percent in the first quarter of 2018 falling to $115.8 billion. Semiconductor industry performance was negatively affected by the declining sales and first-quarter seasonality in the wireless communications market. Other sectors, such as automotive and consumer semiconductors, experienced nominal market growth, according to IHS Markit (Nasdaq: INFO).

The memory category experienced the highest growth of 1.7 percent in the first quarter, reaching $39.7 billion, as demand for memory components increased in the enterprise and storage markets. In fact, DRAM pricing and shipments both increased during the quarter, as strong demand for server DRAM continued to propel the semiconductor market. However, NAND began to show signs of softening, with slight revenue declines during the quarter, mainly due to single-digit price declines. “Even with the slight revenue decline during the quarter, the NAND market still achieved its second-highest revenue quarter on record, with strong demand coming from the enterprise and client solid-state drive markets,” said Craig Stice, senior director, memory and storage, IHS Markit.

Semiconductor market share

Led by its dominant position in the memory market, Samsung Electronics led the semiconductor industry in the first quarter of 2018, with 16.1 percent of the market, followed by Intel at 13.6 percent and SK Hynix at 7.0 percent. Quarter-over-quarter market shares were relatively flat, with no change in the top-three ranking list. However, on a year-over-year basis, Samsung supplanted Intel as the leading semiconductor company, compared to the first quarter of 2017.

Analog component sales for Texas Instruments, Maxim Integrated, ON Semiconductor and other companies with a strategic focus on industrial and automotive industries managed single-digit sales increases in the first quarter. In contrast, analog component revenue declined by double digits for Qualcomm, Skyworks Solutions, Oorvo and other companies targeting the wireless industry.

Memory IC companies — Samsung Electronics, SK Hynix, Micron Technologies and Toshiba — continued to dominate the top ten semiconductor companies. Micron achieved the highest growth rate in the top ten, recording 9.8 percent growth in the first quarter, compared to the previous quarter. Qualcomm revenue fell 13.6 percent, which was the largest sequential drop, due to the weakness in the wireless communication market. Qualcomm and nVidia were the only two fabless companies remaining in the top ten.

By Paula Doe, SEMI

With artificial intelligence (AI) rapidly evolving, look for applications like voice recognition and image recognition to get more efficient, more affordable, and far more common in a variety of products over the next few years. This growth in applications will drive demand for new architectures that deliver the higher performance and lower power consumption required for widespread AI adoption.

“The challenge for AI at the edge is to optimize the whole system-on-a-chip architecture and its components, all the way to semiconductor technology IP blocks, to process complex AI workloads quickly and at low power,” says Qualcomm Technologies Senior Director of Engineering Evgeni Gousev, who will provide an update on the progress of AI at the edge in a Data and AI program at SEMICON West, July 10-12 in San Francisco.

Qualcomm Snapdragon 845 uses heterogeneous computing across the CPU, GPU, and DSP for power-efficient processing for constantly evolving AI models. Source: Qualcomm

A system approach that optimizes across hardware, software, and algorithms is necessary to deliver the ultra-low power – to a sub 1-milliwatt level, low enough to enable always-on machine vision processing – for the usually energy-intensive AI computing. From the chip architecture perspective, processing AI workloads with the most appropriate engine, such as the CPU, GPU, and DSP with dedicated hardware acceleration, provides the best power efficiency – and flexibility for dealing with rapidly changing AI models and growing diversity of applications.

“But we’re going to run out of brute force options, so the future opportunity is more innovations with new architectures, dedicated hardware, new algorithms, and new software.” – Evgeni Gousev, Qualcomm Technologies

“So far it’s been largely a brute force approach using conventional architectures and cloud-based infrastructure,” says Evgeni. “But we’re going to run out of brute force options, so future opportunities lie in developing innovative architectures, dedicated hardware, new algorithms, and new software. Innovation will be especially important for AI at the edge and applications requiring always-on functionality. Training is mostly in the cloud now, but in the near future it will start migrating to the device as the algorithms and hardware improve. AI at the edge will also  remove some privacy concerns,  an increasingly important issue for data collection and management.”

Practical AI applications at the edge where resources are constrained run the gamut, spanning smartphones, drones, autonomous vehicles, virtual reality, augmented reality and smart home solutions such as connected cameras. “More AI on the edge will create a huge opportunity for the whole ecosystem – chip designers, semiconductor and device manufacturers, applications developers, and data and service providers. And it’s going to make a significant impact on the way we work, live, and interact with the world around us,” Evgeni said.

Future generations of chips may need more disruptive systems-level change to handle high data volumes with low power

A next-generation solution for handling the massive proliferation of AI data could be a nanotechnology system, such as the collaborative N3XT (Nano-Engineered Computing Systems Technology) project, led by H.S. Philip Wong and Subhasish Mitra at Stanford. “Even with next-generation scaling of transistors and new memory chips, the bottlenecks in moving data in and out of memory for processing will remain,” says Mitra, another speaker in the SEMICON West program. “The true benefits of nanotechnology will only come from new architectures enabled by nanosystems. One thing we are certain of is that massively more capable and more energy-efficient systems will be necessary for almost any future application, so we will need to think about system-level improvements.”

Major improvement in handling high volumes of data with low high energy use will require system-level improvements, such as monolithic 3D integration of carbon nanotube transistors in the multi-campus N3XT chip research effort. Source: Stanford University

That means carbon nanotube transistors for logic, high density non-volatile MRAM and ReRAM for memory, fine-grained monolithic 3D for integration, new architectures for computation immersed in memory, and new materials for heat removal. “The N3XT approach is key for the 1000X energy efficiency needed,” says Mitra.

“One thing we are certain of is that massively more capable and more energy efficient systems will be necessary for almost any future application, so we will need to think about system-level improvements.” – Subhasish Mitra, Stanford University

Researchers have demonstrated improvements in all these areas, including multiple hardware nanosystem prototypes targeting AI applications. The researchers have transferred multiple layers of as-grown carbon nanotubes to the target wafer to significantly improve CNT density. They have developed a low-power TiN/HfOx/Pt ReRAM whose low-temperature CNT and ReRAM processes enable multiple vertical layers to be grown on top of one another for ultra-dense and fine-grained monolithic 3D integration.

Other speakers at the Data and AI TechXpot include Fram Akiki, VP Electronics, Siemens; Hariharan Ananthanarayanan, motion planning engineer, Osaro; and David Haynes, Sr. director, strategic marketing, Lam Research.  See SEMICONWest.org.

IC Insights will release its 200+ page Mid-Year Update to the 2018 McClean Report next month.  The Mid-Year Update will revise IC Insights’ worldwide economic and IC industry forecasts through 2022 that were originally presented in the 2018 McClean Report issued in January of this year.

Figure 1 shows that IC Insights forecasts that China-headquartered companies will spend $11.0 billion in semiconductor industry capex in 2018, which would represent 10.6% of the expected worldwide outlays of $103.5 billion.  Not only would this amount be 5x what the Chinese companies spent only three years earlier in 2015, but it would also exceed the combined semiconductor industry capital spending of Japan- and Europe-headquartered companies this year.

Since adopting the fab-lite business model, the three major European producers have represented a very small share of total semiconductor industry capital expenditures and are forecast to account for only 4% of global spending in 2018 after representing 8% of worldwide capex in 2005.  Although there may be an occasional spike in capital spending from European companies (e.g., the surge in spending from ST and AMS in 2017), IC Insights believes that Europe-headquartered companies will represent only 3% of worldwide semiconductor capital expenditures in 2022.

It should be noted that several Japanese semiconductor companies have also transitioned to a fab-lite business model (e.g., Renesas, Sony, etc.).  With strong competition reducing the number and strength of Japanese semiconductor manufacturers, the loss of its vertically integrated businesses and thus missing out on supplying devices for several high-volume end-use applications, and its collective shift toward fab-lite business models, Japanese companies have greatly reduced their investment in new wafer fabs and equipment.  In fact, Japanese companies are forecast to represent only 6% of total semiconductor industry capital expenditures in 2018, a big decline from the 22% share they held in 2005 and an even more precipitous drop from the 51% share they held in 1990.

Figure 1

Although China-headquartered pure-play foundry SMIC has been part of the list of major semiconductor industry capital spenders for quite some time, there are four additional Chinese companies that are forecast to become significant semiconductor industry spenders this year and next—memory suppliers XMC/YMTC, Innotron, JHICC, and pure-play foundry Shanghai Huali.  Each of these companies is expected to spend a considerable amount of money equipping and ramping up their new fabs in 2018 and 2019.

Due to the increased spending by startup China-based memory manufacturers, IC Insights believes that the Asia-Pac/Others share of semiconductor industry capital spending will remain over 60% for at least the next couple of years.