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Worldwide semiconductor revenue totalled $419.7 billion in 2017, a 22.2 percent increase from 2016, according to preliminary results by Gartner, Inc. Undersupply helped drive 64 percent revenue growth in the memory market, which accounted for 31 percent of total semiconductor revenue in 2017.

“The largest memory supplier, Samsung Electronics, gained the most market share and took the No. 1 position from Intel — the first time Intel has been toppled since 1992,” said Andrew Norwood, research vice president at Gartner. “Memory accounted for more than two-thirds of all semiconductor revenue growth in 2017, and became the largest semiconductor category.”

The key driver behind the booming memory revenue was higher prices due to a supply shortage. NAND flash prices increased year over year for the first time ever, up 17 percent, while DRAM prices rose 44 percent.

Equipment companies could not absorb these price increases so passed them onto consumers, making everything from PCs to smartphones more expensive in 2017.

Other major memory vendors, including SK Hynix and Micron Technology, also performed strongly in 2017 and rose in the rankings (see Table 1).

 

2017 Rank

2016 Rank

Vendor

2017 Revenue

2017 Market Share (%)

2016 Revenue

2016-2017 Growth (%)

1

2

Samsung Electronics

61,215

14.6

40,104

52.6

2

1

Intel

57,712

13.8

54,091

6.7

3

4

SK Hynix

26,309

6.3

14,700

79.0

4

6

Micron Technology

23,062

5.5

12,950

78.1

5

3

Qualcomm

17,063

4.1

15,415

10.7

6

5

Broadcom

15,490

3.7

13,223

17.1

7

7

Texas Instruments

13,806

3.3

11,901

16.0

8

8

Toshiba

12,813

3.1

9,918

29.2

9

17

Western Digital

9,181

2.2

4,170

120.2

10

9

NXP

8,651

2.1

9,306

-7.0

Others

174,418

41.6

157,736

10.6

Total Market

419,720

100.0

343,514

22.2

Source: Gartner (January 2018)

Second-placed Intel grew its revenue 6.7 percent in 2017, driven by 6 percent growth in data center processor revenue due to demand from cloud and communications service providers. Intel’s PC processor revenue grew more slowly at 1.9 percent, but average PC prices are on the rise again after years of decline following the market’s shift from traditional desktops toward two-in-one and ultramobile devices.

The current rankings may not last long, however, “Samsung’s lead is literally built on sand, in the form of memory silicon,” said Mr. Norwood. “Memory pricing will weaken in 2018, initially for NAND flash and then DRAM in 2019 as China increases its memory production capacity. We then expect Samsung to lose a lot of the revenue gains it has made.”

2017 was a relatively quiet year for mergers and acquisitions. Qualcomm’s acquisition of NXP was one big deal that was expected to close in 2017, but did not. Qualcomm still plans to complete the deal in 2018, but this has now been complicated by Broadcom’s attempted takeover of Qualcomm.

“The combined revenues of Broadcom, Qualcomm and NXP were $41.2 billion in 2017 — a total beaten only by Samsung and Intel,” said Mr. Norwood. “If Broadcom can finalize this double acquisition and Samsung’s memory revenue falls as forecast, then Samsung could slip to third place during the next memory downturn in 2019.”

Through three quarters of calendar year 2017, market shares of top semiconductor equipment manufacturers indicate large gains by Tokyo Electron and Lam Research, according to the report “Global Semiconductor Equipment: Markets, Market Shares, Market Forecasts,” recently published by The Information Network, a New Tripoli-based market research company.

The chart below shows shares for the entire year of 2016 and for the first three quarters of 2017. Market shares are for equipment only, excluding service and spare parts, and have been converted for revenues of foreign companies to U.S. dollars on a quarterly exchange rate.

equipment shares

Market leader Applied Materials lost 1.3 share points, dropping from 28.2% in 2016 to 26.9% YTD (year to date). Gaining share are Tokyo Electron Ltd. (TEL), which gained 2.4 share points while rising from 17.0% in 2016 to 19.4% in 2017 YTD. Lam Research gained 1.6 share points and growing from a 19.0% share in 2016 to a 20.6% share in 2017 YTD.

On a competitive basis, Applied Materials competes against both competitors in conductor and dielectric etch equipment and in deposition equipment (atomic layer deposition [ALD] and non-tube low pressure chemical vapor deposition [LPCVD]). TEL also competes against Screen Semiconductor Solutions, which dropped 1.4 share points, in photoresist track and wet clean equipment.

According to SEMI, the industry consortium, semiconductor equipment grew 41% in 2017.

Industry enters the age of WOW


December 13, 2017

By Christian G. Dieseldorff, Industry Research & Statistics Group, SEMI, Milpitas, California

The semiconductor industry has been there before, with large increases in investments followed by dramatic downturns. While the most dramatic downturns, 2001 and 2009, were due to, in a large part, acro-economic factors, the industry has typically observed one to two years of increased investment spending followed by a down period. This time around, the industry will achieve a “WOW” with three consecutive years of fab investment growth, a pattern not observed since the mid-1990s.

Why are things different this time?  A diverse array of technology drivers promise more robust long-term growth, such as Mobile applications, Internet of Things (IoT), Automotive & Robotics, Industrial, Augmented Reality & Virtual Reality (AR&VR), Artificial Intelligence (AI), and 5G networking. Each of these new technologies inspires a big “WOW” as the industry embarks on the beginning of a promising journey of growth.

Driven by these technologies, on average the semiconductor revenue CAGR from 2016 to 2021 is forecasted to be 6 percent (in comparison to the previous 2011-2016 CAGR of 2.3 percent). For the first time in the industry’s history, semiconductor revenues will exceed the US$400 billion revenue milestone in 2017. Demand for chips is high, pricing is strong for memory, and the competition is fierce. All of this is spurring increased fab investments, with many companies investing at previously unseen levels for new fab construction and fab equipment. See Figure 1.

Figure 1

Figure 1

The World Fab Forecast report, published on December 4, 2017, by SEMI, is modeling that fab equipment spending in 2017 will total US$57 billion or 41 percent year-over-year (YoY) growth. In 2018, spending is expected to shoot up another 11 percent at US$63 billion. The two spending jumps in 2017 and 2018 are contributing to the “WOW” factor and to two consecutive years of record fab investments. Following historic large investments, some slowdown is expected for 2019.

Many companies, such as Intel, Micron, Toshiba (and Western Digital), and GLOBALFOUNDRIES, have increased fab investments in 2017 and 2018; however, the strong increases we see in both years are not caused by these companies but by one company and primarily one region. See Figure 2.

Figure 2

Figure 2

The first jump – a Big WOW – in 2017 is the surge of investments in Korea, due mainly to Samsung. Samsung is expected to increase its fab equipment spending by 128 percent in 2017 from US$8 billion to US$18 billion. No single company has invested so much in a single year in its fabs and much of its spending is in Korea. SK Hynix also increased fab equipment spending, by about 70 percent, to US$5.5 billion, its largest spending level in its history.  While the bulk of Samsung’s and SK Hynix’s spending remains in Korea, some will also go to China, and in the case of Samsung to the United States. Both Samsung and SK Hynix are expected to maintain high levels of investments for 2018.

The second jump – another WOW – is investment growth for 2018 in China. China is expected to begin equipping the many fabs that were constructed in 2017. In the past, non-Chinese companies made the majority of the fab investments in China but for the first time in 2018, Chinese-owned companies will approach parity, spending nearly as much on fab equipment as non-Chinese device manufacturers.

Between 2013 and 2017, fab equipment spending in China by Chinese-owned companies typically ranged between US$1.5 billion to US$2.5 Billion per year, while non-Chinese companies invested between US$2.5 billion to US$5 billion per year. In 2018, Chinese-owned companies are expected to invest about US$5.8 billion, while non-Chinese will invest US$6.7 billion. Many new companies such as Yangtze Memory Technology, Fujian Jin Hua, Hua Li, and Hefei Chang Xin Memory are investing heavily in the region.

New fabs being built

Historic highs in equipment spending in 2017 and 2018 reflect growing demand. This spending follows unprecedented growth in construction spending for new fabs also detailed in SEMI’s World Fab Forecast report. Construction spending will reach all-time highs with China construction spending taking the lead: US$6 billion in 2017 and US$6.6 billion in 2018, shattering another record – no region has ever spent more than US$6 billion in a single year for construction. More new fabs mean another wave of spending on equipping fabs in the next few years. See Figure 3.

Fab-forecast-Chart3

Figure 3

Considering all of these “WOW” factors, there is good reason to feel positive about the semiconductor industry. Even with a slowdown, the industry has and will continue to enjoy a positive outlook for long-term growth. In the meantime, hold on tight and enjoy the “WOW.”

More details are available in SEMI’s just-published World Fab Forecast, December 4, 2017, edition which covers quarterly data (spending, capacity, technology nodes, wafer sizes, and product types) per fab until end of 2018.

Today, SEMI, the global industry association representing the electronics manufacturing supply chain, released its Year-end Forecast at the annual SEMICON Japan exposition. SEMI projects that worldwide sales of new semiconductor manufacturing equipment will increase 35.6 percent to US$55.9 billion in 2017, marking the first time that the semiconductor equipment market has exceeded the previous market high of US$47.7 billion set in 2000. In 2018, 7.5 percent growth is expected to result in sales of US$60.1 billion for the global semiconductor equipment market – another record-breaking year.

The SEMI Year-end Forecast predicts a 37.5 percent increase in 2017, to $45.0 billion, for wafer processing equipment. The other front-end segment, which consists of fab facilities equipment, wafer manufacturing, and mask/reticle equipment, is expected to increase 45.8 percent to $2.6 billion. The assembly and packaging equipment segment is projected to grow by 25.8 percent to $3.8 billion in 2017, while semiconductor test equipment is forecast to increase by 22.0 percent to $4.5 billion this year.

In 2017, South Korea will be the largest equipment market for the first time. After maintaining the top spot for five years, Taiwan will place second, while China will come in third. All regions tracked will experience growth, with the exception of Rest of World (primarily Southeast Asia). South Korea will lead in growth with 132.6 percent, followed by Europe at 57.2 percent, and Japan at 29.9 percent.

SEMI forecasts that in 2018, equipment sales in China will climb the most, 49.3 percent, to $11.3 billion, following 17.5 percent growth in 2017. In 2018, South Korea, China, and Taiwan are forecast to remain the top three markets, with South Korea maintaining the top spot at $16.9 billion. China is forecast to become the second largest market at $11.3 billion, while equipment sales to Taiwan are expected to approach $11.3 billion.

The following results are in terms of market size in billions of U.S. dollars:

equipment forecast

By Inna Skvortsova, SEMI

Electromagnetic interference (EMI) is an increasingly important topic across the global electronics manufacturing supply chain.  Progressively smaller geometries of ICs, lower supply voltages, and higher data rates all make devices and processes more vulnerable to EMI. Electrical noise, EMI-induced signal generated by equipment, and factors such as power line transients affect manufacturing processes, from wafer handling to wire bonding to PCB assembly and test, causing millions of dollars in losses to the industry. Furthermore, conducted emission capable of causing electrical overstress (EOS) can damage sensitive semiconductor devices.  Intel consistently names EOS as the “number one source of damage to IC components.” (Intel® Manufacturing Enabling Guide 2001, 2010, 2016).

While EMC (Electromagnetic Compatibility) standards, such as the European EMC Directive and FCC Testing and Certification, etc. provide limits on allowed emission levels of equipment, once the equipment is installed along with other tools, the EMI levels in actual operating environments can be substantially different and therefore impact the equipment operation, performance, and reliability. For example, (i) Occasional transients induce “extra” pulses in rotary feedback of the servo motor which in time contributes to robotic arm’s erroneous position eventually damaging the wafer; (ii) Combination of high-frequency noise from servo motors and switched mode power supplies in the tool creates difference in voltage between the bonding wire/funnel and the device which causes high current and eventual electrical overstress to the devices; (iii) Wafer probe test provides inconsistent results due to high level of EMI on the wafer chuck caused by a combination of several servo motors in the wafer handler.  Field cases like these illustrate the gap between EMC test requirements and real-life EMI tolerance levels and its impact on semiconductor manufacturing and handling.

EMI on AC power lines

EMI on AC power lines

New standard, SEMI E176-1017, Guide to Assess and Minimize Electromagnetic Interference (EMI) in a Semiconductor Manufacturing Environment, developed by the NA Chapter of the Global Metrics Technical Committee bridges this gap. Targeted to IC manufacturers and anyone handling semiconductor devices, such as PCB assembly and integration of electronic devices, SEMI E176 is a practical guide as well as an educational document. SEMI E176 provides a concise summary of EMI origins, EMI propagation, measurement techniques and recommendations on mitigation of undesirable electromagnetic emission to enable equipment co-existence and proper operation as well as reduction of EOS in its intended usage environment. Specifically, E176 provides recommended levels for different types of EMI based on IC geometries.

“SEMI E176 is likely the only active Standard in the entire industry providing recommendations on both acceptable levels of EMI in manufacturing environments and the means of achieving and maintaining these numbers,” said Vladimir Kraz, co-Chair of the NA Metrics Technical Committee and president of OnFILTER, Inc. “E176 is also unique because it is not limited just to semiconductor manufacturing, but has application across other industries.  Back-end assembly and test, as well as PCB assembly are just as affected by EMI and can benefit from SEMI E176 implementation as there are strong similarities between handling of semiconductor devices in IC manufacturing and in PCB assemblies and prevention of defects is often shared between IC and PCBA manufacturers.”

The newly published SEMI E176 and recently updated SEMI E33-0217, Guide for Semiconductor Manufacturing Equipment Electromagnetic Compatibility (EMC),provide complete documentation for establishing and maintaining low EMI levels in the manufacturing environment.

Undesirable emission has operational, liability and regulatory consequences.  Taming it is a challenging task and requires a comprehensive approach that starts from proper system design practices and ends with developing EMI expertise in the field.  The new SEMI 176 provides practical guidance on reducing EMI to the levels necessary for effective high yield semiconductor manufacturing today and in the future.

SEMI Standards development activities take place throughout the year in all major manufacturing regions. To get involved, join the SEMI International Standards Program at: www.semi.org/standardsmembership.

 

The hows and whys of resin bleed-out (RBO) are discussed, as well as the impact it makes and how to control it.

BY RONGWEI ZHANG, ABRAM CASTRO and YONG LIN, Semiconductor Packaging, Texas Instruments Inc., Dallas, TX

Die attach pastes, which consist of resin, curing agent, catalyst, filler and additives, have been extensively used to attach die onto lead frames in various electronic packages such as small outline integrated circuit (SOIC), thin-shrink small outline package (TSSOP), quad flat package (QFP) and quad-flat no-lead (QFN). One of the issues commonly encountered during package assembly is resin bleed-out (RBO), or epoxy bleed out (EBO). RBO is the separation of some formulation ingredients in the paste from the bulk paste (see FIGURE 1). Depending on die attach paste formulations and lead frame surface chemistry and morphology, bleeding ingredients can be solvents, reactive diluents, low-molecular-weight resins, catalysts, and additives like adhesion promoter. Resin bleed out tends to occur on high energy surfaces such as metal lead frames without any organic coating. In particular, if plasma cleaning is utilized to remove the contaminants prior to assembly, the bleeding issue may become more pronounced due to the increase in surface energy. Bleed-out can occur once die attach pastes are dispensed on to lead frames or during thermal curing. As microelectronics continue to move towards smaller form factor, higher reliability and higher performance, control of RBO becomes increasingly critical for packages where there is a very little clearance between die and die pad edge, or between one die and another in multi-chip modules (MCMs).

Screen Shot 2017-12-05 at 1.29.34 PM

How resin bleed-out occurs

When die attach paste is dispensed onto a solid surface like lead frame surface, the paste will typically wet the surface partially. The adhesive force between die attach paste and lead frame surface causes the paste to spread while the cohesive force within the bulk paste will hold the ingredients together and avoid contact with a lead frame surface. The adhesive and cohesive forces are the intermolecular forces such as hydrogen bonding and Van der Waals forces. So the degree of wetting will depend on the balance between adhesive force and cohesive force. Bleed-out occurs when the adhesive force of some formulation ingredients to the substrate is stronger than the cohesive force within the paste. The driving force for bleed out is to minimize the surface energy of the substrate by wetting.

Impact of resin bleed-out

Resin bleed-out can cause several issues if it is not well controlled.

• If the formulation ingredients bleed from the periphery of the die attach pastes and covers the wire bonding area, then issues like non-stick on pad (NSOP) and weak wire bond can occur. It can also be an issue if bleeding occurs from the die attach fillet along die edge to the die top, contaminating the bond pad on die top surface [1].

• Resin bleed-out may affect the adhesion of mold compound to die pad or mold compound to die top surface, both of which can lead to delamination. In particular, die top delamination is strictly not allowed in wire-bonded packages because it can cause the ball bond to be mechanically lifted, thereby leading to electrical failures during temperature cycling [2].

• As the formulation ingredients bleed out of the bulk paste, the composition of die attach paste under die may change accordingly. This can impact the adhesion of die attach to lead frame adversely, leading to an adhesive failure [3].

Influence of surface roughness

There are many factors that can cause resin bleed-out, such as low surface tension of die attach pastes, high surface energy of metal lead frames, surface contami- nation, surface porosity and surface roughness. Here we will focus on the impact of surface roughness, which is critical to achieve high package reliability. Two die attach pastes were dispensed onto three lead frames with different surface roughness. The surface roughness of these three lead frames was characterized by Atomic Force Microscopy (AFM) using the roughness average (Ra) and the roughness ratio (r) (FIGURE 2). The roughness average (Ra) represents the arithmetic average of the deviations from the center plane. The roughness ratio is the ratio between the actual 3-D surface area calculated by AFM and the flat surface. The 3D morphologies of lead frames are shown in FIGURE 3. It was found that (a) there is a good correlation between the roughness ratio and resin bleed-out. As the surface roughness ratio increases, the bleeding becomes increasingly worse; (b) LF1 and LF2 have almost same Ra, but the bleeding performance of DA3 and DA4 are different. This indicates that the roughness average is not a good index for RBO; (c) DA4 is more resistant to bleed out than DA3.

Screen Shot 2017-12-05 at 1.30.15 PM

The relationship between surface roughness and the wettability has been described by Young equation (Equ. 1) and Wenzel equation (Equ. 2).

cos0y=(YS-YSL)/YL (1)0
cosöm=rcos0y (2)

Screen Shot 2017-12-05 at 1.29.41 PM Screen Shot 2017-12-05 at 1.29.48 PM

Where Ys, YL, YSL are surface tensions of the solid, liquid and interfacial tension between die attach paste and lead frame, respectively; 0y is the Young contact angle, 0m is the measured contact angle, and r is the roughness ratio. As the surface roughness increases, the better the wetting, and the worse the bleed-out if the contact angle is < 90o [4]. This is the case for die attach paste on a metal surface without anti-EBO coating.

Approaches to control resin bleed out

There are several approaches to control or eliminate resin bleed-out. These approaches include modifying formulation by selecting appropriate anti-EBO, using die attach film (DAF)/B-stage epoxy, controlling surface roughness, creating mechanical barrier, and lowering the surface energy of lead frames by surface coating.

• Modifying formulations. Generally, anti-bleeding agents are added to die attach pastes to reduce or eliminate RBO. Different anti-bleeding agents may have different working mechanisms. Some anti- bleeding agents are added to enhance the cohesiveness of the pastes while others are added to form a thin layer with a surface energy lower than the pastes themselves on a lead frame surface [5]. Therefore, tailoring die attach adhesives with appropriate anti-bleeding agents is critical to prevent RBO on different types of lead frames, while maintaining high adhesion to metal lead frames to achieve high reliability.

• Die Attach Film/B-stage Epoxy. The simplest and most effective way to eliminate RBO is to use die attach films or B-stage materials. However, there are limitations associated with this approach. These can include high material cost and capital investment, difficulty to achieve high adhesion and thus high reliability, and limited thermal performance of these materials.

• Mechanical barriers. In some cases, grooves on lead frames are designed in between die attach area and wire bond area to reduce resin bleed-out, as shown in FIGURE 4. This is a simple and cost-effective process. However, this approach may not work well if the bleeding is severe. Similarly, some low surface energy insulating film around a chip can be printed to confine the un-cure pastes to the space defined by the printed pattern [5].

Screen Shot 2017-12-05 at 1.30.23 PM

• Vacuum baking. Vacuum baking of ceramic substrates with gold or other metal surfaces has been reported to reduce bleed-out. Several mechanisms were proposed: (a) through removal of polar surface contaminant, which promotes bleed-out of lighter organic resin by dipole attraction or chemical reaction [6]; (b) through reducing the surface energy of the plating surface by the formation of Ni2O3 [7]; (c) through producing a coating of hydrocarbon by oil back streaming toreduce the surface energy [8]. The method is not recommended either due to lack of controllability or due to the detrimental effect on wire bonding quality [7]. A more controlled method to reduce or eliminate RBO is to treat the surface with known chemicals and controlled processes, as discussed below.

• Low surface energy coating. Roughened lead frames have been utilized to enhance package reliability, particularly to meet Automotive Grade 0 requirements or beyond, as they increase surface contact area and enhance mechanical interlocking. As shown in Fig. 2, a small increase in roughness can result in a severe bleed-out. Therefore, increasing surface roughness will promote bleed-out if there is no anti-EBO on the surface. According to Young’s equation, decreasing surface energy will increase the contact angle, i.e. decreasing the wetting of the surface. Therefore, in roughened lead frame manufacturing, a solution of low surface energy material is used to treat roughened lead frames to lower their surface energy to reduce or eliminate RBO. Alternatively, a thin layer of film can be deposited onto the assembly surface by gas plasma technology to modify the surface energy [9]. FIGURE 5 shows water contact angles of lead frames with or without anti-EBO treatment. The anti-EBO coating will increase the contact angle on standard lead frame as explained by Young’s equation. Compared with standard lead frames, roughened lead frames have an increasing roughness and the anti-EBO coating on roughened lead frames further increases contact angle significantly. This can be explained by Wenzel equation, which demonstrates that adding surface roughness will increase surface hydrophobicity if the surface is chemically hydrophobic. In addition, Fig. 5 shows the resin bleed-out performances of a die attach paste (DA2) on these three types of lead frames. Bleed out was observed on the standard lead frame without anti-EBO, but there was no bleeding on both standard and roughened lead frame with anti-EBO coating. The low surface energy anti-EBO coating eliminates resin bleed out.

Screen Shot 2017-12-05 at 1.30.31 PM

Summary

This article provides an understanding of how bleeding occurs, the impact of bleeding, and methods to control bleeding. Bleeding is the result of the interaction between die attach pastes and metal lead frames. In particular, we studied the influence of surface roughness on RBO of different die attach materials, and found that there is a good correlation between the roughness ratio and bleed-out performance. Reducing the surface roughness will reduce or eliminate RBO. It is noteworthy that there is a line between reducing roughness to achieve no RBO and increasing roughness to ensure excellent delamination performance for lead frames without Anti-EBO. In terms of die attach pastes, the most effective way to control RBO seems to be the surface coating with anti-RBO without affecting other performances like delamination, or combining this method with others to provide an even better solution.

References

1. B. Neff, J. Huneke, M. Nguyen, P. Liu, T. Herrington, S. K. Gupta, “No bleed die attach adhesives”, IEEE International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005, pp. 1-3.
2. R. W. Zhang, Y. Lin, A. Castro, “Solving delamination in lead frame- based packages”, Chip scale review, 2015, pp. 44-48.
3. S. Kanagavel, D. Hart, “Optimization of die attach to surface-enhanced lead frames for MSL-1 performance of QFN packages”, Chip scale review, 2017, pp. 35-38.
4. J.-C. Hsiung, R.A. Pearson, T.B. Lloyd, “A surface energy approach for analyzing die attach adhesive resin bleed,” J. of Adhesion Science and Technology, 2003, 17, No. 1, pp. 1-13.
5. H. Schonhorn, L. H. Sharpe, “Liquids with reduced spreading tendency”, US Patent 4,483,898.
6. J. Ireland, “Epoxy bleedout in ceramic chip carriers”, Int. J Hybrid Microelectron., 1982, 5, pp. 1-4.
7. M. R. Marks, J. A. Thompson, R. Gopalakrishnan, “An experimental study of die attach polymer bleedout in ceramic packages”, Thin Solid Film, 1994, 252, pp. 54-60.
8. N. Tan, K. H. H. Lim, B. Chin, A. J. Bourdillon, “Engineering surface in ceramic pin grid array packaging to inhibit epoxy bleeding”, The Hewlett-Packard Journal, 1998, pp. 81-89.
9. M. Burmeister, “Elimination of epoxy resin bleed through thin film plasma deposition”, Proceeding of the 36th international IMAPS conference, Boston, MA, 2003, pp. 780-785.

By Walt Custer, Custer Consulting

SEMICON Europa 2017 and productronica were co-located November 14 to 17 at Messe Munchen in Munich, Germany. Attendance was very good and the mood was upbeat.

The third quarter of this year has seen broad growth both globally and also for the European electronic supply chain.

Chart 1 shows 3Q’17/3Q’16 growth by electronic sector for the world. SEMI and PCB process equipment and semiconductors stand out but almost all key sectors expanded.

Custer-Chart-1-Global-Elec-

Chart 2 shows third quarter growth for Europe.  SEMI equipment leads but the third quarter Eurozone expansion was broad based.

Custer-Chart-2-EUropean-Ele

At productronica, Custer Consulting presented at the “Business Outlook for the Global Electronic Supply Chain” event (with emphasis on Europe).  For a copy of Walt’s charts, please email [email protected].

The semiconductor industry continued its upward trend in the third quarter of 2017, notching 12 percent sequential growth with strength across all application markets, according to IHS Markit (Nasdaq: INFO). Global revenue totaled $113.9 billion, up from $101.7 billion in the second quarter of 2017.

As memory prices remain high and the wireless market continues to see strong demand through the fourth quarter, 2017 is shaping up to be a record-breaking year for the semiconductor industry. IHS Markit projects that semiconductor revenue will reach a record-high $428.9 billion in 2017, representing a year-over-year growth rate of 21 percent.

Key growth drivers

All application end markets posted sequential growth over the prior quarter, with wireless communications and data processing categories leading the pack.

Revenue from wireless applications grew faster sequentially in the third quarter of 2017 than any of the other high-level application markets. Semiconductor revenue from wireless applications was a record high $34.8 billion in the third quarter, representing nearly 31 percent of the total semiconductor market. IHS Markit anticipates an even bigger fourth quarter for wireless applications, projecting $37.5 billion in revenue — and more than $131 billion for the full-year 2017.

As the wireless market evolves, this growth can be attributed to a number of factors. ”More complex and comprehensive smartphone systems on a chip are supporting applications such as augmented reality and computational photography,” said Brad Shaffer, senior analyst for wireless semiconductors and applications at IHS Markit. “Premium smartphones have increasing amounts of memory and storage. The radio frequency content in these smartphones has also grown considerably over the past few product generations, with many high-end smartphones now supporting gigabit LTE mobile broadband speeds.”

The memory markets proved once again to be the driving force and highest-growing segment for semiconductors in the third quarter of 2017. “The DRAM industry had another record quarter with $19.8 billion in revenue, exceeding the prior record by more than $3 billion,” said Mike Howard, director for DRAM memory and storage research at IHS Markit. “Prices and shipments were up during the quarter as strong demand for mobile and server DRAM continued to propel the market.”

Top_5_memory

The NAND industry had another record quarter as well, growing 12.9 percent in the third quarter of 2017, with total revenue reaching $14.2 billion. “Pricing was flat in the quarter, as seasonally strong demand driven by the mobile and solid-state drive segments was able to offset moderate shipment growth,” said Walter Coon, director for NAND flash technology research at IHS Markit. “The market is expected to soften exiting 2017 and into early next year, as the industry transition to 3D NAND technology continues to progress and the market enters a traditionally slower demand period.”

Manufacturer moves

Samsung officially passed Intel to become the number-one semiconductor supplier in the world in the third quarter of 2017, growing 14.9 percent sequentially. Intel now comes in at number two, with SK Hynix securing the third rank in terms of semiconductor revenue for the third quarter.

top_5_semiconductor

Among the top 20 semiconductor suppliers, Apple and Advanced Micro Devices (AMD) achieved the highest revenue growth quarter over quarter by 46.6 percent and 34.3 percent, respectively.

There was a good deal of market share movement within the top 10 suppliers throughout the third quarter as well. In terms of semiconductor revenue, Qualcomm surpassed Broadcom Limited to secure the number-five spot, while nVidia made its way into the top 10 ranking for the first time ever. At this time last year, the top five semiconductor companies controlled 40 percent market share of the entire industry. The top five gained 4.2 percent more market share this year over last year, while comprising three memory companies instead of the previous two.

More information on this topic can be found in the latest release of the Semiconductor Competitive Landscaping Tool (CLT) from the IHS Markit Semiconductor Competitive Landscape CLT Intelligence Service.

IC Insights has revised its outlook for semiconductor industry capital spending and will present its new findings in the November Update to The McClean Report 2017, which will be released at the end of this month.  IC Insights’ latest forecast now shows semiconductor industry capital spending climbing 35% this year to $90.8 billion.

After spending $11.3 billion in semiconductor capex last year, Samsung announced that its 2017 outlays for the semiconductor group are expected to more than double to $26 billion.  Bill McClean, president of IC Insights stated, “In my 37 years of tracking the semiconductor industry, I have never seen such an aggressive ramp of semiconductor capital expenditures.  The sheer magnitude of Samsung’s spending this year is unprecedented in the history of the semiconductor industry!”

Figure 1 shows Samsung’s capital spending outlays for its semiconductor group since 2010, the first year the company spent more than $10 billion in capex for the semiconductor segment.  After spending $11.3 billion in 2016, the jump in capex expected for this year is simply amazing.

To illustrate how forceful its spending plans are, IC Insights anticipates that Samsung’s semiconductor capex of $8.6 billion in 4Q17 will represent 33% of the $26.2 billion in total semiconductor industry capital spending for this quarter.  Meanwhile, the company is expected to account for about 16% of worldwide semiconductor sales in 4Q17.

IC Insights estimates that Samsung’s $26 billion in semiconductor outlays this year will be segmented as follows:

3D NAND flash: $14 billion (including an enormous ramp in capacity at its Pyeongtaek fab)

DRAM: $7 billion (for process migration and additional capacity to make up for capacity loss due to migration)

Foundry/Other: $5 billion (for ramping up 10nm process capacity)

annual samsung capex

IC Insights believes that Samsung’s massive spending outlays this year will have repercussions far into the future. One of the effects likely to occur is a period of overcapacity in the 3D NAND flash market. This overcapacity situation will not only be due to Samsung’s huge spending for 3D NAND flash, but also to its competitors in this market segment (e.g., SK Hynix, Micron, Toshiba, Intel, etc.) responding to the company’s spending surge.  At some point, Samsung’s competitors will need to ramp up their capacity or loose market share.

Samsung’s current spending spree is also expected to just about kill any hopes that Chinese companies may have of becoming significant players in the 3D NAND flash or DRAM markets.  As our clients have been aware of for some time, IC Insights has been extremely skeptical about the ability of new Chinese startups to compete with Samsung, SK Hynix, and Micron with regards to 3D NAND and DRAM technology.  This year’s level of spending by Samsung just about guarantees that without some type of joint venture with a large existing memory suppler, new Chinese memory startups stand little chance of competing on the same level as today’s leading suppliers.

The temperature impact on the performance of UHP pressure transducers is discussed.

BY YANLI CHEN, Ph.D. and MATTHEW MILBURN, P.E., UCT, Hayward, CA

As the semiconductor industry develops new films that require heated delivery systems, all related components need to be characterized at elevated temperatures. Vacuum pressure measurement components, typically called manometers, have been used at elevated temperatures for many years. In fact, many of the vacuum measurement transducers are internally heated to a known temperature to stabilize the mechanical relationships between moving parts and the sensors used to measure the movement. This stabilization enables the precision and inaccuracy of the measurement to be greatly improved. For positive pressure UHP transducers, this elevated temperature characterization has not been done. Based on the testing performed at UCT, temperature related performance variations are very real and must be carefully considered before choosing a positive pressure transducer for elevated temperature use. Since the industry is driving toward higher delivery system operating temperatures, temperature effects will become more important.

The UHP pressure transducer is a widely-used component in the semiconductor industry and the performance is very important for process control and process monitoring. Selecting a proper UHP pressure transducer with good performance for the specific application is challenging, because different UHP pressure transducers manufacturers have different parameters listed in their data and specification sheets. Behind the data presented, it was found that different test procedures and data processing methods were used to determine and report performance characteristics. This reality creates a situation where, without standardized test method or reporting format, neither the specifier nor the end user can compare the performance of different brands of pressure transducers. To date, the industry has not recognized the full scope of the specification problem nor developed a standardized testing and reporting program. A new push toward standardization has become available with the publishing of SEMIF113 “Test Method For Pressure Transducers Used In Gas Delivery Systems” in November of 2016.

In order to have a better understanding about the performance of different UHP pressure transducer manufacturers’ products, UCT initialized a comprehensive performance evaluation project with a participation of three major UHP pressure transducer manufacturers (MFG A, MFG B and MFG C). The totality of the project covered a total of nine test categories, including warm up time test, input voltage sensitivity test, repeatability, linearity, hysteresis and inaccuracy test, reproducibility test, thermal coefficient test, drift test, accelerated lift cycle test, proof and burst test. The topic of this paper is the thermal coefficient test. Interested readers can find the other article “Comprehensive performance evaluation of UHP pressure transducers” published on the VOL. 59 NO. 4 of Solid State Technology (June 2016), which demonstrated the test method of repeatability, linearity, hysteresis and inaccuracy.

Ideally, a pressure transducer would sense pressure and remain unaffected by other environmental changes. In reality, however, the signal output of every pressure transducer is somewhat affected by variations in environment and fluid temperature. Temperature changes can cause the expansion and contraction of the sensor materials, fill fluids, housings, and electronics. Temperature changes also can affect the sensor’s resistors and electrical connections through the thermoelectric effects. Typically, a sensor’s behavior regarding changes in temperature is characterized by two temperature coefficients: temperature effect on zero (TC zero) and temperature effect on span (TC Span). TC zero is expressed as a percentage of full scale and indicates the greatest deviation of a pressure transducer at zero setpoint per equal temperature change (such as 10K or 50°C) during the operating temperature range. TC span is also expressed as a percentage of full scale and indicates the greatest deviation of a pressure transducer at 100%FS setpoint per equal temperature change (such as 10K or 50°C) during the operating temperature range. FIGURES 1, 2 and 3 list the TC zero and TC span of pressure transducer products of MFG A, MFG B and MFG C, respectively.

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Comparing the three thermal coefficient specifications above for MFG A, MFG B and MFC C, it is not possible to conclude which manufacturer’s product is the best for thermal behavior. Therefore, a standard test method and data process for thermal effects evaluation is needed.

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Test setup and procedure

Three major UHP pressure transducer manufacturer (MFG A, MFG B, and MFG C) participated in this comprehensive performance evaluation project by providing test samples. Table 1 shows the detailed information of all the devices under tests (DUTs). Twelve DUTs were installed in a test fixture designed by UCT for running simultaneous tests. The schematic of the test fixture is shown in FIGURE 4. The benefit of this design is to save significant time that would be otherwise used for assembly, disassembly, and testing, and eliminates the potential for setup errors if each transducer was tested separately in the battery of tests.

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The test was conducted in a temperature controlled environmental chamber (see Figure 5). The following sequence of steps were taken:

• A leak integrity test
• Make the initial zero adjustment per the manufacturer’s instructions
• Adjust the temperature of the environmental chamber to 0°C and allow the temperature to stabilize for a minimum period of two hours.
• Adjust the pressure to 0% FS (-14.7 psig), and record the signal output of all the DUTs and the pressure reference device after the pressure stabilization.
• Adjust the pressure to 100% FS(235.3 psig),andrecord the signal output of all the DUTs and the pressure reference device after the pressure stabilization.
• Repeat the same procedure for the temperature setpoints of 20°C, 40°C and 60°C at the pressure setpoints of 0%FS and 100%FS.

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Results and discussion

The TC zero (0%FS) and TC span (100%FS) values of all DUTs are listed in Table 2. For each manufacturer’s sample group, the highest value for the thermal coefficients at zero and span are highlighted in red; the lowest value for the thermal coefficients at zero and span are highlighted in green. To reiterate, the smaller the TC value, the better.

• For the DUTs from MFG A, the smallest TC zero is 0.0022%FS/°C and the smallest TC span is 0.0324%FS/°C.
• For the DUTs from MFG B, the smallest TC zero is 0.0012%FS/°C and the smallest TC span is 0.0099%FS/°C.
• For the DUTs from MFG C, the smallest TC zero is 0.0102%FS/°C and the smallest TC span is 0.0215%FS/°C.
• For the DUTs from MFG A, the largest TC zero is 0.0127%FS/°C and the largest TC span is 0.0564%FS/°C.
• For the DUTs from MFG B, the largest TC zero is 0.0042%FS/°C and the largest TC span is 0.0155%FS/°C.
• For the DUTs from MFG C, the largest TC zero is 0.0283%FS/°C and the largest TC span is 0.0354%FS/°C.

The extreme TC values for each manufacturer are summarized in Table 3. As shown in this table, the MFG B product has the lowest value (0.0042%FS/°C) and MFG C product has the highest value (0.0283%FS/°C) for the TC zero. For the TC span, the MFG B product still has the lowest value (0.0155%FS/°C), and the MFG A product has the highest value (0.0564%FS/°C).

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To compare the results to the published specification from MFG A, the results needed to be converted and are listed in Table 4.

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Comparing test results with the published specifications (FIGURE 1), the MFG A devices are meeting their thermal coefficient specification.

To compare the results to the published specification from MFG B, the results needed to be converted and are listed in Table 5.

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Compared with the published specifications (FIGURE 2), the MFG B devices are meeting their thermal coefficient specification at zero. All the MFG B devices except DUT 6 meet the of the thermal coefficient specification at span. However, the TC span for DUT 6 is 0.15550%FS/10K, which is very close to the specification value (0.15%FS/10K).

To compare the results to the published specification from MFG C, the results needed to be converted and are listed in Table 6.

Screen Shot 2017-11-08 at 1.45.15 PM

Compared to the published MFG C specifications (FIGURE 3), the MFG C devices are meeting their thermal coefficient specification.

The error change with the temperature increase of all the DUTs at 0%FS is shown graphically in FIGURE 6. Comparing the three plots, it can be seen that the DUTs from manufacturer C have the largest thermal variation across the temperature range of the test as well as device to device variation. The DUTs from manufacturer B have the smallest thermal variation across the temperature range of the test as well as device to device variation.

The error change with the temperature increase of all the DUTs at 100%FS is shown graphically in FIGURE 7. Comparing the three plots, it can be seen that the DUTs from manufacturer C have the largest thermal variation across the temperature range of the test as well as device to device variation. The DUTs from manufacturer B have the smallest fluctuation across the temperature range.

Conclusion

Based on this study, transducers marketed as comparable to each other display dramatically different performance levels within a relatively small temperature range which could lead to process reproducibility challenges. As the demand for higher temperature applications increases, these temperature performance variances will become more pronounced. These variations may prove to be very problematic with tool-to-tool process replication or when a transducer is replaced as a repair activity and the new transducer does not have the same performance characteristic as the old unit. The test results also demonstrate that the published specifications need to be standardized to improve direct comparison by end users. In addition, a uniform test procedure and data processing method needs to be adopted by the industry. The pressure measurement task force of SEMI North America Gases and Facilities Committee has developed and published a new pressure transducer measurement standard in November of 2016 based on this study.

Temperature-related shift not only contributes to the overall inaccuracy of a pressure transducer in a particular application, but they also factor into the economics of designing and manufacturing pressure transducers. This is due to the fact that temperature compensation is a complex, time-consuming, and expensive process that requires a significantly larger investment in production equipment and a deeper understanding of the influencing parameters.

References

1. Chemical Engineering Progress (CEP), June 2014 Gassmann, E. (2014, June) Pressure Sensor Fundamentals: Interpreting Accuracy and Error, 37-45
2. IEC 61298-3 Process measurement and control devices-General methods and procedures for evaluating performance-Part 3: Tests for the effects of influence quantities
3. SEMI C59-1104-0211R Specifications and Guidelines for Nitrogen
4. SEMI F1-0812 Specification for leak integrity of high-purity gas piping systems and components
5. SEMI F62-1111 Test method for determining mass flow controller performance characteristics from ambient and gas temperature effects
6. SEMI F113-1116 Test method for pressure transducers used in gas delivery systems