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The RC delay issues started a few nodes ago, and the problems are becoming worse.

BY ZSOLT TOKEI, imec, Leuven, Belgium

With the 7nm technology node in the development phase and the 5nm node moving into development, transistor scaling gets ever more complex. On top of that, the performance benefits gained at the front-end-of-line (i.e., the transistors) can easily be undone if the back-end-of-line can’t come along. BEOL processing involves the creation of stacked layers of Cu wires that electrically interconnect the transistors in the chip. Today, high-end logic chips easily have 12 to 15 levels of Cu wires. With each technology node, this Cu wiring scheme becomes more complex, mainly because there are more transistors to connect with an ever tighter pitch. Shrinking dimensions also means the wires have a reduced cross-sectional area, which drives up the resistance-capacitance product (RC) of the interconnect system. And this results in strongly increasing signal delay. The RC delay issues started a few nodes ago, and the problems are becoming worse. For example, a delay of more than 30% is expected when moving from the 10nm to the 7nm node.

The current BEOL flow

Cu-based dual damascene has been the workhorse process flow for interconnects since its introduction in the mid 1990s. A simple dual damascene flow starts with the deposition of a low-k dielectric material on a structure. These low-k films are designed to reduce the capacitance and the delay in the ICs. In a next step, this dielectric layer is covered with an oxide and a resist, and vias and trenches are formed using lithography and etch steps. These vias connect one metal layer with the layer above or below. Then, a metallic barrier layer is added to prevent Cu atoms from migrating into the low-k materials (FIGURE 1). The barrier layers are deposited with physical vapor deposition, using materials such as tantalum and tantalum nitride, and subsequently coated by a Cu seed barrier. In a final step, this structure is electroplated by Cu in a chemical mechanical polishing (CMP) step.

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A 5nm technology full dual damascene module

The semiconductor industry is hugely in favor of extending the current dual damascene technology as long as possible before moving to a new process. And this starts with incremental changes to the current technology, which should suffice for further scaling to at least the 5nm technology node. Researchers at imec have demonstrated a full dual damascene module for the 5nm technology node. At this node, the BEOL process becomes extremely complex, and interconnects are designed at very tight pitches. For example, a 50% area scaling in logic and 60% scaling of an SRAM cell from 7nm to 5nm results in a gate pitch at around 42nm and an intermediate first routing metal at 32nm pitch (or 16nm half pitch, which is half the distance between identical features). In these BEOL layers, trenches are created which are then filled with metal in a final metallization step. In order to create electrically functional lines, perpendicular block layers to the trenches are added, where metal traces are not formed. One of the many challenges to scaling the interconnects relates to the patterning options. Patterning these tight pitch layers is no longer possible by using single immersion lithography and direct etch steps. Only multi-patterning – which is known to be very costly and complex – is possible either by immersion or by EUV or by a combination of immersion and EUV exposures to form a single metal layer. At IITC, imec showed a full integration flow using multi-patterning, which enables the patterning of tight-pitch metal-cut (the blocks), and effectively scaling the trench critical dimension to 12nm at 16nm half pitch. The researchers also looked at the reliability, for example at electromigration issues caused by the movement of atoms in the interconnect wires. They demonstrated the ability of imec’s Cu metallization scheme at 16nm critical dimension with extendibility to 12nm width, and investigated full ruthenium (Ru) metallization as copper replacement.

Scaling the BEOL beyond the 5nm node

For the technology nodes below the 5nm, the team of imec is investigating a plethora of options and comparing their merits. Options include new materials for conductors and dielectrics, barrier layers, vias, and new ways to deposit them; innovative BEOL architectures for making 2.5D/3D structures; new patterning schemes; co-optimization of system and technology, etc.

For example, to achieve manufacturable processes and at the same time control the RC delay, scaling boosters, such as fully self-aligned vias, are increasingly being used. Via alignment is a critical step in the BEOL process, as it defines the contact area between subsequent interconnect levels. Any misalignment impacts both resistance and reliability. Imec’s team has shown the necessity of using a fully self-aligned via to achieve overlay specifications, and proposed a process flow for 12nm half pitch structures.

Also, self-assembled monolayers (SAMs) open routes to new dielectric and conductor schemes. SAMs composed of sub-1nm organic chains and terminated with desired functional groups can help engineering thin-film dielectric and metal interfaces, and can strongly inhibit interfacial diffusion. The use of SAMs has been a topic of research for the past ten years. Imec has now moved this promising concept from lab to fab, and combined SAMs with a barrier/liner/metallization scheme on a full wafer. The researchers investigated the implica- tions on the performance and scaling ability of this process flow, and demonstrated a ~18% reduction in the RC of 22nm half-pitch dual damascene intercon- nects, due to a better interface and thinner barrier.

For conventional BEOL metallization, a barrier layer is coated by a Cu seed barrier, and this structure is electroplated with low-resistive Cu, which acts as the conductor. But when moving to sub-10nm interconnects, the resistivity of Cu continues to increase. At the same time, the diffusion barrier – which is highly resistive and difficult to scale – is taking up more space, thereby increasing the overall resistance of the barrier/Cu structure. Therefore, alternative metals are being investigated that could possibly serve as a replacement for Cu and do not require a diffusion barrier. Among the potential candidates, such as Co, Ni, Mo, etc., platinum-group metals, especially ruthenium (Ru), have shown great promise due to their low bulk resistivity and resistance to oxidation. They also have a high melting point which can result in better electromigration behavior (FIGURE 2). Imec has realized Ru nanowires with 58nm2 cross section area. The nanowires exhibit low resistivity and robust wafer-level reliability. For example, a very high current carrying capacity with fusing currents as high as 720MA/cm2 was demonstrated.

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At the 2017 IITC conference, this author was invited to take part in a panel discussion, organized by Applied Materials, to discuss the latest developments in metallization at single-digit nodes, the challenges and bottlenecks arising at these very small dimensions, and new application-driven requirements. Distinguished speakers from the technical field reviewed viable solutions for extending the current technology and alternative options were discussed. From the discussion it is clear that the biggest immediate benefit can be found in the area of conductors – both from the material side as well as design. Indeed, it is driving the replacement of copper at specific metallization levels. Other avenues – such as dielectric innovations, functionality in the BEOL or 2D materials – remain interesting options for the R&D pipeline.

As an option that is further out, spin wave propagation in conductors is an alternative signaling to traditional electron based propagation.

Adding additional functionality in the BEOL

In the future, more and more technology options may get dictated by the requirements of systems or even applications. This could result in a separate technology for e.g. high-performance computing, low-power mobile communication, chips for use in medical applications, or dedicated chips for IoT sensors. Along the same lines, imec is investigating the benefits of introducing additional functionality in the BEOL.

More specifically, imec is evaluating the possibility of integrating thin-film organic transistors – with typically low-leakage level – into the BEOL interconnect circuitry of Si FinFETs. The potential advantages of fabricating them together are mainly a reduced power consumption and improved area saving. A variety of circuits can fully utilize the benefits of this hybrid processing, including portable applications, eDRAM, displays and FPGA applications. As a concrete example, imec researchers are currently merging imec’s expertise in BEOL technologies and in thin-film-based flat panel displays, thereby opening opportunities for new applications…

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $107.9 billion for the third quarter of 2017, marking the industry’s highest-ever quarterly sales and an increase of 10.2 percent compared to the previous quarter. Sales for the month of September 2017 were $36.0 billion, an increase of 22.2 percent over the September 2016 total of $29.4 billion and 2.8 percent more than the previous month’s total of $35.0 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

highest ever sales

“Global semiconductor sales increased sharply year-to-year in September, and year-to-date sales through September are more than 20 percent higher than at the same point last year,” said John Neuffer, SIA president and CEO. “The industry posted its highest-ever quarterly sales in Q3, and the global market is poised to reach its highest-ever annual revenue in 2017.”

Regionally, year-to-year and month-to-month sales increased in September across all markets: the Americas (40.7 percent year-to-year/5.9 percent month-to-month), China (19.9 percent/2.5 percent), Europe (19.0 percent/1.8 percent), Asia Pacific/All Other (16.8 percent/1.9 percent), and Japan (11.9 percent/0.5 percent).

“The Americas market continued to stand out, notching its largest year-to-year sales increase in more than seven years,” Neuffer said. “Standouts among semiconductor product categories included memory products like DRAM and NAND flash, both of which posted major year-to-year growth in September, as well as Logic products, which enjoyed double-digit growth year-to-year.”

Silicon has provided enormous benefits to the power electronics industry. But performance of silicon-based power electronics is nearing maximum capacity.

Enter wide bandgap (WBG) semiconductors. Seen as significantly more energy-efficient, they have emerged as leading contenders in developing field-effect transistors (FETs) for next-generation power electronics. Such FET technology would benefit everything from power-grid distribution of renewable-energy sources to car and train engines.

Diamond is largely recognized as the most ideal material in WBG development, owing to its superior physical properties, which allow devices to operate at much higher temperatures, voltages and frequencies, with reduced semiconductor losses.

A main challenge, however, in realizing the full potential of diamond in an important type of FET — namely, metal-oxide-semiconductor field-effect transistors (MOSFETs) — is the ability to increase the hole channel carrier mobility. This mobility, related to the ease with which current flows, is essential for the on-state current of MOSFETs.

Researchers from France, the United Kingdom and Japan incorporate a new approach to solve this problem by using the deep-depletion regime of bulk-boron-doped diamond MOSFETs. The new proof of concept enables the production of simple diamond MOSFET structures from single boron-doped epilayer stacks. This new method, specific to WBG semiconductors, increases the mobility by an order of magnitude. The results are published this week in Applied Physics Letters, from AIP Publishing.

Left: Optical microscope image of the MOSCAPs and diamond deep depletion MOSFETs (D2MOSFETs) of this work. Top right: Scanning electron microscope image of a diamond D2MOSFET under electrical investigation. S: Source, G: Gate, D: Drain. Bottom right: D2MOSFET concept. The on-state of the transistor is ensured thanks to the accumulation or flat band regime. The high mobility channel is the boron-doped diamond epilayer. The off-state is achieved thanks to the deep depletion regime, which is stable only for wide bandgap semiconductors. For a gate voltage larger than a given threshold, the channel is closed because of the deeply and fully depleted layer under the gate. Credit: Institut NÉEL

Left: Optical microscope image of the MOSCAPs and diamond deep depletion MOSFETs (D2MOSFETs) of this work. Top right: Scanning electron microscope image of a diamond D2MOSFET under electrical investigation. S: Source, G: Gate, D: Drain. Bottom right: D2MOSFET concept. The on-state of the transistor is ensured thanks to the accumulation or flat band regime. The high mobility channel is the boron-doped diamond epilayer. The off-state is achieved thanks to the deep depletion regime, which is stable only for wide bandgap semiconductors. For a gate voltage larger than a given threshold, the channel is closed because of the deeply and fully depleted layer under the gate. Credit: Institut NÉEL

In a typical MOSFET structure, an oxide layer and then a metal gate are formed on top of a semiconductor, which in this case is diamond. By applying a voltage to the metal gate, the carrier density, and hence the conductivity, of the diamond region just under the gate, the channel, can be changed dramatically. The ability to use this electric “field-effect” to control the channel conductivity and switch MOSFETS from conducting (on-state) to highly insulating (off-state) drives their use in power control applications. Many of the diamond MOSFETs demonstrated to date rely on a hydrogen-terminated diamond surface to transfer positively charged carriers, known as holes, into the channel. More recently, operation of oxygen terminated diamond MOS structures in an inversion regime, similar to the common mode of operation of silicon MOSFETS, has been demonstrated. The on-state current of a MOSFET is strongly dependent on the channel mobility and in many of these MOSFET designs, the mobility is sensitive to roughness and defect states at the oxide diamond interface where unwanted carrier scattering occurs.

To address this issue, the researchers explored a different mode of operation, the deep-depletion concept. To build their MOSFET, the researchers deposited a layer of aluminum oxide (Al2O3) at 380 degrees Celsius over an oxygen-terminated thick diamond epitaxial layer. They created holes in the diamond layer by incorporating boron atoms into the layer. Boron has one less valence electron than carbon, so including it leaves a missing electron which acts like the addition of a positive charge, or hole. The bulk epilayer functioned as a thick conducting hole channel. The transistor was switched from the on-state to the off-state by application of a voltage which repelled and depleted the holes — the deep depletion region. In silicon-based transistors, this voltage would have also resulted in formation of an inversion layer and the transistor would not have turned off. The authors were able to demonstrate that the unique properties of diamond, and in particular the large band gap, suppressed formation of the inversion layer allowing operation in the deep depletion regime.

“We fabricated a transistor in which the on-state is ensured by the bulk channel conduction through the boron-doped diamond epilayer,” said Julien Pernot, a researcher at the NEEL Institute in France and an author of the paper. “The off-state is ensured by the thick insulating layer induced by the deep-depletion regime. Our proof of concept paves the way in fully exploiting the potential of diamond for MOSFET applications.” The researchers plan to produce these structures through their new startup called DiamFab.

Pernot observed that similar principles of this work could apply to other WBG semiconductors. “Boron is the doping solution for diamond,” Pernot said, “but other dopant impurities would likely be suitable to enable other wide bandgap semiconductors to reach a stable deep-depletion regime.”

The number of IC packages utilizing wafer-level packaging (WLP) will overtake flip chip shipments in 2018 and then continue growing at a compound annual growth rate of 15% (between 2014 and 2020) compared to just 5% for flip chip, according to the report entitled “Flip Chip/WLP Manufacturing and Market Analysis,” recently published by The Information Network, a New Tripoli, PA-based market research company.

“Advanced wafer-level packaging technologies hold the key to meeting future technology needs, from mobile devices to automotive applications, to those required for enabling the IoT,” noted Dr. Robert Castellano, [resident of The Information Network. “Flip chip technology is slowly replacing wire bonding for many high-performance chips, and wafer level packaging (WLP) is replacing flip chip.”

wlp device shipment

To meet the needs of thinner mobile devices, fan-out WLP (FO-WLP) enables redistribution of I/Os beyond the chip footprint, differing from Fan-in WLP in several key areas. One major advantage of FO-WLP, especially in mobile applications, is that the elimination of the substrate reduces the vertical footprint by an average of 40% compared with Fan-in WLP, enabling thinner products or making it possible to stack more components in the same form factor. The elimination of the interposer and TSVs also provides a cost reduction and eliminates concerns on the effects of TSVs on electrical behavior. The reduced path to the heat sink also helps improve thermal performance.

China IC industry outlook


October 17, 2017

SEMI, the global industry association and provider of independent electronics market research, today announced its new China IC Industry Outlook Report, a comprehensive report for the electronics manufacturing supply chain. With an increasing presence in the global semiconductor manufacturing supply chain, the market opportunities in China are expanding dramatically.

China is the largest consumer of semiconductors in the world, but it currently relies mainly on semiconductor imports to drive its growth. Policies and investment funds are now in place to further advance the progress of indigenous suppliers in China throughout the entire semiconductor supply chain. This shift in policy and related initiatives have created widespread interest in the challenges and opportunities in China.

With at least 15 new fab projects underway or announced in China since 2017, spending on semiconductor fab equipment is forecast to surge to more than $12 billion, annually, by 2018. As a result, China is projected to be the top spending region in fab equipment by 2019, and is likely to approach record all-time levels for annual spending for a single region.

Figure 1

Figure 1

This report covers the full spectrum of the China IC industry within the context of the global semiconductor industry. With more than 60 charts, data tables, and industry maps from SEMI sources, the report reveals the history and the latest industry developments in China across vast geographical areas ranging from coastline cities to the less developed though emerging mid-western regions.

The China IC industry ecosystem outlook covers central and local government policies, public and private funding, the industry value chain from design to manufacturing and equipment to materials suppliers. Key players in each industry sector are highlighted and discussed, along with insights into China domestic companies with respect to their international peers, and potential supply implications from local equipment and material suppliers. The report specifically details semiconductor fab investment in China, as well as the supply chain for domestic equipment and material suppliers.

Figure 2

Figure 2

Today, Intel announced the delivery of a 17-qubit superconducting test chip for quantum computing to QuTech, Intel’s quantum research partner in the Netherlands. The new chip was fabricated by Intel and features a unique design to achieve improved yield and performance.

The delivery of this chip demonstrates the fast progress Intel and QuTech are making in researching and developing a working quantum computing system. It also underscores the importance of material science and semiconductor manufacturing in realizing the promise of quantum computing.

Intel’s director of quantum hardware, Jim Clarke, holds the new 17-qubit superconducting test chip. (Credit: Intel Corporation)

Intel’s director of quantum hardware, Jim Clarke, holds the new 17-qubit superconducting test chip. (Credit: Intel Corporation)

Quantum computing, in essence, is the ultimate in parallel computing, with the potential to tackle problems conventional computers can’t handle. For example, quantum computers may simulate nature to advance research in chemistry, materials science and molecular modeling – like helping to create a new catalyst to sequester carbon dioxide, or create a room temperature superconductor or discover new drugs.

However, despite much experimental progress and speculation, there are inherent challenges to building viable, large-scale quantum systems that produce accurate outputs. Making qubits (the building blocks of quantum computing) uniform and stable is one such obstacle.

Qubits are tremendously fragile: Any noise or unintended observation of them can cause data loss. This fragility requires them to operate at about 20 millikelvin – 250 times colder than deep space. This extreme operating environment makes the packaging of qubits key to their performance and function. Intel’s Components Research Group (CR) in Oregon and Assembly Test and Technology Development (ATTD) teams in Arizona are pushing the limits of chip design and packaging technology to address quantum computing’s unique challenges.

About the size of a quarter (in a package about the size of a half-dollar coin), the new 17-qubit test chip’s improved design features include:

  • New architecture allowing improved reliability, thermal performance and reduced radio frequency (RF) interference between qubits.
  • A scalable interconnect scheme that allows for 10 to 100 times more signals into and out of the chip as compared to wirebonded chips.
  • Advanced processes, materials and designs that enable Intel’s packaging to scale for quantum integrated circuits, which are much larger than conventional silicon chips.

“Our quantum research has progressed to the point where our partner QuTech is simulating quantum algorithm workloads, and Intel is fabricating new qubit test chips on a regular basis in our leading-edge manufacturing facilities,” said Dr. Michael Mayberry, corporate vice president and managing director of Intel Labs. “Intel’s expertise in fabrication, control electronics and architecture sets us apart and will serve us well as we venture into new computing paradigms, from neuromorphic to quantum computing.”

Intel’s collaborative relationship with QuTech to accelerate advancements in quantum computing began in 2015. Since that time, the collaboration has achieved many milestones – from demonstrating key circuit blocks for an integrated cryogenic-CMOS control system to developing a spin qubit fabrication flow on Intel’s 300mm process technology and developing this unique packaging solution for superconducting qubits. Through this partnership, the time from design and fabrication to test has been greatly accelerated.

“With this test chip, we’ll focus on connecting, controlling and measuring multiple, entangled qubits towards an error correction scheme and a logical qubit,” said professor Leo DiCarlo of QuTech. “This work will allow us to uncover new insights in quantum computing that will shape the next stage of development.”

Advancing the quantum computing system

Intel and QuTech’s work in quantum computing goes beyond the development and testing of superconducting qubit devices. The collaboration spans the entire quantum system – or “stack” – from qubit devices to the hardware and software architecture required to control these devices as well as quantum applications. All of these elements are essential to advancing quantum computing from research to reality.

Also, unlike others, Intel is investigating multiple qubit types. These include the superconducting qubits incorporated into this newest test chip, and an alternative type called spin qubits in silicon. These spin qubits resemble a single electron transistor similar in many ways to conventional transistors and potentially able to be manufactured with comparable processes.

While quantum computers promise greater efficiency and performance to handle certain problems, they won’t replace the need for conventional computing or other emerging technologies like neuromorphic computing. We’ll need the technical advances that Moore’s law delivers in order to invent and scale these emerging technologies.

Intel is investing not only to invent new ways of computing, but also to advance the foundation of Moore’s Law, which makes this future possible.

Global power semiconductor revenues grew year-over-year by 3.9 percent in 2016, reversing a 4.8 percent decline in 2015, according to a recent report from business information provider IHS Markit (Nasdaq: INFO).

All categories of power semiconductors (power discretes, power modules, and power integrated circuits) were up for the year, with the discretes market seeing the biggest jump. Sales in all regions increased, with China revenues topping the list. IHS Markit expects the market to grow by 7.5 percent in 2017, to $38.3 bill and achieve yearly increases through 2021.

Automotive and industrial lead the way

The automotive and industrial segments were particularly strong in 2016, with power semis in automotive growing by 7.0 percent and industrial by 5.0 percent. Advanced driver assistance systems (ADAS) – such as blind-spot detection, collision avoidance, and adaptive cruise control – are moving from luxury to mid-level vehicles, driving double digit increases for power semiconductors in that category.

Power semiconductors, especially power modules and discretes also saw sharp gains as the number of cars equipped with inverter systems for advanced start/stop and hybrid powertrains increased. In particular, power modules for cars and light trucks jumped 29.3 percent in 2016.

In the broad industrial sector the drive for energy efficiency improvement led to growth in renewable energy (solar and wind inverters), building and home control, and factory automation applications. Revenues from home appliances in the consumer segment also grew nicely as advanced motor control systems found their way into white goods, fans, kitchen, and cleaning products.

Despite good gains, other categories were flat to down. Power module sales for industrial motor drives, a large sub-segment, slid 1.1 percent and modules for traction applications were down 17.5 percent for the year.  Power ICs for consumer application declined 4.9 percent while power discretes for lighting applications were off 2.7 percent.

Growth to continue

“The industry megatrends of vehicle electrification, advanced vehicle safety, energy efficiency and connected everything will continue to drive growth over the next five years,” said Kevin Anderson, senior analyst, power management for IHS Markit. “IHS Markit predicts that the compound-average annual growth rate (CAGR) from 2016 – 2021 will be 4.8 percent.  Regionally, the highest growth is projected in China, at 6.0 percent CAGR, followed closely by the rest of Asia including Taiwan, Europe, Middle East and Africa, and the Americas – all with projected growth over 5 percent.”

BY ARABINDA DAS and JUN LU, TechInsights, Ottawa, ON

Last year was a great year for photovoltaic (PV) technology. According to Renewable Energy World magazine, since April 2016, 21 MW of solar PV mini-grids were announced in emerging markets [1]. The exact numbers of installed solar grids for 2016 has not been published yet but looking at the data for 2015, the PV industry is growing, helped by the $/watt for solar panels continuing to drop. The $/watt is obtained by taking the ratio of total cost of manufacturing and the number of watts generated. According to the Photovoltaic Magazine, the PV market continued to grow worldwide in 2015. The magazine also makes reference to the newly published report by the International Energy Agency Photovoltaic Power System (IEA PVPS) programme’s “Snapshot of Global Photovoltaic Markets 2015,” which also states that the total capacity around the globe has crossed the 200 GW benchmark and is continuing to grow [2]. This milestone of 200 GW in installed systems is a remarkable achievement and makes us think of the amazing journey of PV technology. The technology was born in Bell Labs, around 1954, with a solar cell efficiency of just 4% [3]. By the end of the 20th century, the overall solar cell efficiency was close to 11% and the worldwide installed capacity of PV was only 1 GW [3]. Today, seventeen years later, it has soared to 200 GW, with single junction cells having efficiencies around 20% [2].

Si-based solar cells

To celebrate this important milestone, we put TechInsights’ analysis and technical databases to work to investigate the structure of solar cells of two leading manufacturers and compare them to earlier technologies. We chose to analyze Si-based solar cells only, as they represent over 85% of the global market. According to the 2016 IHS Markit report, the top three PV module suppliers in the world are Trina Solar, SunPower, and First Solar [4]. We procured panels from Trina Solar, a Chinese based company, and SunPower, an American company, and carried out a structural analysis of these panels. These analyses helped us take a snapshot of current PV technology. We compared these two types of panels with an older panel from our database. This panel is about eight years old and was made by Kaneka (Japan). We will provide an overview of each panel and their underlying structure.

Table 1 consolidates some of the important param- eters of the three panels. The SunPower panel is based on monocrystalline silicon and the Trina solar panels are based on polycrystalline silicon. The older Kaneka panel is based on amorphous Si thin film technology. The panel from Kaneka is an earlier product; their recent products are made using hybrid technology, a combination of amorphous films and polycrystalline substrates, The Kaneka panel complements very well the other two products which are based on Si crystalline wafers. The technology to fabricate the solar cells (thin film, multi-crystalline or mono-crystalline) has a direct impact on the efficiency of the cells and on their electrical parameters like the open circuit voltage (Voc) and the short circuit current (Isc), as can be seen in Table 1. This table also shows that the Kaneka thin-film based panel has the lowest nominal power among the three. The ratio of nominal power to the light power that is received by the PV panel is indicative of its efficiency. It can be seen also that Kaneka’s thin film panel has the highest open circuit voltage which is the maximum voltage available from the solar cell without any load connected to it.

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Table 1 indicates that SunPower is the only one among the three that uses an n-type substrate and has the highest solar efficiency. SunPower has the lowest weight per meter-square of all the panels assessed (9.3kg).

Unlike SunPower panels, most installed Si solar panels employ a p-type substrate, even though the first silicon-based solar cells developed at Bell Labs were based on n-type Si substrates [3]. Researchers J. Libal and R. Kopecek posit that the industry transitioned to p-type substrates because the initial usage of solar cells was in space applications and p-type wafers demonstrated less degradation in the presence of cosmic rays. They suggest that for terrestrial applications there is growing evidence that n-type based solar panels are preferred over p-type based panels [5]. The reasons for choosing n-type Si substrates rather than p-type substrates are because the former are less sensitive to metallic impurities and thus are less expensive to fabricate. In general, the minority carrier diffusion lengths in n-type substrates are higher than p-type Si substrates. Also, n-type Si substrates can withstand higher processing temperatures than p-type substrates, which are prone to boron diffusion. According to the International Technology Roadmap for Photovoltaic (ITRPV), n-type based substrates will increase in prevalence and may eventually replace the p-type monocrystalline Si cells [6].

Thin film based solar panels are very different from monocrystalline Si cells. Thin film cells have the lowest efficiency and yet they too have a role to play in the PV industry. They are the most versatile; they can be coated on different substrates such as glass, plastic or even flexible substrates. The other big advantage of amorphous solar films is that they can be manufac- tured in a range of shapes, even non-polygonal shapes, thus they can be used in various applications. Also, thin film solar panels are not affected by high temper- atures, unlike crystalline solar panels. Thin film based panels made from amorphous Si are more effective for wavelengths between 400 nm to 700 nm, which is also the sensitive spectrum of the human eye; thus they can be used as light sensors [7]. Usually, thin film panels are almost half the price of monocrystalline panels. Amorphous silicon solar cells only require 1% of the silicon used in crystalline silicon solar cells [7].

Multi-crystalline (MC) solar panels are also cheaper than monocrystalline solar panels. MC panels are made by melting raw silicon and confining them into square molds, where they are cooled. This MC-Si process does not require the expensive Czochralski process. In the early days, the cost of fabrication of MC-Si panels was higher than thin film based panels. Now, due to the major advances in fabrication technologies, these panels often have the best $/ watt, which represent the ratio of cost to manufacture to energy output [8]. It is difficult to compare $/watt directly from different manufacturers and different types of solar panels as the technology is manufacturing is changing rapidly and often the most recent products of a manufacturer are not compared. A more sensible factor of comparison would be the ratio of total kilowatt-hours the system generates in its lifetime divided by the cost per square unit of the panel. To make a detailed estimation even the installation cost and tolerance to shade, overall reliability must be included in the calculations, which is beyond the scope of this article.

Solar panel overview

FIGURE 1 shows the panel from Kaneka. It indicates that the Kaneka solar panel cells are long strips that run across the whole length of the panel. The color of the panels is a shade of purple. The Kaneka Solar which is amorphous Si-based, has a very uniform color. The inherent structure of amorphous Si-films has many structural defects because they are not crystalline and thus are tolerant to other defects like impurities during manufacturing, unlike crystalline based panels [7]. The color of the thin film panels is strongly thickness dependent because thickness affects the light absorption. A solar cell’s outward appearance can range from blue to black and is dependent on the absorption and reflectivity of their surface. Ideally, if the cell absorbs all the light impinging on the surface it should be black. FIGURE 2 shows the panels from Trina solar and Sunpower. The Trina Solar panel has a blueish color and each cell is perfectly square. The SunPower SPR-X20- 250-BLK solar cell has a uniform blackish color. The spacing between the cells, the interconnect resis- tance, the top contacts and the materials used for the connections affect the overall performance of the panel. All three manufacturers connect their cells within a PV module and PV modules within an array in a series configuration.

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Table 2 summarizes the cell dimensions for the three manufacturers. Kaneka panels have the narrowest space (0.55mm) between the cells. The Trina solar panel has a 3 mm wide gap and a 5 mm gap, between two adjacent solar cells, in the horizontal and vertical direction respectively. These gaps are used for bus electrodes. In the SunPower solar panel, the metal grid is placed on the back surface eliminating metal finger width as a layout constraint. This design significantly reduces the finger resistance and improves the series resistance.

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For all panels, interconnects are made between the cells. The metallization and interconnects between the cells is a field of technology on its own. There are various techniques like lithography, laser grooving and printed contacts and these details are discussed more in detail elsewhere [9, 10, 11].

Solar panel cross-sections

In this section, we look into the layers deposited on the substrates. Cross-sectioning these big panels is not a trivial feat. These panels are covered with tempered glass and shatter during sawing and cross-sectioning. To extract a small rectangular piece requires patience and involves sawing and grinding processes. In most cases, the glass was removed before doing the cross-section. FIGURE 3 illustrates two SEM cross-sectional images and one schematic drawing. The SEM cross-sectional images show the top and bottom part of the Kaneka solar cell. In figure 3(a), the active layers comprise indium- tin- oxide, an amorphous silicon layer capped with zinc oxide, silver and a very thin layer of Ni-Al. On top of the Ni-Al film, solder is deposited. Ni-Al provides better adhesion to solder. Two electrical contacts are made between the cells, one to the indium-tin-oxide for the back contact and the other to the Ni-Al layer. Figure 3(b) exposes the layers under the glass substrate. The rear surface of the glass substrate is covered by a soft material such as EVA (ethyl-vinyl-acetate), which in turn is covered by a rear Polyvinyl Fluoride (PVF) layer called the backsheet (Tedlar or similar). EVA is also used on the top surface (figure 3(a)). The usage of these layers is standard practice in the PV industry. The main function of these layers is that they are impervious to moisture and are stable under prolonged exposure to sunlight. On the front side, EVA also helps to reduce reflection and provides good adhesion between the top glass and the solar panels. Figure 3(c) shows the complete stack in the Kaneka solar cell.

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FIGURE 4 presents the stack of materials on the multi- crystalline substrate of the Trina Solar panel. The substrate is p-type and has a very thin phosphorous doped region near the top surface. This n-doped region forms the PN junction. A silicon nitride anti-reflective coating layer is deposited on top of the substrate and in designated areas the passivation is opened and silver is deposited to make electrical contact to the n-doped regions. At the bottom of the multi-crystalline substrate, there is also a thin region of high p-doping concentration and this forms the back surface field layer. This solar cell module is fabricated using passivated emitter and full metal back-surface-field (BSF) technology. BSF technology is implemented to mitigate rear surface recombination and this is done by doping heavily at the rear surface of the substrate. This high doping concentration keeps minority carriers (electrons) away from the rear contact because the interface between the high and low doped areas of same conductivity acts like a diode and restricts the flow of the minority carriers to the rear surface. Passivated emitters in the front side and BSF layer on the rear side improve the efficiency of the cells. Figure 3(b) is the schematic repre- sentation of the cell without the EVA and PVF layers.

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FIGURE 5 shows an optical cross-section of the SunPower cell. Figure 5(a) shows that SunPower employs a backside junction technology with interdigitated backside p-emitter and n-base metal. This means that both the contact’s n and p-electrodes are at the bottom of the substrate and are placed in in an alternating manner. Having all the metal contacts on the rear side has two big advantages:

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1. Metallic contacts are reflective and occupy space that can be used to collect more sunlight; transferring these contacts to the rear side improves the cell efficiency and also leaves the front surface with a uniformly black color, which is more aesthetic for the home users.

2. It reduces bulk recombination. The mono-crystalline substrate is only 120 μm thick. It is designed so that the carrier is generated close to the junction. The substrate is n-type and p-electrodes are formed by localized doping on the bottom part of the substrate.

Figure 5(b) illustrates the general structure of the cell.

FIGURE 6 depicts a SEM cross-section of the metal fingers that connect to the interdigitated electrodes. The pitch between the metal fingers is 920 um and repeats over the entire back surface of the panel.

All three manufacturers employ some sort of surface texturing along with anti-reflective coatings to reduce reflection but SunPower uses the most advanced technology for surface texturing. FIGURE 7 illustrates a SEM topographical image of the front surface texture of the monocrystalline substrate having pyramids, which are etched into the silicon surface. These faceted surfaces increase the probability of reflected light entering back to the surface of the substrate. A similar concept is also applied to the back surface.

Screen Shot 2017-09-26 at 1.07.11 PM Screen Shot 2017-09-26 at 1.07.20 PM

The future is sunny and bright

Of the three panels we analyzed, SunPower solar panels employ the most advanced technologies and they illustrate how the solar cell has evolved over the ages. It started from a simple PN junction, then passivated emitters were intro- duced along with local back-surface-field (BSF) technology, which came to be known as Passivated-Emitter with Rear Locally (PERL) diffused technology. In contrast, today the most advanced technology is interdigitated back contacts along with passivated contacts.

In addition to these advances, there is great progress in tandem cells and multi-junctions to capture the different wavelength regions of the sun’s rays. A recent article in IEEE spectrum magazine presented the state of art of record-breaking PV cells made with different techniques such as thin film, crystalline Si, single junction, multi-junction cells. PV cells especially the multi-junction cells, have now crossed the 50% efficiency barrier [12]. Similarly, a publication from the alterenergy.org has collected all the major advances made in PV technology and discusses concepts like colloidal quantum dots and GaAs for cell technology, along with new applications [13]. Today, we regularly read about new materials (like perovskites) and come across new techniques that improve solar panel efficiencies, including new manufacturing methods to reduce the overall cost of fabrication. Moreover, PV cells are used in an innovative manner. The installation of PV panels is no more restricted to isolated rooftops or solar farm. An article in the Guardian made a reference to a solar panel road in Normandy, France [14]. At TechInsights, we will continue to keep an eye on emerging solar cell technologies.

The efforts emerging from various organizations all over the world are very encouraging. There are indeed many challenges for renewable energy to overcome before fiscal parity with fossil fuels is achieved; particularly for PV energy. Nevertheless, there is an increased focus on climate change issues. This has resulted in a significant amount of resources being allotted to PV technology in many countries, especially in developing countries such as China, India, and Brazil [1, 2]. This optimistic scenario reminds us of the song “I Can See Clearly Now” by the 1970s American singer Johnny Nash, where the refrain runs optimistically, “It’s gonna be a bright, bright sun-shiny day.”

References

1. http://www.renewableenergyworld.com/articles/2017/01/21-mw- of-solar-pv-for-emerging-market-community-mini-grids-announced- since-april.html;
2. http://www.pv-magazine.com/news/details/beitrag/iea-pvps— installed-pv-capacity-at-227-gw-worldwide_100024068/#ixzz4MB1 a44hq
3. The history of solar: https://www1.eere.energy.gov/solar/pdfs/solar_ timeline.pdf
4. http://news.ihsmarkit.com/press-release/technology/ihs-markit- names-trina-solar-sunpower-first-solar-hanwha-q-cells-and-jinko-
5. www.pv-tech.org/guest…/n_type_silicon_solar_cell_technology_ ready_for_take_off
6. http://www.itrpv.net/; http://www.itrpv.net/Reports/Downloads/2016/ 7. http://www.solar-facts-and-advice.com/amorphous-silicon.html
8. http://energyinformative.org/solar-cell-comparison-chart-mono-
polycrystalline-thin-film/
9. RP_0706-14839-O-4CS-11Kaneka
10. RP_0616-41931-O-5SA-100_Trina
11. RP_0716-42662-O-5SA-100_SunPower
12. http://spectrum.ieee.org/green-tech/solar/what-makes-a-good-pv-
technology
13. http://www.altenergy.org/renewables/solar/latest-solar-technology.
html
14. https://www.theguardian.com/environment/2016/dec/22/solar-panel-
road-tourouvre-au-perche-normandy

DSA and EUV should be envisioned as complementary, not competing, techniques that will eventually become mainstream for fine-pitch lithography.

BY DOUGLAS J. GUERRERO, Ph.D., Brewer Science, Rolla, MO

Advances in lithography have always been critical in the drive toward each subsequent semiconductor node. Anticipating limitations in the scaling ability of immersion lithography, the industry has been pursuing next-generation lithography techniques. Several techniques have been proposed, including extreme ultraviolet (EUV) lithography, multibeam electron-beam lithography, nanoimprint lithography and directed self-assembly (DSA) of block copolymers.

DSA attracted a great deal of interest from major semiconductor manufacturers for several years, following its initial development in the early 2000s. However, it has since fallen out of favor to some extent, in part because of advances in EUV lithography as a result of focused investment in that technology. Recent developments in DSA materials and processing promise to overcome concerns that have delayed its implementation.

Choosing an appropriate lithography technique does not need to be an either-or proposition. The greatest opportunity may lie in leveraging both EUV lithography and DSA. Although these two technologies are sometimes seen as competing, it makes more sense to envision them as complementary. This article explains how lithography may benefit by taking advantage of both EUV and DSA, and why previously existing roadblocks may no longer pose obstacles.

The material defines the pattern

Unlike most lithography techniques, where the mask defines the pattern, in DSA the pattern exists in the material itself. The original block copolymers (BCPs) for DSA combine polystyrene (PS) and poly(methyl methacrylate) (PMMA), two polymers that naturally segregate themselves into separate phases. Adjusting the relative proportions of PS and PMMA in the PS-b-PMMA material changes the morphology from spherical to cylindrical to lamellar (FIGURE 1). The product of the Flory interaction parameter, χ, and the segment length determine the spacing of the ordered structure. The higher the value of χ, the finer the pitch of the resulting structure.

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Standard PS-b-PMMA materials have relatively low χ, which limits the pitch to 20nm or larger. Some materials manufacturers are considering chemistries other than PS-b-PMMA to produce high-χ BCPs, replacing the PMMA component with polydimethylsiloxane or polyhydroxystyrene. Modifying PS-b-PMMA is another approach to increase χ. In this manner, it is possible to tune χ, the molecular weight and the glass transition temperature to achieve lamellar spacing between 14nm and 40nm under various annealing conditions.

The process flow for BCP deposition is straightforward. A neutral layer spin-coated onto the substrate allows for the BCP to separate into its individual domains during the thermal annealing process. The neutral layer allows for domain separation because it does not have affinity for either of the polymer chains in the BCP. Polymer domain separation is responsible for pattern formation.

Processing considerations

The DSA deposition process uses one of two basic approaches (FIGURES 2 and 3). Graphoepitaxy leverages topography to align the BCPs, depositing them into relatively deep trenches. Guide patterns define the trenches, confining the BCPs into configurations in which they align in a preferred direction. Chemical epitaxy, or chemoepitaxy, is based on a chemical pattern on a flat substrate, on top of which the BCPs self-align.

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Click to enlarge.

The semiconductor industry is pursuing both graphoepitaxy and chemoepitaxy approaches, favoring the former for producing fine-pitch vias and the latter for creating arrays of parallel lines.

Annealing temperatures are in the range of 250°C to 275°C, making them compatible with standard semiconductor processing. The annealing step can be lengthy—up to two hours to create structures with sufficiently low defect rates—adding cost to the process.

PS-b-PMMA BCPs are being manufactured in high- volume quantities. Worldwide, 1.1 million tons of the material are currently in use for a variety of applica- tions. This quantity is greater than the needs of the entire semiconductor industry. Therefore, although no commercially produced DSA materials are currently targeted for semiconductor applications, the infra- structure is in place to scale up production of suitable materials when the industry is ready.

Why DSA is attractive now

DSA was added to the ITRS roadmap in 2007. Major semiconductor industry players originally believed DSA would enter commercial production anywhere between the 14nm and 7nm logic nodes, and even sooner for DRAM; but so far that has not come to pass. A survey at the 2016 DSA Symposium suggested that the technology is still not ready for the mainstream and won’t be for several years. But some IDMs would like to accelerate the process, and there are reasons to believe this is not only possible, but desirable.

Decreasing the wavelength to 193nm immersion lithography has enabled line width and spacing down to 80nm. Techniques such as self-aligned quadruple patterning (SAQP) can create even smaller features through multiple lithography/etch iterations, but at the expense of adding lithography steps, each requiring a custom mask.

Immersion lithography is reaching its limits, providing an opportunity for next-generation lithographic techniques. Designs with critical dimensions (CD) in the range of 10nm to 30nm create a sweet spot for these state-of-the-art techniques.

Advances in EUV lithography are one factor that has led the industry to favor it over DSA. Today’s EUV materials have greater sensitivity compared with older- generation products, therefore requiring lower UV doses; and line roughness has improved as well. EUV lithography can create vias with 30nm or 40nm spacing that are not feasible with immersion lithography.

DSA enables even finer resolution than the semicon- ductor industry currently demands. Feature sizes are just now approaching a level where DSA can be especially effective. If these trends continue, the technique is poised to be widely adopted before the end of this decade.

DSA and EUV: Better together?

The most effective solution may lie in leveraging EUV and DSA technologies to take advantage of the strengths of each. Both methods can achieve resolution levels that are compatible with the N7 and N5 logic nodes. EUV lithography is well-suited to patterning designs with multiple different pitches, down to line width and spacing around 30nm. For such fine pitches, however, the number of mask steps required may make the technique prohibitively expensive. Local CD uniformity (LCDU) can also be a concern, especially at high throughput rates.

The initial hard-mask lithography process is the same for both EUV and DSA, but they diverge during pattern processing. Once the BCPs are deposited, DSA can achieve 30nm feature size without requiring additional masks. Annealing naturally separates the two phases into the correct morphology. The DSA process, however, is best suited to designs with a single pitch.

EUV can be used to pattern lower-resolution features on a chip, plus create spacers for subsequent DSA deposition. This combination provides the greatest design flexibility while streamlining the fabrication process, eliminating processing steps and reducing mask costs. LCDU is also better than with EUV alone.

DSA is best suited for devices with multiple repeating, regular fine-pitch features. Therefore, it likely will first be implemented in DRAM storage, later migrating to use in via layers on logic devices. Graphoepitaxy, especially using EUV to deposit the spacers, can enable more complex designs using DSA, where different regions of the chip require different pitches. This will presumably be the approach of choice for logic chips.

Despite the promise that leveraging both DSA and EUV offers, the semiconductor industry will only migrate to this approach once suppliers can convince IDMs that the materials have overcome their technical limita- tions. DSA has suffered from several challenges that have delayed its adoption: Primary issues are defectivity, pattern placement accuracy, ease of integration into manufacturing flows, and cost. But there is reason to be optimistic, as advances in chemistry and processing methods are improving all these metrics.

Overcoming technical challenges

The 2016 DSA Symposium survey identified defec- tivity as the greatest technical challenge. Defectivity and cost are related, in that the lowest defect levels are seen with the longest annealing times. While annealing for as little as five minutes causes the two phases to separate, the resulting material contains far too many defects to be suitable for commercial use.

Wafers are typically annealed one at a time, which can make the cost of annealing prohibitive. However, recent research using batch annealing in a vertical furnace showed great promise for reducing cost. By annealing 150 wafers in parallel for 30 minutes, researchers were able to demonstrate sufficiently low defect levels at a cost lower than that of SAQP.

Using both DSA and EUV has the potential to alleviate the problem of pattern placement errors. For example, EUV lithography can create prepatterned holes for doublet vias. The two vias may merge during the EUV process but will then automatically separate during DSA. Without DSA, an additional lithography step may be required to avoid merged vias.

This approach of leveraging EUV and DSA for fine- pitch vias is most reliable when the via shape is optimized. Studies have shown that a peanut shape, rather than an elliptical one, is ideal for creating doublet vias with minimal risk for pattern placement errors, even at the challenging N5 node.

Collaborating to advance DSA adoption

The semiconductor industry has extensive experience with lithography, but DSA requires a shift in mindset. BCP materials are not something that the industry is used to, and revolutionary rather than evolutionary changes in materials and processes can face resistance. DSA needs to be demonstrated on real devices before it can achieve traction in the semiconductor market.

Collaborative efforts between semiconductor industry materials suppliers and chemical companies with deep experience in BCPs are one route to bridge this gap. One such collaboration is currently underway. Brewer Science has teamed up with Arkema, a company with two decades of experience producing BCPs, but little leverage with the semiconductor industry. The partnership, begun in 2015, has led to pilot production of DSA materials, paving the way for the technique to move out of the laboratory and into commercial semiconductor products.

DSA and EUV should be envisioned as complementary, not competing, techniques that will eventually become mainstream for fine-pitch lithography at the N7 node and beyond. Partnerships between materials and chemical companies are poised to enable this transition, unlike previous efforts by single organizations.

IC Insights has just released its September Update to The McClean Report.  This 32-page Update includes a detailed look at the pure-play foundry market and an analysis of the historical DRAM price-per-bit trends.  Shown below is an excerpt from the Update that examines the IC technology trends in the pure-play foundry market.

In 2017, the 7% increase in the total pure-play foundry market is forecast to be almost entirely due to an 18% jump in <40nm feature size device sales (Figure 1).

Figure 1

Figure 1

Although expected to represent 60% of total pure-play foundry sales in 2017, the ≥40nm pure-play IC foundry market is forecast to be up only $0.2 billion this year.  In contrast, the 2017 leading-edge <40nm pure-play foundry market is expected to surge by a hefty $3.3 billion.  Moreover, not only is almost all of the pure-play foundry growth forecast to come from leading-edge production in 2017, most of the profits that are expected to be realized in the foundry market also forecast to come from the finer feature sizes as well.

TSMC is by far the technology leader among the major pure-play foundries.  In 2017, 58% of TSMC’s revenue is expected to come from <40nm processing, more than double percentage at GlobalFoundries and more than triple the share at UMC.  In total, TSMC is forecast to hold an 86% share of the total <40nm pure-play foundry market this year.

Illustrating how dominant TSMC is in the leading-edge pure-play foundry market, the company is expected to have almost 7x the dollar volume sales at <40nm as compared to GlobalFoundries, UMC, and SMIC combined this year ($18.5 billion for TSMC and $2.7 billion for combined total of GlobalFoundries, UMC, and SMIC).  In fact, 10% of TSMC’s total sales this year are forecast to be for its 10nm process technology.

In contrast to TSMC, SMIC only entered initial production of its 28nm technology in 4Q15, more than three years after TSMC first put its 28nm process into production.  In fact, only 7% of SMIC’s 2017 sales are expected to be from devices having 28nm feature sizes (the company does not offer a finer feature size at this time), which is the primary reason its revenue per wafer is so much less compared to TSMC.