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A main focus of this year’s Electronic Components and Technology Conference (ECTC), held this week in San Diego, is 3D integration and through silicon vias (TSVs).  “The biggest trend for the last couple of years has been 3D and TSV and it continues to be that way,” said David McCann of GLOBALFOUNDRIES and ECTC conference chair.  This year, the conference features a set of sessions specifically on 3D TSVs, with minimal overlap.  There’s also an additional session specifically on interposers, otherwise known as 2.5D. “The industry really wants to see 2.5D happen as an easier way to do 3D before all the 3D tools are in place,” McCann said. “The struggle is over how much is an interposer going to cost.”

Presently, that struggle appears to be between glass and silicon, where glass is a less expensive alternative. “Glass would be a cheaper approach to silicon interposers, but is limited to line space and via diameter,” McCann said. “Glass is not able to get as dense as silicon.” He said there may be a bifurcated market on interposers, where the high end is on silicon, and the low end is on glass. High end applications are devices such as microprocessors, which need high density, 1 micron lines and spaces. Low end devices are capabilities such as RF.  

In terms of when TSVs will move into volume production for mainstream applications, McCann said that RF devices that already have TSVs because they have backside contact. Next, memory devices are in line to for TSV production. “I think there will be more and more memory stacks,” he said. Fabricating a memory stack internally for a memory company is easy (at least compared to alternative approaches) in that it doesn’t require an outside standard to be able to do the connection between the devices. “Next will be wide I/O or whatever wide I/O morphs into, maybe wide I/O2, where you get an apps processor with a wide I/O DRAM on top of it,” McCann said. “I think we’ll see those starting in 2013, first products in the industry and 2014 for adoption into 20nm. And then, following that, it’s very dependent upon standards. Wide I/O standard is critical for getting multiple memory suppliers to supply memory or a consuming company to use multiple suppliers,” he said.  “Standards are going to enable products and those first 3D products are going to use devices that already exist and put TSVs into them.”

The real potential of 3D integration will come around 2017 or 2018, McCann believe, when heterogeneous stacks with different devices with different functions, such as memory, digital, analog , RF and power, are integrated in a stack. “There will be design tools that optimize the design of those devices for placement of blocks, TSVs and bumps  for optimal performance. In the first products, we won’t have so much optimization, but more enablement, and then where we all really want to get to is that optimization of performance, “ McCann said. “What that will look like is say a bit of memory just above a processing cell, right where you want it. Or the analog the right where you want it to be placed with this very short vertical interconnect to the circuitry that it needs to communicate with. We’ll get to optimal block placement when the tools start getting available to help us co-design devices from different manufacturers for optimal performance.”  

McCann acknowledged that testing these complex 3D stacks will be a major challenge, saying is revolves very much around IP. “If you think about DRAM and how it’s tested, it’s all internal to the DRAM company and it’s very tightly protected IP. Nobody wants to let that outside, understandably. Then you start thinking about 2.5D and 3D where you’ve got integrated memory – how do you do that? The assembly of those is not going to be at the memory manufacturer,” he said.

McCann believe stacked memory will evolve in two stages. The first stage will be it will be shipped as a completed component so that the memory company can continue to adhere to the business model of shipping a completed, tested, repaired device — a know good die.” That small stack will be placed on an apps processor for 3D, or on an interposer for 2.5D,” he said. The second part of it is what IP is needed for both the microprocessor and the memory to enable test. “We’ll start seeing test IP blocks from the foundries and the memory companies to enable test by using the processor to test the memory . I think we’re still exploring what that looks like. I can’t tell you what that’s going to end up looking like, but it’s clear that we’ve got to enable that together to enable the products,” McCann said.  

Dr. Vivek Bakshi blogs about trends he expect to see at the upcoming 2012 International Workshop on EUV Lithography, in Maui Hawaii. 

Currently, EUV source suppliers are working on increasing source power for EUVL scanners. The ASML 3300 Series scanners, designed for high-volume manufacturing, are scheduled for delivery later this year. Most probably, high power sources will not be quite ready in 2012 to support HVM requirements, and will need to be upgraded on site.  So the questions still needing to be answered are:

  • When will these HVM-level EUVL scanners be used to make products?
  •  What will trigger the industry-wide insertion of EUV scanners in HVM production lines?
  • Will it be a certain source power level, throughput, yield, or cost that raises the confidence of users?
  •  Who will be the first users of EUVL in HVM, and for what products and which node?

Similar questions can be posed for EUVL mask defect metrology tools. With scanners, we have an approximate throughput model that is widely known, so we can estimate throughput and cost of ownership at a given source power level. This is not quite so for mask defection inspection tools, as they are still being designed and need brighter EUV sources.  The leading option for sources for defect metrology tools (and the only one for a 24 x 7 operation) is the Energetiq Xe discharge-produced plasma (DPP) source. However, current performance levels for this source allow only development of prototypes. 

In my opinion, memory makers probably will be the first adopters of EUVL technology. Throughput as high as 40 wafers per hour (WPH) will convince chip-makers that EUVL is a viable technology, and sales of EUVL scanners and associated tools and products will start soaring. Mask defect metrology tools will remain unready for HVM until a brighter source becomes available. We can expect a déjà vu: low throughout metrology tools waiting to be upgraded.

In the case of high-power sources, we have three major suppliers with the commitment and resources to continue development. Not so for metrology sources, and the end customers will have only themselves to blame this time. I have read that end users are spending up to $150 million on metrology tool development, but not a dime on developing EUV sources for metrology. A source supplier told me that promises of support for metrology source development have not materialized,  even though EUV sources for metrology are the weakest link in the chain. With virtually all of the money going to engineering development of tools and none to this weakest link, the results are very predictable.

As the industry Roadmap moves to smaller nodes of resolution (10 nm and below), will we choose EUVL with double patterning, or change the wavelength once again and move toward Beyond EUV (BEUV)? Gadolinium (Gd) at 6.8 nm is the current leading option for BEUV source material, as we saw from the latest development results on source and optics in last year’s EUVL Source Workshop. Increased optical proximity correction (OPC), off-axis illumination (OAI), and double patterning may require more power at these nodes than 13.5 nm sources can provide, so it might make sense to move to BEUV. For BEUV, we have a leading source material for multilayer (ML) optics and resist development has already started.  We also can apply lessons learned from 13.5 nm to BEUV tools, although more infrastructure work will be required.

These and related topics will debated by panelists from Intel, GlobalFoundries, Toshiba and Applied Materials (AMAT) at the 2012 EUVL Workshop being held June 4-8 in Maui, Hawaii. The panel will be moderated by Sushil Padiyar of AMAT. The Workshop also will feature many papers on BEUV and EUVL R&D from some of the world’s leading researchers. I will be blogging here about these new developments after the EUVL Workshop.

MEMS isn’t NEW


May 30, 2012

Karen Lightman, MEMS Industry Group (MIG), lets us in on the real meaning of MEMS new product development. MEMS are micro electro mechanical systems.

May 30, 2012 — What do you think of when I say the words “MEMS new product development?” Do you envision new categories of newly discovered MEMS hatching somewhere in a university lab? If your answer is “yes,” perhaps you should rethink that — because MEMS isn’t new.  If we are to grow this $9 billion/year industry to a hundred-billion or even trillion dollar industry as some predict, we need to think of new MEMS in terms of how the “regular, everyday” MEMS we have right now are used in development of new end products.  Whether these new MEMS-enabled products come from a combination of market pull and/or technology push, there are challenges and hurdles that the industry must come together to address, now!

That is why we focused the MEMS Industry Group (MIG) Member-to-Member (M2M) Forum® on MEMS “New Product Development” earlier in May — because it is so time-critical for the MEMS industry to come together and address these barriers and challenges to commercialization that are hindering growth. Barriers that I like to call the “stickiness of MEMS,” which include the “S” word of MEMS — “Standards” for things such as testing, packaging…not the sexy, shiny, bright things that are hatched in the lab and then probably never make it to the market.

I invited Len Sheynblat of Qualcomm CDMA Technologies (QCT) to give the keynote, “Sensor Systems Integration Challenges,” which spelled out in very specific terms what the MEMS industry needs to do, specifically, Sensor API Standardization. He shared QCT’s commonly requested sensor vendors: 18+! With 26+ sensor product lines! And on top of this, there are numerous handset and tablet OEMS with different ecosystems: Android, Windows, RIM (which used to be Palm), etc.  They all want to be loved, and this makes developing with MEMS just a smidge complex.

Sounds a bit nightmarish, don’t you think? I sure do, and MIG will be working with our members and strategic partners, including the MIPI Alliance, to address these challenges and issues of the stickiness of MEMS. I urge you to contact me and become active and involved in our M2M Action Item Task Forces.

That’s also why the MIG Technology Advisory Committee (MIG TAC) chose Mary Ann Maher, CEO of SoftMEMS, as the winner of our first-ever white paper competition, because she discussed the important issue of co-design and yes, standards. And because Mary Ann was the evening speaker, she also made the presentation into a drinking game. (Every time she said “co-design,” you were to take a sip; I gave up after the 15th time.)

And as we have every year, since MIG began with DARPA funding, we also had working groups to dive deeper into the conference topic. Our working group leaders (Jim Knutti of Acuity, Mike Mignardi of TI, Jason Tauscher of MicroVision and Valerie Marty of HP) did a fantastic job of moderating the rich discussions we had in the working group breakout groups on “Market Pull vs. Technology Push” and “MEMS Technology Development.” I encourage you to check out the MIG resource library to see the body of knowledge and case studies we’ve gathered; and MIG action item task forces will be forming soon to carry out several of the recommendations.

M2M Forum also featured a panel of speakers expressing diverse opinions and perspectives on new product commercialization — from those involved heavily and not so heavily with MEMS. The panel included: Anne Schneiderman of Harris Beach, an expert in IP law; Stefan Finkbeiner, a MEMS device manufacturing veteran with Bosch/Akustica; Matt Apanius with SMART Commercialization Center for Microsystems, who is well versed in tech transfer from lab to fab; and Ivo Stivoric with BodyMedia, someone who embodies a MEMS supplier’s dream of an end-user company.

My favorite part of the panel was when Ivo described the challenges in understanding/analyzing the “white space in the market.” He warned that as a consumer of MEMS, he oftentimes doesn’t need a new device; he just needs a tweak or two and then wants the device manufacturer to “just go away” so he can go back to his customers. Amen, brother. I want that for you, too. Because the truth is that MEMS isn’t new, and so we need to find the solutions to these challenges to commercialization, and then move on to conquer the other white space in the market.

Contact Karen Lightman, managing director of MEMS Industry Group at [email protected], 412-390-1644. Read her other blogs:

May 29, 2012 — KLA-Tencor Corporation (NASDAQ:KLAC), maker of semiconductor manufacturing metrology tools, measures a 70% increase in fab process steps from 90nm to 32nm semiconductor nodes. This doubles the critical inspection steps required, report Citi analysts from a non-deal roadshow with KLAC’s CFO and EVP Mark Dentinger.

Node changes are not accelerating, but continue to present technology challenges that should enable both inspection and metrology to outgrow the overall equipment market. Importantly, KLAC noted that the 28nm node’s process control spending cycle is still in the early to middle inning and nowhere near its ending phases.

New device architectures — like 3D gates — and processing technologies — like double/triple patterning and extreme ultraviolet (EUV) lithography — will accelerate the demand further. Some will change metrology tool requirements — EUVL will shift fab demands from optical inspection to reticle inspection, overlay metrology demand will grow with adoption of double patterning. KLAC noted that electron-beam inspection, which it refers to as an R&D rather than process line tool, will see flat growth in the near future.

In addition to new nodes, the move to 450mm wafers will push fabs to add metrology/inspection tools. KLAC is supplying its first bare wafer inspection system for 450mm this quarter to an OEM. KLAC believes Intel will develop 450mm pilot lines in 2016 with volume production starting sometime in 2018. The pace at which INTC executes this transition will determine the pace at which other manufacturers (foundries) embark on the transition.

Inspection/metrology spending will be 16-20% of foundry/logic capital expenditures, and 8-12% of memory’s, with combined 15% share of wafer fab equipment spending, Dentinger said. This could go higher on foundry strength. In total, for all tools, KLAC foresees 2012 spending flat to down 5%.

KLA-Tencor Corporation provides process control and yield management products, including state-of-the-art inspection and metrology technologies for the semiconductor, data storage, LED, photovoltaic, and other related nanoelectronics industries. Additional information may be found at www.kla-tencor.com (KLAC-P).

Visit the Semiconductors Channel of Solid State Technology!

“The Dangerous Disappearing Defect” is the first article in a new series called Process Watch. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions for chip manufacturing at the leading edge.

Finding and classifying defects on a wafer is a statistics game. The defect pareto—the bar graph showing the number of defects by type caught by the defect inspector and identified by the e-beam review system—drives the actions of the defect engineers in the fab. However, it’s not necessarily the tallest bar in the graph that tells the experienced defect engineer how to fix a defect problem. Far too often, the tallest bar is the insidious “SNV”—SEM Non-Visual. Some fabs bluntly label this category “Not Found.”

It might be more accurate to call the category “Not Found Again.” The defect inspection system did indeed find these defects and reported them in the KLARF, the output file that lists the locations of the defects detected on the wafer along with some descriptive information such as the size of the scattering signal associated with them. The “Not Found” problem arose when the wafer was moved to the e-beam review system to identify defect type. As the e-beam review system drove to the sites of the defects found by the inspection tool, sometimes it didn’t see a defect. This situation can arise for any of several reasons. First, the inspection system could have experienced a glitch, a result of electrostatic discharge or system noise, and therefore reported a false event. Second, misalignment between the coordinate system of the inspector and that of the e-beam review system could have resulted in the defect lying outside the field of view (FOV) of the e-beam review system. Third, the inspection system could have detected a defect at a previous layer that’s covered by a film transparent to the (optical) inspection system but not to the e-beam review system. Fourth, the defect could have arisen from nuisance variation, such as line-edge roughness, that shows up as a defect when the inspector uses a die-to-die detection algorithm, but is not evident in a review image, which is viewed alone. In any of these cases, the defect will be classified as “Not Found” or “SNV.”

SNV Type One: False events. As defined above, false events are a rare occurrence for today’s wafer inspection systems. Advances in signal processing algorithms, mechanical and electrical subsystems, and system integration have virtually eliminated false events. (False events are not to be confused with nuisance defects, which are defects arising from real, physical phenomena on the wafer—that defect engineers have designated as not affecting yield, performance or reliability. Examples of nuisance defects besides line-edge roughness might include particles that reside in open areas and bridges within dummy pattern. Nuisance defects can be culled from defects-of-interest (DOI) through multiple means, including choice of wavelength, aperture and polarization in the inspection recipe, and by various defect classification schemes post-detection. Nuisance defects like particles on open areas might be successfully re-detected by the e-beam review system, then binned or classified as nuisance, or they might be SNV, like line-edge roughness.)

SNV Type Two: Field-of-View Errors. For previous-generation inspection and review tools, insufficient coordinate accuracy often meant that the e-beam review tool had to search for each defect using a large field of view, then “zoom in” to image the defect with sufficient resolution to allow its classification. This strategy had two drawbacks: 1) it was very time-consuming, and thus limited the number of defects that could be reviewed on a wafer so that a statistically representative defect population was nearly impossible to attain; and 2) with a large FOV, the resolution of the image was too low to find the smallest critical defects. It didn’t matter that the ultimate resolution of the review tool was a couple of nanometers; if that resolution had to be compromised while the system was searching for defects, a significant number of defects would be missed. Defect engineers began to realize that, while resolution of the e-beam system is necessary for defect classification, the tool’s ultimate resolution is useful only if the defects of interest can be located reliably. 

Recent advances in stage accuracy on the wafer inspection and review tools, and improved communication between the tools, have now made it possible for e-beam review tools to drive directly to the location of the defect using a sub-micron field of view. The latest e-beam review tools can now reliably and efficiently locate the smallest yield-critical defects reported by the latest inspection systems and, without zooming in, image these defects for classification. This breakthrough has had a tremendous effect on the reduction of SNV counts, and the redistribution of these counts to appropriate defect classes (see Figure). Having a defect pareto that more accurately represents the defects on the wafer allows defect engineers to direct their efforts toward solving the most critical problems.

SNV Types 3 and 4: Previous-Layer Defects and Nuisance Variation. With the matter of false events out of the way, and having ensured that the review system is looking in the right place, we are left the problem of separating previous-layer defects—which truly should be SEM non-visual—from SNV nuisance, i.e. defects correctly imaged by the e-beam review tool but difficult to identify as defects from the review image. If the layer inspected is transparent to the wavelength band of the optical inspection tool, then the possibility that the defect is from the previous layer should be considered. In some cases the previous layer was also inspected, in which case defect source analysis (DSA) can be used to compare the locations of the previous layer’s results to those of the current layer. If the possibility of previous-layer defects has been ruled out, the expertise of the defect engineer is essential for determining the source of the “defect.” If it’s nuisance variation, it may be possible to hone the defect classification schemes to disposition nuisance variation defects into their own category in the defect pareto. Alternatively, the defect engineer may need to adjust the recipe of the inspection system to lower its capture rate for these SNV defects, through choice of a different aperture, wavelength band or polarization mode.

Why does it matter that the SNV defects are properly categorized? Defect engineers act on the information given by the defect pareto, and a high SNV count can disguise or hide real problems. For example, some of these mysterious, disappearing defects may be important DOI lying just outside the field of view of a previous-generation review tool. A misleading defect pareto can result in a delay in getting a new process to yield, or even a delay in getting a new chip to market. Using every means possible to ensure that the defect pareto properly represents the defects on the wafer—especially those defects that affect device yield, performance or reliability—gives fabs the best chance to bring their products to market profitably and on time.

Rebecca Howland, Ph.D., is a senior director in the corporate group and Christina Wang is a senior product marketing manager in the e-beam technology division at KLA-Tencor.


Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

The first MEMS Business Forum, sponsored by MEMS Journal and MEPTEC (MicroElectronics Packaging and Test Engineering Council) was held May 24 at the Santa Clara Biltmore Hotel. Ten speakers presented on topics ranging from near- and mid-term business opportunities to roles of MEMS in broad visions for the future. Registered attendance was just over 90.

Sandhi Bhide, Intel’s Senior Strategist and Futurist, opened the meeting with a discussion of emerging uses and applications for sensors in 2016 and beyond. He opened with a theme from yesterday’s MEPTEC meeting: machines need to become aware of the user’s context and intent, rather than humans conforming to the machine requirements. The fusion of sensors and interpretive software can enable devices to be aware of their connectivity surroundings, environmental changes, and user activity context to modify the presentation and responsiveness of the device. Domains include personal health and safety, social interactions, and relevant business and news events. The notion of proximity detection to help enforce restraining orders against ex-spouses seemed to resonate with this audience. I’m just saying… Extension of this concept to machine-to-machine awareness and interaction melds nicely into the CeNSE (central nervous system for the earth) being promoted by HP. Demands on data processing and storage, bandwidth and energy consumption will be huge, and system reliability will be critical. He anticipates it will take another 8-10 years for the market to reach the trillion sensor level, including both MEMS and other sensor technologies.

Jérémie Bouchaud of IHS iSuppli speculated whether the market for MEMS in consumer electronics will keep growing forever. MEMS microphone revenue jumped 63% in 2011, with background noise suppression driving redundancy and media tablets opening new demand. RF MEMS tuners are starting to show up in mobile handsets in place of analog, facilitating a smaller antenna volume. Based on the current consumer product mix, MEMS annual growth is projected to drop below 10% in 2015 following a +29% peak in 2011. However, there are plenty of ‘next big thing’ candidates that collectively seem to hold the promise of sustaining a healthy growth rate. MEMS for drug delivery and energy scavenging are two leading prospects, with environmental and biosensors in handsets and tablets also very promising. Breath analyzers for a variety of target compounds range from alcohol (excessive consumption) to acetone (hunger and fat burning) to many other biomarkers still in early development. I’ve been hearing more and more that future growth is dependent, at least in part, on “whatever Apple is working on.”

Shahin Farshchi of Lux Capital Management described the role of MEMS in enabling distributed healthcare. VC activity today is weighted toward mobile/social/internet opportunities and healthcare, with lower emphasis on the energy and semiconductors & related equipment segments. The rising prevalence of diabetes and obesity in the US suggests some promising targets. Over 22% of healthcare expenditures are spent on the sickest 1% of the population; 50% of the expenditures care for the 10% most chronically ill. The smart phone platform is gaining broader acceptance as a diagnostic and health data communications tool. Perspiration, respiration, excretion, blood, heart signals and brain waves are relatively accessible data sources with technology that is available or being readied for market today.

Jeffrey Hilbert of wiSpry presented the emerging opportunities for RF MEMS in mobile applications. They manufacture the first MEMS tuner to be implemented in high volume manufacturing in a smart phone (Samsung). Demands for multi-band and multi-mode support, high data rates, power efficiency and decreasing form factor make this an exercise in compromised RF performance. The heart of wiSpry’s approach is an array of MEMS parallel plate capacitor tunable over a wide range using conventional CMOS interconnect materials built atop a 4LM CMOS circuit. The infamous ‘Antennagate’ episode brought to light by the iPhone 4 was resolved by implementing the wiSpry tuner. (The core issue was that the RF antenna tuning and available power changes the instant you touch your phone or put it near your ear. Touchless levitating iPhones were not considered a viable solution.) Tuners alone are a $150M market opportunity. Other applications include tunable antennae, notch filters, power amps and duplex filters. Field demonstrations of complete 1st generation multiband tunable radio front ends can be anticipated in ~6 months.

Prof. Gabriel Rebeiz at UCSD and Director of the DARPA/Industry Center on RF MEMS elucidated the commercialization trends and business opportunities presented by RF MEMS switches and tuners. One shortcoming of RF MEMS is that they require voltage up conversion to 25V or higher for reliable operation; they do not operate at 5V. From 2002 to 2012, front end RF integration has allowed the industry to reduce the RF front end area 13.5x from 5400mm2 to 400mm2 while increasing the number of radios in that space 8x from 2 to 16. For antenna tuning, RF MEMS competitors Cavendish Kinetics and wiSpry compete very well on performance, but SOS/SOI alternatives like Peregrine do much better on manufacturing and device cost. Antenna tuning will be the big market driver through 2018, followed by power amp tuning with filter tuning trailing; the CAGR over the next 7 years will be an impressive +99%. He expects that all smart phones will have tuners by 2014.

Frank Melzer, CEO of Bosch Sensortec shared his perspectives on the interplay between technologies, software and sensor fusion as they conspire to deliver MEMS sensor performance. Barometric pressure devices for geopositional sensing require much greater accuracy than pressure sensors for automotive applications. Ten DoF (degree of freedom) systems have become the benchmark challenge for smart phone integration. The gyroscope component is the limiting factor in terms of size, power management and complexity in 10 DoF systems.

Prof. Al Pisano of UC Berkeley updated the group on the requirements for harsh environment MEMS wireless sensors for energy and power applications. Unlike the miniature, low cost, low power devices needed for smart phones and tablets, these devices may operate at 600°C and cost $100k each. A 1% efficiency gain in a large gas or steam generator can allow it to produce an additional 17 GWH/year of energy, worth almost $2M in additional revenue. In one design, MEMS sensors are bonded to the surface of gas turbine blades, without degrading the necessary aerodynamics, to fine tune the gas flow direction for a more uniform burn and squeeze out an additional percent or two or efficiency. Sensors based on SiC and AlN have been developed for geothermal energy systems that operate at 400°C to 600°C in order to allow in situ subterranean imaging for optimum well identification. This is 4x hotter than oil and gas wells. JFET and bipolar transistors have been fabricated in SiC to operate in this environment. A 20nm layer of graphene is the secret sauce to preserve ohmic contacts and prevent formation of PtSi. The subterranean systems are powered by vibrational energy harvesters based on rapid local pressure fluctuations rather than mechanical vibration.

Harmeet Bhugra of IDT’s MEMS Division explained why people want to buy MEMS alternatives to quartz crystal oscillators. MEMS resonators claim greater reliability and tunability than quartz, with the ability to offer reliable just-in-time delivery akin to related semiconductor technologies. Piezoelectric MEMS oscillators require no DC bias or narrow gaps like capacitive MEMS oscillators, so piezoelectric is the focus for future commercialization. Current aging data shows a frequency stability of ±0.5ppm over 21 months so far.

Prof. Marc Madou of UC Irvine described a sensor technology based on suspended carbon nanowires as a proxy for insight into several new and creative directions into which MEMS fabrication may develop. Structures are formed lithographically using polymer precursors that are pyrolized to glassy carbon. These materials have excellent electrochemical electrode performance, and can be intercalated with materials such as Li (think Li+ battery applications). The suspended nanowires are fabricated with an electrospinning technique that string the fiber between individual posts. In a sense, this addresses the controlled assembly deficiencies associated with carbon nanotubes. Suspension provides 360° access to the sensing element without contamination or undesirable interactions with the surface. In addition to this family of applications, the technique can be applied to fabricate structural colors, which are surfaces that derive their color from microstructural light scattering effects.

Kurt Petersen of KP-MEMS wrapped up the meeting with a retrospective view on MEMS: how did we get here? He published a seminal paper “Silicon as a structural material” 30 years ago, and had been working in MEMS 7 years already before that. The MEMS market today is 3.5% the size of the semiconductor industry, up from 1% in 1986. Market ‘desperation’ can be identified for each incremental jump in the MEMS market dating back to 1985 and HP’s response to dot matrix printer shortcomings with inkjets. The proliferation of MEMS microphones in cell phones was largely driven by the fact that conventional microphones were incompatible with wave soldering, thus requiring that they be hand soldered at assembly. As to the elusive goal of $1T or 1T units, we are presently short by a factor of 100x. As a benchmark, it took the semiconductor industry 35 years to grow 100x. Kurt foresees a 25 year runway for MEMS to achieve this 100x milestone, gated largely by ‘the transformation of the infrastructure of the planet’ associated with CeNSE and the internet of things.

In an exclusive series of blogs, imec’s science writers report from the International Technology Forum (ITF) in Brussels. This year, ITF’s theme was “It’s a changing world. Let’s make a sustainable change together”.

What would our smart world be without displays? That was the question posed by imec’s Paul Heremans, Fellow and Director Large Area Electronics, in a presentation titled “Towards flexible active matrix OLED displays.” On a daily basis, we run our eyes over dozens of displays for various purposes, he said. And this number might increase if we look at the innovations that the display industry has in mind. No more newspapers or paper novels, but digital e-readers on mobile displays. No more paper posters for advertisement, but digital posters on large flexible screens. It’s time for a new era where OLED displays and flexible displays on plastic substrates enter the market and gradually replace cathode ray tubes and liquid crystal displays. They will enable a new wave of products and an increase of the display market size in general.

Meanwhile, the first commercial OLED displays have appeared in consumer products. So, how can an R&D centre such as imec and Holst Centre contribute to such a promising and fast evolving industry? Flexible OLED displays can be extensively adopted, e.g. in flexible posters for advertisement, as rollable TV screens, or, in smaller format,  as an e-reader or on a smart card. And all these applications come with very different specifications. Therefore, says Heremans, it’s important to focus on just one, or on a very few, applications. And they chose the mobile tablet display as the point of focus of their new technology integration program, launched by imec and Holst Centre at the beginning of 2012. The mobile tablet will gather all functionalities of a mobile phone, e-reader, digital camera, MP3 player, tablet pc, netbook… in just one device. The screen must be comfortable enough to be read and touched, and small, thin and flexible enough to be mobile. Such a display must be low power, low cost and high resolution. A humidity barrier, new thin-film transistor technology to drive the pixels, innovative technologies for patterning… the list of required innovations is impressive.

According to Heremans, the prospects are good. The researchers involved in the program can rely on 6 years of experience in the various building blocks, obtained from collaboration within Holst Centre. As a result, only one quarter after the launch of the program, they have realized the first integrated display. It’s not yet the targeted 300ppi OLED display, but it’s good enough to study the pixel engines and to understand what improvements need to be done in order to get to the ultimate targeted mobile tablet display.

Mieke Van Bavel, science editor, imec, Belgium

May 25, 2012 — THE BEST rankings from VLSIresearch identify the highest-rated suppliers of wafer processing, assembly, and test equipment. Chipmakers applauded their suppliers with increased ratings this year, according to a survey by VLSIresearch.

Wafer processing equipment supplier rankings are available here.

Suppliers of assembly equipment
Rank Company Rating
1 Hitachi High-Technologies 9.05
2 F&K Delvotec 8.51
3  Kulicke & Soffa 7.70
4 ASM International 7.61
Source: VLSIresearch 2012 Customer Satisfaction Survey.

Hitachi High-Technologies, a leading die bonder supplier, retained its #1 position for the second year in a row with an excellent rating of 9.05. This rating also earned Hitachi High-Tech the highest rating among all THE BEST Suppliers of 2012. The company topped all categories, earning its highest ratings among all assembly equipment suppliers in 14 of 15 categories. The company

In an exclusive series of blogs, imec’s science writers report from the International Technology Forum (ITF) in Brussels. This year, ITF’s theme was “It’s a changing world. Let’s make a sustainable change together”. More info: www.itf2012.com

“If we succeed in connecting biology with microsystems, we can revolutionize life sciences,” begins Peter Peumans, department director bio-nano electronics of imec. And it’s high time for a revolution. Just look at the stethoscopes doctor’s are using today and the microscopes that labs are using and compare this to a 100 years ago. It hasn’t changed much.

“The perfect example of connecting biology to microsystems is the bioreactor we are developing,” explains Peumans. He shows a chip with a dense array of electrodes onto which a cell culture can be applied. “The electrodes allow to measure activity of single cells. Moreover, they also allow to create a local voltage to the cell which results in nanosize pores in the membrane. In this way, the patch clamp technique can be automated and performed simultaneously on hundreds of cells. These smart bioreactors can be used to study neurons or cardiac cells or even to culture stem cells. The production of stem cells holds a high promise for a lot of diseases,” emphasizes Peumans.

He also shows three other promising examples of technologies that connect biology and microsystems. The first one is a neuroprobe with close to 250 electrodes. This new generation of probes will be a key asset to brain research.

Another imec research topic Peumans mentions is the high speed cell inspection platform which is based on microscopes on chip. These microscopes don’t use any sort of optics. “The platform allows to take microscopic images of cells. Based on these images, the cells are classified and sorted by using a fast microfluidic switch that routes the cells into a chosen channel,” says Peumans. Such inspection chips could be used for the diagnosis of cancer in a very early stage.

And finally Peumans shows the promise of high-throughput molecular analysis by marrying biology and microsystems. He is convinced that high-throughput sequencing will become an important diagnostic tool in the future by making it low cost, fast and easy to use. “We have developed a chip with a dense array of molecular sensors. This combined with the capability to quickly wash and flood these local sensor sites with reagents results in the basic infrastructure required for genome sequencing,” states Peumans. “Imec is committed to make partnerships between the world of biology and microsystems and as such contribute to the coming revolution in life sciences.“

Els Parton, Science editor imec

May 25, 2012 — VLSIresearch polled semiconductor manufacturers about their tool suppliers, asking chipmakers to rank equipment providers on customer satisfaction. This year’s results show renewed focus on fab needs.

Large suppliers of chip-making equipment

Rating

Focused suppliers of chip-making equipment

Rating

1 Novellus

8.95

1 F&K Delvotec

8.51

2 Advantest

8.37

2 Oerlikon

8.19

3 Teradyne

8.35

3 Plasma-Therm

8.18

4 Hitachi High-Technologies

8.09

4 EV Group

8.14†

5 ASML

8.07

5 LTX – Credence

8.14†

6 Applied Materials

8.02

6 Nanometrics

8.10

7 Tokyo Electron

7.84

7 Delta Design

7.62

8 Kulicke & Soffa

7.70

8 Agilent Technologies

7.60

9 Hitachi Kokusai Electric

7.58

9 Seiko Epson

7.56

10 Nikon

7.48

10 ACCRETECH – Tokyo Seimitsu

7.45
Source: VLSIresearch 2012 Customer Satisfaction Survey.

† Rankings for the #4 and 5 positions were determined on ratings carried out to three decimal places.

For the first time in the history of the survey more than half of the suppliers in each category had greater than an 8.0 average rating, compared to two suppliers last year. As a result the average rating for these 10 BEST suppliers was 8.0, an increase of 0.35 points over last year. “This year’s ratings reflect new supplier initiatives to focus on their customers’ satisfaction, with better service and products,” commented G. Dan Hutcheson, Chairman and CEO of VLSIresearch.

Large Suppliers of Chip Making Equipment

Novellus retained its #1 spot this year with an increase of 0.77 points to 8.95. The company’s dedication to customer satisfaction paid off this year by earning the highest ratings among all Large Suppliers in 14 of the 15 rating categories. Advantest and Teradyne improved ranking positions substantially this year while competing for the 2nd and 3rd positions, with Advantest slightly exceeding Teradyne by a mere 0.02 points. Teradyne leaped from the 9th spot and Advantest from 7th, with point increases of 1.35 and 1.01 respectively. Advantest achieved its highest rating in trust in supplier at 8.7; Teradyne in would recommend supplier, also at 8.7.

Although both Hitachi High-Technologies and ASML achieved increased ratings this year, they dropped a slot to 4th and 5th positions as a result of Advantest and Teradyne’s jumps. ASML, well-known for its highly-productive lithography tools earned the highest rating of all Large Suppliers in technical leadership. Hitachi High-Technologies’ highest attribute was in quality of results.

Focused Suppliers of Chip Making Equipment

F&K Delvotec, a supplier of wire bonders, rose to the top spot for the first time this year with a rating of 8.51. The company garnered the highest rating of all Focused Suppliers in nine categories, with its highest rating of 9.0 earned in both field engineering support and support after sales.

Oerlikon retained its #2 rank with a rating of 8.19. This PVD supplier achieved its highest rating of 8.4 in five categories: would recommend supplier, trust in supplier, product performance, usable performance, and uptime.

Plasma-Therm moved up five slots to the 3rd position with a rating of 8.18. Customers applauded this etch & clean supplier as the highest in commitment of all Focused Suppliers as well as a tying for spares support with F&K Delvotec.

Most Improved Suppliers

In Large Suppliers, Teradyne showed the most improvement with its movement up from 9th to 3rd position and a 19% surge in its rating. Teradyne is followed by Applied Materials with a 17% jump in its rating. Nikon closed out this race with an increased rating of 16%.

Nanometrics deserves particular notice in Focused Suppliers with a remarkable 47% climb in its ratings, leaping from the 36th to the 6th slot. LTX-Credence’s significant increase of 33% moved it up from the 31st to the 5th slot. EV Group also showed a notable improvement with a 16% rise from the 15th to the 4th spot.

Stay tuned for additional rankings from VLSIresearch’s survey!

The VLSIresearch annual Customer Satisfaction Survey on Chip Making Equipment allows chip manufacturers to provide feedback on their suppliers. VLSIresearch is a leading provider of market research and economic analysis on the technical, business, and economic aspects within nanotechnology and related industries. Website: www.vlsiresearch.com.

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