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Heinz Kundert, president of SEMI Europe, started off the Industry Strategy Symposium Europe conference by noting that this year’s event attracted more than 200 attendees, and 30 sponsors. He said there are several new developments in the marketplace, such as the transition to 450mm wafers and smaller dimensions with EUV. “These will have enormous impact on the competitiveness of individual companies, as well as entire regions such as Europe,” he said. ISS Europe has a strong focus on 450mm this year, in an effort to showcase Europe’s strength in this emerging technology.

A common theme among the presenters on the first day was how Europe might bridge the so-called “valley of death” between basic research and volume manufacturing. Europe leads the world in research and new patents, it was generally agreed, but has lost ground to the rest of the world when it comes to putting these ideas into practice.

The first step in bridging this gap is to identify key enabling technologies (KETs), according to keynote speaker Professor Gabriel Crean, scientific director of the Division of Technological Research of the Atomic Energy Commission of France (CEA).

“We have to try to reindustrialize Europe,” he said. Three pillars needed to support the bridge between research and industrialization: 1) research and technological facilities, 2) pilot production lines, and 3) globally competitive manufacturing facilities.  In his keynote talk titled “Key Enabling Solutions for a Competitive Europe: Challenges and Solutions,” Crean said work at building the first pillar is already underway. “We asked for a significant increase in the budget for tech research in the European Commission budget,” he said.

He said KETs are essential to develop and manufacture any kind of advanced products, and therefore important to underpin European economic growth. The six KETS indentified by the European Commission as the most critical are:  Micro- and nanoelectronics; advanced materials;  nanotechnology;  biotechnology; photonics and advanced manufacturing. All of these are knowledge-intensive, and require rapid innovation cycles, high capex, and highly skilled employees. A commission identified KETs  in a report "Preparing for our future: Developing a common strategy for key enabling technologies in the EU" in 2009.

Crean said these KETs are at the basis of all advanced products we have today, particularly ones that have been successful  in Europe: cars, lighting and nanoelectronics. “No matter what example of a product we can find a number of those key technologies in there,” he said. He emphasized that many products require multiple KETs, and that they need to be addressed with a “multi-KETs” toolbox. That could be a challenge in the EU since different commissioners oversee different technology areas.  “We really need to see how we can optimize this moving forward,” he said.  

He noted with some alarm the “very aggressive” action in the U.S. at the federal and State level to attract foreign firms. He noted SAFT’s $200 million battery production facility in the U.S. was funded by a $95.5 million grant from the U.S. DoE. “The U.S. aggressively targets our KETs, our early champions of technology,” he said.

He also talked about Europe’s trouble maintaining its lead in the photovoltaic industry. He noted that in 2001, there were six German companies in the top 10. By 2010, there was only one (Q-Cells). “With the recent news that Q-Cells cutting manufacturing operations in Germany by 50%, and relocating them to Malaysia, there will none,” he said. “There’s a very unlevel playing field,” he added.

Europe recently implemented the European Regional Development Fund (ERDF), with funding 300+ billion euro.  This opens up “vast new possibilities of funding for microelectronics in Europe,” Crean said.

In this 2-part series, Part 1 describes aluminum nitride (AlN) and what it accomplishes as a ceramic substrate for high-brightness light emitting diodes (HB-LEDs). Part 2 provides analysis of the impact of this new technology on sintering throughput.

February 24, 2012 — HB-LED packaging requirements push the materials envelope for low cost and high thermal performance. As manufacturers look to shrink LED size, the substrate is required to dissipate more heat. The commercial imperative to decrease the $/Watt figure of merit for light output is also increasing interest in low-cost substrates.

HB-LED devices are bonded to a ceramic tile, comprising a ceramic substrate metallized with thick-plated copper (Cu), with Cu-filled via interconnections to the printed circuit board (PCB). Heat conduction from the active device occurs through both the Cu vias and the ceramic. The ceramic material provides electrical isolation between the different polarity inputs that drive the LED.

Traditionally, 96% Al2O3 is used as the ceramic substrate in HB-LED applications because of its low cost and good mechanical stability. However, with a thermal conductivity of only 20W/m-K, alumina does not contribute significantly to heat transport in the tiles. This brings in the opportunity for using other ceramic materials with higher thermal performance such as AlN or Si3N4. Both of these alternatives cost more than alumina.

Aluminum Nitride

Aluminum nitride (AlN) is a polycrystalline, high melting temperature (refractory), ceramic material with an advantageous set of properties for die-level packaging of HB-LEDs and power semiconductors: good electrical insulation, high thermal conductivity, high flexural strength, stable in high temperatures, and ease of fabrication (laser drilled, metallized, plated and brazed).

Table 1. AlN properties.

Properties

Value

Comments

Thermal Conductivity

170 W/m-K

Laser Flash

Flexural Strength

325 MPa

Four Point Bend Test

Volume Resistivity

1014 Ohm-cm

Four Point Probe

Metallization Systems

Thin Film, DBC

Thin Film, DBC

 

As power densities of semiconductor devices increase, the need for thermal dissipation from packaging, particularly for temperature-sensitive devices such as LEDs. AlN has a thermal conductivity that is 8-9x higher than competitive materials such as Al2O3. It offers an excellent answer to increasing thermal demands on first-level packaging materials.

Also read: LED packaging report reveals costs, reliability impact of package

Applications with high and increasing thermal demand include: radio frequency (RF) power components for cellular infrastructure, HB-LED, power semiconductors for motor control, packaging for concentrated photovoltaic (CPV) installations, and packaging for semiconductor lasers used in telecommunications.

AlN ceramic substrates are typically made 15 to 60 mils thick, and up to 4.5” square (larger for some specialized applications). These substrates are fabricated using conventional ceramic processing technology.

Table 2. A typical fabrication sequence.

Fabrication Step

Processing Method

Equipment and Comments

Form a slurry with ceramic powder, sintering aids and organic binders

Slurry mixing and milling

Non-aqueous Solvents

Form a thin sheet

Tape casting

Non-aqueous tape caster

Cut out non-fired substrates

Blanking

Press which cuts tape

Press to a controlled density

Iso static lamination

Produces uniform density

Burn out the binder

Binder removal furnace

Continuous thick film furnace in air. Removes binder so only ceramic powder and sintering aids are left in sheet.

High temperature densification

Sinter at temperatures above 1800C to full density

High Temperature, high cost, Tungsten or graphite batch furnace

Flatten dense substrates

Fire in stack with weight at high temperature (near 1800C)

High Temperature, high cost, Tungsten or graphite batch furnace

 

AlN has a range of beneficial properties for high-thermal-demand applications. However, the cost of AlN has limited its utilization. Typically, AlN costs 5-7x more than lower-performance alumina on a cost/square inch basis.

Key contributors to this higher cost structure:

  • Currently available AlN powder is approximately 20x more expensive than alumina powder of comparable quality (purity, particle size).
  • AlN tape must be fired in a non-oxidizing atmosphere. This means that binder removal, which is typically done through oxidation, must be done in a separate furnacing step (at a temperature well below the sintering temperature). A thick film continuous furnace can be used. For alumina, binder removal can be accomplished in the sintering furnace in one furnace step.
  • AlN is sintered in a batch furnace with much lower throughput than continuous furnaces used for alumina. In addition, these batch furnaces are constructed using Mo and W metal heat shields and heating elements  because of the extremely high sintering temperatures (>1800C), so the overall furnace cost is very high.
  • AlN can also be sintered in graphite batch furnaces. Though lower capital cost than W furnaces, the sintering fixtures for this type of furnace are very high cost and the throughput is still low due to batch processing. Also, the interaction of AlN with the carbon containing atmosphere is a graphite furnace must be limited to produce high quality product.
  • The considerations of furnace cost and low throughput for sintering are also a factor for flat fire, so there is essentially a “double hit” for using batch processing.
  • Alumina can be processed in an aqueous environment. This makes the tape fabrication less expensive than the AlN process which must utilize non-aqueous solvents. This is a significant factor for tape casting.

HB-LED-grade AlN

CMC Laboratories Inc. developed a new material that addresses the lower-throughput batch sintering of AlN, higher-cost graphite batch sintering fixtures, and “double” firing costs. This new technology allows AlN to be sintered at lower temperatures in a continuous furnace very similar to furnaces used for alumina.

Table 2. Key properties for the low-temperature-sintered, lower-cost HB-LED Grade AlN compared to the standard, high temperature sintered, higher cost AlN material that is currently commercially available.

Properties

Current AlN

HBLED Grade

Thermal Conductivity

170-190 W/m-K

110-130 W/m-K

Flexural Strength

325 MPa

300 – 325 MPa

Volume Resistivity

1014 Ohm-cm

1014 Ohm-cm

Metallization Systems

Thin Film, DBC

Thin Film, DBC

 

All of the properties are very similar, except that the thermal conductivity of the HB-LED grade material is about 24% lower than the high-cost AlN, but still 6+ times higher than alumina. This makes the HBLED grade material suitable for all but the highest thermal demand applications for AlN.

HBLED grade AlN is made with the same basic processing steps outlined in Table 2 that are used for the high-temperature material. The key difference is the sintering additives that allow the material to densify at 1675°-1690°C as compared to the conventional 1820°-1835°C. Tape binder formulations, tape casting conditions, and the binder burn out process are also the same as, or very similar, to conventional AlN material.

Figure 1 shows a 4.5” x 4.5” x 20 mils substrate made from HBLED grade material that was fired at 1690°C in a nitrogen gas atmosphere with a hold time at sintering temperature of 3 hours.

Figure 1. Low-temperature sintered AlN substrate.

Sintering aids for AlN ceramics form a liquid phase at the sintering temperature that increases the rate of densification and they getter oxygen from the AlN grains during sintering. Since the oxygen content of the AlN grains controls AlN’s thermal conductivity, effective oxygen gettering is key to achieving the highest possible thermal performance. A plot of thermal resistivity vs. oxygen content is shown in Figure 2 [1].

Typical sintering aids for AlN are rare earth oxides with a large chemical driving force for reaction with oxygen in the AlN grains. For the conventional high temperature system, Y2O3 is added to the AlN. At high temperatures during sintering, the added Y2O3 reacts with oxygen from the AlN grains in the form of Al2O3 to form various Y-Al-O phases. The Y2O3– Al2O3 pseudo-binary phase diagram, which is key to understanding the conventional high temperature sintering process for AlN, is shown in Figure 3 [2]. As is evident from the phase diagram, there is a eutectic in the Y2O3– Al2O3 system at 20% Al2O3 which melts at 1780°C. This is the initial liquid phase that promotes sintering. This liquid phase reacts with the added Y2O3 to form more yttria-rich Y-Al-O compounds, which in turn reacts with oxygen from the AlN grains. This reaction shifts the composition toward more Al2O3 rich compositions as oxygen is gettered from the grains. For conventional high temperature sintered AlN, the final second phase composition after the sintering process is complete is composed of YAP (Al2O3:Y2O3), YAM (2Y2O3:Al2O3) or a combination of YAP and YAM.

Figure 2. Oxygen vs. thermal resistivity of AlN.

To summarize, there are two reasons for the high sintering temperature. First, the temperature must be high enough to melt the additive phase to form a liquid which enhances the rate of sintering by orders or magnitude. Second, the temperature must be high enough so that oxygen can diffuse out of the AlN grains during sintering to enhance the thermal conductivity of the AlN ceramic.

There is a third critical requirement for the additive phase during AlN sintering. While a liquid, the Y-Al-O phase will completely surround each AlN grain. If we define a wetting angle between the AlN and Y-Al-O measured at the 3 grain junctions, the microstructure has a very low wetting angle that is less than 60°C. This type of microstructure is shown in the SEM micrograph in Figure 4A. The dark grains in this figure, which are about 10µm large, are the AlN. The bright phase is the Y-Al-O.

Figure 3. Y2O3– Al2O3 pseudo-binary phase diagram.

 

There are two critical performance issues with a wetted microstructure. First, because AlN fracture is inter-granular, the presence of a Y-Al-O phase between the grains lowers the tensile strength of the ceramic by a large factor. The second problem is that a wetted microstructure results in Y-Al-O covering large portions of the surface of the substrate. This reduces the consistency of AlN metallization processes.

Figure 4A. Wetted microstructure- High-temperature AlN.
Figure 4B. De-wetted microstructure- High-temperature AlN.

 

A key requirement for the oxide second phase during AlN sintering is that the oxide phase de-wet the ceramic grains during the later stages of the sintering process so that the final microstructure will have a de-wetted Y-Al-O phase as shown in the micrograph in Figure 4B.

Figure 5. Microstructure sintered at 1675C (and zoom on a particular spot).

These same basic considerations for sintering of high temperature, conventional AlN are relevant to designing a low temperature sintering process:

  • The sintering additive must melt at the sintering temperature to facilitate liquid phase sintering kinetics.
  • The temperature must be high enough for oxygen to diffuse out of the AlN grains during sintering. This consideration puts somewhat of a lower limit on how low AlN can be sintered to produce high thermal conductivity.
  • The liquid phase must de-wet from the AlN grains after densification to form a de-wetted microstructure and thus high flexural strength.
  • This de-wetting is also required to produce ceramic with high electrical resistivity

Figure 5 shows the microstructure of a low temperature formulation that was fired at 1675°C. This has a modified sintering additive package that will melt at much lower temperature than the conventional Y-Al-O additives, but still has a strong chemical driving force to getter oxygen from the AlN grains.

As in the previous micrographs, the dark grey areas are the AlN ceramic grains, about 3-5µm in size, and the bright areas are the oxide sintering additive phase. The difference in color between the micrographs in Figure 4 and Figure 5 are due to imaging conditions, not material differences.

In Part 2 here, the furnace considerations are discussed, as well as furnace throughput. It covers the role of the oxide sintering phase in AlN in defining the materials microstructure and thus determining key properties such as thermal conductivity and mechanical strength.

Jonathan Harris, PhD is president of CMC Laboratories Inc., www.cmclaboratories.com.

References:

[1] J.H. Harris, R.A. Youngman and R.G. Teller, J. Mater. Res. 5, 1763 (1990)

[2] J. McCauley, and N. Corbin, High Temperature Reactions and Microstructures in the Al2O3-AlN System, Progress in Nitrogen Ceramics, ed. F.L. Rley, Martinus Nijhoff Pub., The Netherlands, 111- 118 © 1983.

February 24, 2012 — North America-based manufacturers of semiconductor equipment posted $1.18 billion in orders, $1.24 billion in billings, and a book-to-bill of 0.95 in January 2012, according to the January Book-to-Bill Report by SEMI. This is the 4th consecutive month of growth in wafer fab tool orders.

North American semiconductor manufacturing tool providers booked $1.18 billion in orders for January (three-month average), 7% more than in December and 22.1% less than January 2011.

Tool makers recorded $1.24 billion in billings (three-month average), 4.7% below December’s $1.30 billion, and 30.7% less than January 2011.

"While year-over-year bookings and billings are lower than in 2011, the current outlook for equipment spending in 2012 has improved over the past couple of months," acknowledged Denny McGuirk, president and CEO of SEMI.  

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars. A book-to-bill of 0.95 means that $95 worth of orders were received for every $100 of product billed for the month.

Month Billings (3-mo. avg, $M) Bookings (3-mo. avg, $M) Book-to-Bill
Aug 2011  1,457.7 1,162.4 0.80
Sept 2011  1,313.5 926.5 0.71
Oct 2011 1,258.3 926.8 0.74
Nov 2011 1,176.7 977.2 0.83
Dec 2011 (final) 1,300.0 1,102.9 0.85
Jan 2012 (prelim) 1,238.5 1,179.7 0.95
Source: SEMI February 2012.

The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

The data are contained in a monthly Book-to-Bill Report published by SEMI. The report tracks billings and bookings worldwide of North American-headquartered manufacturers of equipment used to manufacture semiconductor devices, not billings and bookings of the chips themselves. The Book-to-Bill report is one of three reports included with the Equipment Market Data Subscription (EMDS).

SEMI is a global industry association serving the nano- and micro-electronic manufacturing supply chains. For more information, visit www.semi.org.

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In this three-part series, SEMATECH’s authors cover metrology for FinFETs (Read Part 1) and 3D memory devices (Read Part 2), and defect detection capabilities at 22nm. The series appears in the upcoming March 2012 issue of Solid State Technology, along with other metrology-focused pieces from KLA-Tencor and Entegris. Subscribe to Solid State Technology magazine here.

February 23, 2012 — Future challenges for semiconductor defect metrology go beyond merely extending the capability of current technologies to meet International Technology Roadmap for Semiconductors (ITRS) requirements [8]. In recent years, the yield enhancement ITRS chapter has shown that the semiconductor industry consistently arrives at each new technology node without a long-term solution that combines defect sensitivity and throughput requirements at either development, ramp-up, or HVM phases.[8]   Both defect inspection and review are approaching their fundamental limits, which cannot be easily circumvented with gradual improvements on workhorse toolsets [13].

Figure 3. There is a single defect in this 22nm-node SRAM array. Can you find it?

In the specific case of inspection, optical simulations show that the defect contrast signal decays aggressively beyond the 22nm node, and predict that deep ultraviolet (DUV) bright field tools are likely to lack useable signal at or beyond the 11nm node. Wavelength scaling is not expected to provide an acceptable solution, prompting the need to seek alternative technologies that rely on different contrast mechanisms that may bridge this gap: interferometric (phase shift signal) [14], near-field (sub-wavelength resolution), or fast probe microscopy [15]. This path-finding effort will have a steep learning curve in terms of the application space for these techniques and the engineering to translate them into manufacturing-worthy tools. An alternative path to achieve sub-11 nm inspection capability may be electron beam (e-beam) inspection. In this case, the challenge is not resolution but increasing the system throughput by several orders of magnitude, which will most likely require a breakthrough in e-beam column parallelization. Early efforts are currently driven by lithography needs, but could benefit the inspection application space [16].

After defects are found (see Figure 3 for an example), they must be identified and sourced to maintain yield, requiring increasing amounts of off-line lab analysis. As features shrink, the X-ray interaction volume used in EDX for in situ defect analysis is becoming larger than the sizes of critical defects. The only solution appears to be an explosive growth in the workload of the TEM characterization lab. The limitation to TEM is not capability but throughput. TEM requires extensive, time-consuming sample preparation. Moreover, the microscope itself is a complex device that traditionally requires hours of work by a highly skilled operator to obtain good results. The solution therefore is to focus on both problems. To this end, SEMATECH is working with leading suppliers to develop faster sample preparation techniques, by both optimizing existing technologies and testing novel methods such as plasma focused ion beam (FIB) and laser-based milling. SEMATECH is also working in cooperation with its strategic partners to develop higher speed TEM imaging capabilities. This includes testing the latest generation of high sensitivity and high throughput windowless detector systems and developing automated image setup and metrology on critical dimension scanning/tunneling (CD-S/TEM) systems.

Figure 4. Sample image of a high-speed EDX element map taken on a SEMATECH FinFET sample. Total collection time was 4 minutes.

Conclusion
As device technology transitions from traditional scaling to new architectures, new application needs are driving metrology towards evolutionary and revolutionary shifts in technologies and methodologies. Adaptation to new tool paradigms, enhancements of existing technologies, and productivity innovations will be critical to maintain process control and high yield in the coming technology generations. The SEMATECH Advanced Metrology Program is well positioned to develop solutions to address the measurement challenges of next generation devices.

Miss Parts 1 and 2? Check them out:

References
[1] Doyle, B. et al., “Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout,” Symposium on VLSl Technology Digest of Technical Papers, pp. 133-134 (2003).

[2] Vaid, A., et al. “A holistic metrology approach: hybrid metrology utilizing scatterometry, CD-AFM, and CD-SEM.” Metrology, Inspection, and Process Control for Microlithography XXV. Proceedings of the SPIE, Volume 7971, pp. 797103-797103-20 (2011).

[3] Wang, C., Choi, K., Chen, Y. Price, J., Ho, D., Jones, R., Soles, C., Lin, E., Wu, W.L., Bunday, B. “Nonplanar high-k dielectric thickness measurements using CD-SAXS.” Proc. SPIE, v. 7272, pp 72722M (2009).

[4] De Martino, A., et al., “Comparison of Spectroscopic Mueller Polarimetry, Standard Scatterometry and Real Space Imaging Techniques (SEM and 3D-AFM) for Dimensional Characterization of Periodic Structures,” Proc. of SPIE Vol. 6922, 69221P (2008).

[5] Larson, D.J., and Kelly, T. F., “Nanoscale Analysis of Materials using a Local-Electrode Atom Probe,” Microscopy and Microanalysis Volume: 20, Issue: 3, pp: 59-62 (2006).

[6] Mody, J. et al., “Dopant and Carrier Profiling in FinFET-Based Devices with Sub-Nanometer Resolution,” 2010 Symposium on VLSI Technology, pp. 155-156

Abraham Arceo is a metrology development engineer at SEMATECH Advanced Metrology group. For the past three years he has been involved in film and defect inspection metrology development.

Benjamin Bunday is the project manager of CD Metrology and a Senior Member Technical Staff at SEMATECH (Albany, NY, USA). For ten years he has led SEMATECH/ISMI’s CD-SEM and OCD benchmarking, advanced CD technology evaluation and development efforts, and SEMATECH’s Advanced CD Metrology Advisory Group (AMAG).

Aaron Cordes is a research engineer for Sematech in Albany doing work on AFM, TEM, and focused ion beam metrology. He is also a PhD student with SUNY Albany’s College of Nanoscale Science and Engineering.

Victor Vartanian is a metrology engineer at SEMATECH in Albany, New York. Before coming to SEMATECH, he worked at Freescale Semiconductor in Austin, Texas, where he worked on applications of strained silicon to advanced transistor design and analytical applications of FTIR and mass spectrometry to environmental issues in semiconductor manufacturing and in process optimization.

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A team of researchers at the University of New South Wales, Purdue University and the University of Melbourne have built the smallest transistor ever using a single phosphorous atom.

The single-atom device was described in a paper in the journal Nature Nanotechnology (published Feb. 19).

Michelle Simmons, group leader and director of the ARC Centre for Quantum Computation and Communication at the University of New South Wales, says the development is less about improving current technology than building future tech.

"This is a beautiful demonstration of controlling matter at the atomic scale to make a real device," Simmons says. "Fifty years ago when the first transistor was developed, no one could have predicted the role that computers would play in our society today. As we transition to atomic-scale devices, we are now entering a new paradigm where quantum mechanics promises a similar technological disruption. It is the promise of this future technology that makes this present development so exciting."

Caption: A controllable transistor engineered from a single phosphorus atom has been developed by researchers at the University of New South Wales, Purdue University and the University of Melbourne. The atom, shown here in the center of an image from a computer model, sits in a channel in a silicon crystal. The atomic-sized transistor and wires might allow researchers to control gated qubits of information in future quantum computers (Purdue University image).

The same research team announced in January that it had developed a wire of phosphorus and silicon – just one atom tall and four atoms wide – that behaved like copper wire.

Simulations of the atomic transistor to model its behavior were conducted at Purdue using nanoHUB technology, an online community resource site for researchers in computational nanotechnology.

Gerhard Klimeck, who directed the Purdue group that ran the simulations, says this is an important development because it shows how small electronic components can be engineered.

"To me, this is the physical limit of Moore’s Law," Klimeck says. "We can’t make it smaller than this."

Although definitions can vary, simply stated Moore’s Law holds that the number of transistors that can be placed on a processor will double approximately every 18 months. The latest Intel chip, the "Sandy Bridge," uses a manufacturing process to place 2.3 billion transistors 32 nanometers apart. A single phosphorus atom, by comparison, is just 0.1 nanometers across, which would significantly reduce the size of processors made using this technique, although it may be many years before single-atom processors actually are manufactured.

The single-atom transistor does have one serious limitation: It must be kept very cold, at least as cold as liquid nitrogen, or minus 391 degrees Fahrenheit (minus 196 Celsius). "The atom sits in a well or channel, and for it to operate as a transistor the electrons must stay in that channel," Klimeck says. "At higher temperatures, the electrons move more and go outside of the channel. For this atom to act like a metal you have to contain the electrons to the channel.

"If someone develops a technique to contain the electrons, this technique could be used to build a computer that would work at room temperature. But this is a fundamental question for this technology."

Although single atoms serving as transistors have been observed before, this is the first time a single-atom transistor has been controllably engineered with atomic precision. The structure even has markers that allow researchers to attach contacts and apply a voltage, says Martin Fuechsle, a researcher at the University of New South Wales and lead author on the journal paper.

"The thing that is unique about what we have done is that we have, with atomic precision, positioned this individual atom within our device," Fuechsle says.

Simmons says this control is the key step in making a single-atom device. "By achieving the placement of a single atom, we have, at the same time, developed a technique that will allow us to be able to place several of these single-atom devices towards the goal of a developing a scalable system." 

The single-atom transistor could lead the way to building a quantum computer that works by controlling the electrons and thereby the quantum information, or qubits. Some scientists, however, have doubts that such a device can ever be built.

"Whilst this result is a major milestone in scalable silicon quantum computing, it does not answer the question of whether quantum computing is possible or not," Simmons says. "The answer to this lies in whether quantum coherence can be controlled over large numbers of qubits. The technique we have developed is potentially scalable, using the same materials as the silicon industry, but more time is needed to realize this goal."

Klimeck says despite the hurdles, the single-atom transistor is an important development. "This opens eyes because it is a device that behaves like metal in silicon. This will lead to many more discoveries," he said.

"When I established this program 10 years ago, many people thought it was impossible with too many technical hurdles. However, on reading into the literature I could not see any practical reason why it would not be possible," Simmons says. "Brute determination and systemic studies were necessary – as well as having many outstanding students and postdoctoral researchers who have worked on the project."

Klimeck notes that modern collaboration and community-building tools such as nanoHUB played an important role. "This was a trans-Pacific collaboration that came about through the community created in nanoHUB. Now Purdue graduate students spend time studying at the University of New South Wales, and their students travel to Purdue to learn more about nanotechnology. It has been a rewarding collaboration, both for the scientific discoveries and for the personal relationships that were formed."

February 20, 2012 — ElectroIQ recently spoke with Mariquita Gordon from Texas Instruments DLP’s Embedded division about the company’s micro electro mechanical system (MEMS) digital light processing (DLP) technology. DLP is traditionally associated with projectors, television displays, and pico projectors. In TI’s 4th generation embedded DLP evalution module, the LightCrafter, TI is opening up the applications space to bring DLP into new imaging markets, such as security, dentistry, and more.

DLP chips are MEMS designs with 400,000 micro moving mirrors. Texas Instruments has sold 33+ million units for a range of consumer and high-reliability applications. "We have test DLP mirrors in the TI labs that have been moving for 16 years," Gordon said, pointing to the reliability of the devices. Texas Instruments topped the IHS iSuppli 2010 MEMS supplier rankings, on the strength of its DLP chip sales.

Traditional imaging markets are saturated and price-pressured, and DLP products like projection TVs have felt the squeeze. These new imaging applications represent an area of growth for TI’s MEMS business. The LightCrafter Module came about from customer feedback on previous generations of evaluation kits.

The LightCrafter eval kit is designed to be small, lower-cost, and forgo cosmetic features like a coverplate over the chipset, making it easier to design right into a final product. Some users will prototype with the module, then modify it for final volume production. Others will integrate the module as-made into products, said Gordon. "We want users to come to TI with ideas for MEMS-based products that fall outside of our traditional end-market. There are many applications that we can think of for DLP chipsets, but there’s also a whole range that we haven’t thought of," Gordon explained. The more "plug-and-play" LightCrafter is, the more users will discover applications for it, she added.

Some of the non-traditional imaging applications TI’s seen DLP applied in include 3D measurement of teeth for dental crown designs. Here, MEMS can save significant time, human involvement, and costs in the crown’s modeling. Security applications, such as facial mapping, are also emerging. DLP-based systems can replace lab-based chemical analysis with fast, portable, handheld devices. MEMS technology enables one chipset to sense multiple chemicals. Learn more about bio applications from Lee Mather’s blog, DLP technology finds more application in bio from our sister publication BioOptics World.

LightCrafter is the first evaluation kit that Texas Instruments will sell through its online e-store, a strategy that TI plans to use for all kits going forward. There is also an entire eco-system of developers and technical specialists available to help bring new DLP-based products to market quickly, Gordon said.

More on the LightCrafter evaluation kit: The kit includes a DLP 0.3 WVGA chipset, DMD controller board, and more. Get all the specs at Texas Instruments (TI) debuts DLP evaluation module or visit www.ti.com/dlplightcrafter

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In this three-part series, SEMATECH’s authors cover metrology for FinFETs (Part 1) and 3D memory devices, and defect detection capabilities at 22nm (Part 3). The series appears in the upcoming March 2012 issue of Solid State Technology, along with other metrology-focused pieces from KLA-Tencor and Entegris. Subscribe to Solid State Technology magazine here.

February 16, 2012 — The 22nm semiconductor node marks the beginning of a major transition from conventional scaling-driven planar devices to complex 3D transistor architectures, redefining future needs for lithographic, defect, and films metrology solutions for high-volume manufacturing. Future 3D memory devices will include multiple gate-level structures defined by high aspect ratio (HAR) trenches and holes in multilayer stacks, which are major gaps in current metrology technology. No in-line non-destructive metrologies have achieved the sensitivity and resolution to image or measure CD, depth, profile, or contamination of such HAR features [1]. In addition, defect metrology inspection and review suffer from low sensitivity and inadequate throughput even for current 22nm defects of interest. To address these challenges, a robust metrology strategy should encompass the extendibility of conventional techniques that are approaching their fundamental limits, as well as development of new technologies.

Memory producers are migrating beyond planar designs to build multiple levels of gates into 3D structures. These vertical architectures lead to new challenges in semiconductor processing technology [7]. As shown in Figure 2, the basic building blocks of these features are deep, HAR trenches and holes in oxide, silicon, or multiple alternating layers of oxide and silicon.

Figure 2. Left: Diagram of pipe-shaped bit cost scalable (P-BiCS) flash memory cell, which consists of pipe-shaped NAND strings folded in a U shape. This is an example of the types of 3D memory devices that will require HVM metrology. Right: Diagram of various measurement needs on such a structure.
Figure 2. Left: Diagram of pipe-shaped bit cost scalable (P-BiCS) flash memory cell, which consists of pipe-shaped NAND strings folded in a U shape. This is an example of the types of 3D memory devices that will require HVM metrology. Right: Diagram of various measurement needs on such a structure.

3D memory structures present many metrology challenges due to their HAR characteristics. HAR contact holes and trenches at ITRS half-pitch dimensions are known gaps in CD and profile metrology; these same measurement limitations have, to some extent, already been apparent with etched contact holes and shallow trench isolation (STI) trenches in logic for recent ITRS nodes. Furthermore, the problem is increasing with shrinking dimensions. HAR etching is difficult, with 30:1, 40:1, or even 60:1 ARs necessary to form a vertical circuit path among stacked gates.

Process control of the bottom of the CD, profile, and detection of polymeric etch residues is required for HVM. While TSVs may have a similar or higher AR, they are comparatively huge — 3D memory device features will include hole and trench structures with bottom CD sizes at ITRS node dimensions [8], from 0.5 to 2µm deep. This introduces an entirely new set of gaps in metrology capability as the quest for non-destructive measurements of such features has yet to achieve the necessary sensitivity and resolution. Moreover, the physics of these measurements is incompatible with the extremely deep and geometrically confined volumes involved.

Charged particle imaging techniques such as CD-SEM and helium ion microscopy (HeIM) [9] have sensitivity limitations arising from sidewall charging, as only a small fraction of scattered particles follow escape trajectories that reaches the detector. Many optical techniques, especially those that operate off-axis near the critical angle, suffer from a very small fraction of the interrogating light reaching the feature bottom, and reflect upwards to the detector. Thus, in most cases, the various metrology techniques in their present forms will suffer low signal-to-noise ratios (SNRs) on such features.

Many technologies are being explored at SEMATECH to enable HVM of HAR features, including new technologies such as critical dimension small angle X-ray spectroscopy (CD-SAXS) [3], HeIM [9], and through focus scanning optical microscopy (TSOM) [10] and variations of existing technologies, such as Mueller matrix [2] and normal incidence scatterometry (polarized reflectometry), model-based infrared reflectometry (MBIR), high voltage SEM (HV-SEM) [11], environmental SEM (e-SEM) [12], and conventional low-voltage CD-SEM. Results are still forthcoming, but CD-SAXS and scatterometry at normal incidence, MBIR, and HV-SEM may have some capability in this application space. CD-SAXS is currently a lab technique, but X-ray sources with higher brightness offer possibilities for transforming this technique into a feasible HVM metrology tool. MBIR takes advantage of the transparency of the various applicable materials to infrared and thus may have sensitivity to some feature aspects. HV-SEM is being demonstrated as useful in providing the capability to charge HAR holes in such a way that reflected incident or secondary electrons can more easily escape the bottom of the feature. Normal incidence scatterometry may be feasible as more incident light can reach the bottom for potentially improved SNR.

Conclusion, Part 2
Adaptation to new tool paradigms, enhancements of existing technologies, and productivity innovations will be critical to maintain process control and high yield in the coming technology generations. The SEMATECH Advanced Metrology Program is well positioned to develop solutions to address the measurement challenges of next generation devices.

Miss Part 1 on FinFET metrology? Read it here.

Move on to Part 3 on new defect detection technologies here.

References

[1] Doyle, B. et al., “Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout,” Symposium on VLSl Technology Digest of Technical Papers, pp. 133-134 (2003).

[2] Vaid, A., et al. “A holistic metrology approach: hybrid metrology utilizing scatterometry, CD-AFM, and CD-SEM.” Metrology, Inspection, and Process Control for Microlithography XXV. Proceedings of the SPIE, Volume 7971, pp. 797103-797103-20 (2011).

[3] Wang, C., Choi, K., Chen, Y. Price, J., Ho, D., Jones, R., Soles, C., Lin, E., Wu, W.L., Bunday, B. “Nonplanar high-k dielectric thickness measurements using CD-SAXS.” Proc. SPIE, v. 7272, pp 72722M (2009).

[4] De Martino, A., et al., “Comparison of Spectroscopic Mueller Polarimetry, Standard Scatterometry and Real Space Imaging Techniques (SEM and 3D-AFM) for Dimensional Characterization of Periodic Structures,” Proc. of SPIE Vol. 6922, 69221P (2008).

[5] Larson, D.J., and Kelly, T. F., “Nanoscale Analysis of Materials using a Local-Electrode Atom Probe,” Microscopy and Microanalysis Volume: 20, Issue: 3, pp: 59-62 (2006).

[6] Mody, J. et al., “Dopant and Carrier Profiling in FinFET-Based Devices with Sub-Nanometer Resolution,” 2010 Symposium on VLSI Technology, pp. 155-156

Abraham Arceo is a metrology development engineer at SEMATECH Advanced Metrology group. For the past three years he has been involved in film and defect inspection metrology development.

Benjamin Bunday is the project manager of CD Metrology and a Senior Member Technical Staff at SEMATECH (Albany, NY, USA). For ten years he has led SEMATECH/ISMI’s CD-SEM and OCD benchmarking, advanced CD technology evaluation and development efforts, and SEMATECH’s Advanced CD Metrology Advisory Group (AMAG).

Aaron Cordes is a research engineer for Sematech in Albany doing work on AFM, TEM, and focused ion beam metrology. He is also a PhD student with SUNY Albany’s College of Nanoscale Science and Engineering.

Victor Vartanian is a metrology engineer at SEMATECH in Albany, New York. Before coming to SEMATECH, he worked at Freescale Semiconductor in Austin, Texas, where he worked on applications of strained silicon to advanced transistor design and analytical applications of FTIR and mass spectrometry to environmental issues in semiconductor manufacturing and in process optimization.

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February 14, 2012 — The ConFab, an invitation-only global conference and networking event for semiconductor industry executives, announces that Ali Sebt, CEO of Renesas Electronics America, will provide the keynote on the second day of the conference.

In his talk titled "Smart Society, the Sensing Era and Signal Chain," Sebt will address how we as an industry need to support this smart society and help it grow by focusing on the complete signal chain – from analog to digital to low power to the software intelligence – to develop connected, low-power-foundation devices that will shape the next generation of connectivity for a smarter world. 

The first keynote, previously announced, will come from Dr. John Chen, vice president of technology and foundry operations at Nvidia. In a talk titled "The Next Transformation of the Semiconductor Industry," Chen will present the concept of "virtual IDM" as a way for foundries, fabless and OSATs to collaborate to solve the new challenges in technology, manufacturing and business.

The ConFab is announcing a number of confirmed speakers, including: Jackie Sturm, vice president of Intel’s Technology and Manufacturing Group and general manager of Worldwide Materials; An Steegen, senior vice-president, process technology, imec,; Tom Jefferson, ISMI; David McCann, senior director, technical business operations at Global Foundries; Mike Barrow, EVP and COO, International Rectifier; Dan Hutcheson, CEO and chairman of VLSI Research; and Jim Feldhan, president of Semico. The ConFab also welcomes the latest addition to the conference advisory board, Richard Young, vice president of manufacturing at SEMATECH.

The conference, which will be held June 3-6, 2012, is moving to at a new venue, The Encore at the Wynn Las Vegas. The ConFab is operated by PennWell Corp., a diversified global media and information company, and is the primary event produced by Solid State Technology, the leading global information source on semiconductor manufacturing.

The ConFab also welcomes the industry association SEMI, which has again agreed to sponsor
The ConFab, continuing the first-year agreement in 2011. Other confirmed sponsors to-date include: Advantest, AG Semiconductor, Applied Materials, ATMI, AZ Electronic Materials, Brewer Science, EV Group, KLA-Tencor, Hitachi, Lam Research, Levitronix, Nikon, Novellus, Pall Corporation,
Qcept Technologies,  Rudolph Technologies, RED Equipment, Tokyo Electron, Ulvac and Valqua.

With the addition of Richard Young of SEMATECH, The ConFab advisory board now includes:
David Bennett, VP Alliances, GLOBALFOUNDRIES; Janice Golda, Director Lithography Capital Equipment Development, Intel; Abraham Yee, Director Advanced Technology & Package Development, Nvidia Corp; Sima Salamati, President, ZYadS Inc., Engineering and Manufacturing Consulting (Retired Texas Instruments Fab and Test manager); Paul Farrar, VP, Albany Expansion and Strategic Initiatives, IBM Corporation; Hans Stork, CTO, ON Semiconductor; Geoffrey Yeap,
VP of Technology, Qualcomm Inc.; Lori Nye, COO/Executive Director Customer Operations,
Brewer Science; Paul Edstrom, consultant (formerly CTO GE Commercial Finance); John Lin, Director of Mfg Technology Center, Taiwan Semiconductor Manufacturing Company, Ltd.;
Ken Rygler, President, Rygler & Associates (founder of Toppan Photomasks); Takeshi Hattori, President, Hattori Consulting International; Bill Tobey, President, ACT International; Tom Jefferson, ISMI, and Pete Singer, Editor-in-Chief, Solid State Technology.

"We’re delighted to have Ali Sebt and so many other excellent speakers confirmed to speak at The ConFab in 2012," said Pete Singer, Conference Chairman and Editor-in-Chief of Solid State Technology. "The semiconductor industry is in an interesting phase of solid growth as electronic products of all types continue to proliferate, combined with uncertainty about the world economy,
the impact of consolidation, and the ever-higher costs of R&D. It’s great to have so many industry leaders willing to attend The ConFab and provide their insights into what lies ahead."

The ConFab 2012 will continue the conference’s traditional focus on the economics of semiconductor manufacturing, and associated industries such as LEDs, MEMS and displays. Attendees will hear about:

  • The outlook for 2012 and 2013.
  • Technical challenges facing the industry, including next generation lithography, the
    450mm wafer transition, 3D integration, and the advanced packaging and testing of increasingly complex chips.
  • Opportunities to maximize collaborative efforts between fabless companies, foundries, OSATs, and equipment and materials suppliers.
  • The opportunities of high growth markets such as MEMS, LEDs, flexible displays and
    energy storage.

Entering its eighth year, The ConFab (www.theconfab.com) is an exclusive invitation-only global conference and business meeting where executives from semiconductor equipment and material suppliers can meet with key decision makers from manufacturers of semiconductors, LEDs, MEMS and other types of electronics. At The ConFab, these executives discuss business and technology issues and collaborate on future strategic development in device manufacturing. Ample time is available for private face-to-face meetings between equipment and material suppliers and manufacturers. Attendance is by invitation only and attendees are pre-screened to verify that they are key participants in the buying process.

Interested in attending The ConFab? If you are a senior-level decision maker from a semiconductor manufacturing or fabless company, contact Luba Hrynyk to find out if you qualify to attend as our complimentary VIP guest.

For sponsorship information, please contact Sabrina Straub ([email protected]).

Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies based in Research Triangle Park, N.C., is adding three members to the global Energy Research Initiative (ERI) that focuses on new technologies for renewable energy and its efficient and reliable distribution on the power grid. The addition of Hydro One Networks, NEC and ON Semiconductor brings the recently created ERI to 10 members and expands the team’s focus to include finding new materials, devices and methodologies for power controls/management and energy collection, conversion and storage.

ERI’s goal is to address the world’s need for smart alternative energy sources and prepare students with the technical skills required for the growing industry. ERI’s approach is to create and leverage university research centers to address the specific energy research needs of its industry members.

Joining with ERI charter members ABB, Applied Materials, Bosch, First Solar, IBM, Nexans and Tokyo Electron, the three new member companies also will collaborate with selected universities to conduct the industry-specified research.

“It’s a rare advantage for research to enjoy such a diverse range of international expertise as these 10 members of the ERI represent,” said SRC Executive Vice President Steven Hillenius. “We recognize that the scope of what’s required to integrate renewable energy with the smart grid most efficiently is more than what any one company or industry can achieve. By applying its world-class individual and collective strengths, this team of industry and academia should generate far-reaching benefits for global energy use.”

Started in 2010, the ERI focused initially on two critical areas for efficient distribution of renewable energy resources – photovoltaics (PV) and systems and technologies to enable and optimize smart grids. Two centers for ERI research were established at Purdue and Carnegie Mellon universities to work with the industry to produce new findings for commercial applications to photovoltaics (PV) and smart grid.

The new, third center designated to drive advances in power electronics and energy storage will leverage existing centers of excellence in these critical areas and also include researchers from other universities worldwide. As planned, advancements from the current ERI centers in PV and smart grid will be integrated with results from the new center in power electronics and energy storage to provide efficient and affordable solutions for power generation, distribution and use from renewable energy systems.

Among critical elements of the combined effort, the ERI team is creating modeling and simulation tools to support the development of improved photovoltaic devices. They also are developing systems and technologies that will enable an efficient, reliable and secure smart grid electricity infrastructure with integrated renewable energy resources.

In addition to chip manufacturers and energy-related companies, several other industries could also gain greater product effectiveness from related research into ERI’s areas of expertise. These discoveries and their applications ultimately should allow for the realization of a cleaner, more affordable energy network for the planet.

In support of the ERI mission, the third center of research excellence, the Power Electronics and Energy Storage Center, is expected to begin work this spring. Key overarching technical challenges addressed by the center will be:

·         Development of solid state devices with high-voltage/current handling capabilities;

·         Bi-directional power electronics for interfacing, control and stabilization of intermittent renewable energy, including PV at the home/office and smart grid; and

·         Improved performance and lower cost methods for controlling parallel groups of energy storage cells (potential application of wireless sensors), optimized charge/release functions with the grid and dynamic Volt-Var support including optimization of battery charging efficiency and battery life.

ERI is managed by the SRC subsidiary, Energy Research Corp, which was formed in 2009 to create opportunities between the semiconductor industry and energy sector.

February 13, 2012 — After 5 straight months of steep declines, prices for large-sized liquid crystal display (LCD) panels stabilized in December 2011, thanks to better-than expected sales and decreased production, according to an IHS iSuppli LCD PriceTrak report.

Global pricing for average large-sized LCD panels decreased by just 0.1% in December. This slight reduction indicates market pricing is steadying out compared to the 0.5% drop incurred in November and the runaway 3 or 4% contractions regularly seen during most of H2 2011.

The last time that panel pricing came close to December’s minimal level of decrease occurred during a two-month span during May and June 2011, when pricing retreated by 0.2% per month.

Figure. Large-size LCD panel prices.

December’s panel price also showed the smallest month-to-month change in all of the prior 12 months, as shown in the figure.

The overall pricing for large-sized LCD panels reflects the average taken among the three major markets for the panels, i.e., for televisions, monitors and notebooks. Large-sized panels are defined as those having a diagonal dimension of 10.4 to 55" and above.

Also read: Rapid LCD TV shift to 40"+ display panels signals production capacity boost

“The firming in panel prices in December can be attributed to lean inventories throughout the supply chain and to lower factory utilization rates, after suppliers were forced to cut production in order to control supply and stem financial losses,” said Sweta Dash, senior director for LCDs at IHS. “Sales also picked up in the United States and China, helping to further boost the market. Despite this, there will be little opportunity for suppliers to increase pricing even after the market has evened out, due to continuing uncertainties in the global economy. Chinese demand also is expected to decline after the Lunar New Year sales season in January, preventing prices from increasing.”

Large-sized LCD fab capacity utilization was running at 78% in December compared to 86% a year earlier. This reduced available supply, slowing the rate of price declines during the month.

Among the individual large-sized LCD applications, prices for television panels fell 0.2% in December compared to a 0.6% contraction in November. TV panel prices, however, are expected to remain flat in the first quarter of 2012.

Global television inventories in the worldwide retail channel reached a four-to five-week low in January after robust sales during the holidays in the United States and the Lunar New Year holiday in China. This development may cause some brands to build up inventory for future months as well as to stockpile supply for new model introductions. In particular, many new TV sizes — such as 39" and 50" panels — are expected to be introduced. Brands also are exploring 60-inch-and-larger sizes for the niche market, after the sizes proved successful during holiday sales.

Overall, TV panel inventories have declined to less than 25 days, compared to their usual 30-day average. Moving forward, LCD TV panel production will be lower in the first quarter because of the Lunar New Year holidays observed in the Asian manufacturing zones where the panels are made, as well as the shorter month in February.

In comparison to the TV space, panel pricing was down 0.1% in December for the monitor and notebook segments, which individually had fallen 0.2% the month before.

For the desktop PC monitor area, corporate demand remains weak because of prevailing economic caution in the business and enterprise world. Meanwhile, mobile products like tablets, ereaders and notebooks grabbed more sales among consumers than monitors did during the recent Christmas holiday sales. Overall growth in 2012 remains uncertain for the area.

In the notebook PC segment, the October flooding in Thailand is likely to impact production into early 2012, affecting panels being purchased for notebooks in the process. As a result, brands will continue to adjust inventory and pricing in channels, given the shaky outlook here for some time to come.

Increasingly, capacity for notebook and monitor panel production is being shared with that for TV.

Also, more large-sized LCD capacity is being shifted toward tablet applications due to the success of devices like Apple Inc.’s iPad, leading to adjustments in production throughout the chain.

Access the report, Large-LCD Panel Price Stabilized in December After Five Months of Decline, at http://www.isuppli.com/Display-Materials-and-Systems/Pages/Large-LCD-Panel-Price-Stabilized-in-December-After-Five-Months-of-Decline.aspx?PRX

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