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SiC manufacturing: Patents donât equal revenue/market share, and watch for challengers to PVT growth

July 24, 2012

July 24, 2012 — Silicon carbide (SiC) is a niche material for semiconductor, power electronics, and light-emitting diode (LED) manufacturing. Yole Développement analyzed patents related to SiC growth and wafer manufacturing to glean trends in production, R&D, top companies, barriers to entry, and more.

Despite a cumulative raw wafers + epi wafers market that won’t exceed $80 million in 2012, SiC-related patents comprises over 1772 patent families with more than 350 companies involved in the material since 1928. 83% of patents cover a method; 17% of them claim an apparatus.

Figure. SiC crystal, wafer, and epiwafer patents distribution. SOURCE: Yole, July 2012.

SiC growth

Since 1978, the main technique to grow bulk single crystals of SiC has been physical vapor transport (seeded sublimation method, PVT), covered in 36% of published patents, said Dr. Philippe Roussel, business unit manager, Compound Semiconductors, Power Electronics, LED & Photovoltaics, Yole Développement. PVT mostly deals with the hexagonal polytypenH SiC (n=2,4,6). Liquid phase epitaxy (LPE), an alternative SiC growth method developed in 1961, allows crystals to grow with low dislocation densities and at relatively low temperatures. LPE is an attractive SiC growth method for cubic polytype 3C SiC.

Chemical vapor deposition (CVD) almost exclusively dominates SiC epiwafer fab today, and is covered in about 37% of SiC-related patents. Molecular beam epitaxy (MBE) is only mentioned in 1% of patents. The polytype (hexagonal or cubic) is explicitly claimed in 15% of patents.

Numerous strategies to reduce crystal defects (micropipes, carrots, etc.) and make semi-insulating (SI) material are proposed in 23% and 10% of patents respectively.

Patent count vs revenues

About 350 patent applicants are involved in SiC crystal/epiwafer technology, pointed out Roussel, mainly located in Japan (72% of patents) and the US (12% of patents). The five major applicants based on their patents number are Denso, Sumitomo, Nippon Steel, Bridgestone and Toyota. They represent about 35% of studied patents. While Cree Inc. is the 6th major applicant for patents by volume, and the top US company on the list, US companies generate 75% of the SiC wafer business. Leaders include CREE, II-VI, and Dow Corning. Japan is only responsible for 5% of the revenues (at least before SiCrystal was acquired by Rohm). This trend of poor correlation between patent count and revenues is seen in Europe and the rest of Asia as well.

Only 3 Japanese companies are commercially active in SiC material: Showa Denko (epiwafer), Bridgestone (wafer) and Nippon Steel (wafer and epiwafer). China and Korea emerged as new players during the last 5 years, establishing Epiworld, TianYue, TYSTC, and Tankeblue in China and SKC in Korea. However, these companies’ market shares remain very low at the moment.

In the SiC substrate business, Cree holds about 50% market share on a worldwide basis, and has the best reputation in terms of quality, diameter and reproducibility. However, here again Cree does not own the widest patent portfolio.

The only SiC field where number of patents and business size are more balanced is SI SiC technology, where both Cree (vanadium-free) and II-VI (vanadium-doped) have extensively patented their respective developments.

Today’s SiC landscape

Today’s state-of-the-art SiC wafer is 6” diameter, no micropipe, with very low dislocation density. Only CREE seems able to offer such a product today. Barriers to entry and competition in the SiC arena are high, Yole points out.

Cree enjoys funding from the US Department of Defense (DOD), Department of Energy (DOE), Defense Advanced Research Projects Agency (DARPA), and the US Navy, improving its technology for LEDs and power electronics. Cree also likely benefits from cross-fertilization of technologies between LEDs and power electronics.

Virtually no SiC substrate companies are for sale today. Beyond the top 5 SiC substrate leaders, Yole does not see a clear positioning of companies who may want to participate in a sale or merger of their business.

New developments are being made around LPE at Toyota, Denso, and Sumitomo. 3C SiC (Cubic) may also disrupt the current PVT domination.

Report

“Patent analysis of SiC single crystal, wafer and epiwafer manufacturing” from Yole Développement presents the patent landscape for SiC single crystal and epiwafer over a total of 1772 patent families. Several key patents are selected based upon their interest regarding the particular technological issues related to the SiC development, as well as their possible blocking factor for new competing development. It puts in contrast the patent landscape with the current and expected market status, highlighting the most active companies, the patent transfer and the sleeping IP. The document also highlights and describes the key patents that could possibly block newcomers, for both crystal and epi-growth.

The analysis goes along with spreadsheets presenting the 1772 patents (Publication Number, Publication Date, Priority Date, Title, Abstract, Assignee(s) and Inventor(s), Legal Status) with direct link to the full patent text and pictures.

Report author: Philippe Roussel holds a PhD in Integrated Electronics Systems from the National Institute of Applied Sciences (INSA) in LYON. He leads the Compound Semiconductors, LED, Power Electronics and Photovoltaic department at Yole Développement.

Companies cited in this analysis: ABB, ACREO, AIST, Ascatron, ATMI, Bridgestone, C9 Corporation, Cabot, Cree, Crysband, Denso, Dow Corning, Ecotron, Epiworld, Fuji Electric, Fujimi, Fujitsu, Hitachi, Hoya, II-VI, Infineon, Kansai Electric Power, Kwansei Gakuin Univ., Mitsubishi, Mitsui, NASA, National Tsing Hua Univ., N-Crystals, NEC, NeoSemitech, Nippon Pillar Packing, Nippon Steel, NIRO, Nisshin Steel, Norstel, North Carolina Univ., Northrop Grumann, NovaSiC, Okmetic, Panasonic, POSCO, Rohm, Sanyo, SemiSouth, Sharp, Shikusuon, Shinetsu Chemical, Showa Denko, SiC Systems, SiCilab, SiCrystal, Siemens, Sumitomo Metal Industries, TankeBlue, Toshiba, Toyota, TyanYue, TYSTC, United Silicon Carbide, US Navy, Widetronix, etc.

Yole Développement is a group of companies providing market research, technology analysis, strategy consulting, media in addition to finance services. Learn more at www.yole.fr.

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Real-time monitoring slashes water and energy usage in semiconductor manufacturing on 300mm and 450mm wafers

July 23, 2012

July 23, 2012 — Researchers sponsored by Semiconductor Research Corporation (SRC), a leading university-research consortium for semiconductors and related technologies, developed new sensor-based metrology technology that can significantly reduce water and related energy usage during semiconductor manufacturing.

The sensor-based real-time monitoring approach showed 30% less water and energy used for ultra-clean chip production. The SRC Engineering Research Center (ERC) for Environmentally Benign Semiconductor Manufacturing team at the University of Arizona (UA) calls this “the most significant metrology improvements for the rinse and cleaning of wafers in more than a decade.”

Figure. In-situ monitors provide unprecedented control of water and chemical usage during surface preparation for silicon wafers. Highly sensitive sensors, like those shown in this micrograph of a sensing channel, can reduce the amount of resources needed for the cleaning of surfaces.

Surface preparation, when semiconductor wafers are cleaned, rinsed, and dried to prevent defects between various front end of line and back end of line (FEOL/BEOL) steps, is one of the largest water-consuming processes in semiconductor manufacturing. The International Technology Roadmap for Semiconductors (ITRS) identifies lower resource utilization at current and future fabrication steps among its goals.

Also read: Semiconductor fabs use significantly less energy today, but work remains from ISMI.

The ERC team’s real-time monitoring approach is applicable to current cleaning processes for 300mm silicon wafers, and the gain is expected to be especially beneficial when the industry transitions to 450mm wafers. At 450mm, chipmakers will need to clean and prep a wafer surface that is more than twice the size of current state-of-art wafers.

Current surface preparation practices are recipe-based and not controlled with real-time, in-line monitoring of the process steps. Surface prep is carried out without feedback or control, with a large cushion of safety to overcome lack of regulation. This sizeable safety factor creates unnecessary waste of chemicals, water and energy.

“The challenge is how to balance a minimal application of precious resources with the grave risk of allowing contamination to occur, which can kill huge investments made elsewhere in the fabrication process,” said Dr. Steve Hillenius, executive vice president for SRC.

The next step is to commercialize the monitoring technology, said Farhang Shadman, lead researcher and the ERC director at UA for the SRC-funded research. Semiconductor equipment and manufacturing companies, as well as other industries that use ultra-clean for planar or patterned surfaces and small structures could use the real-time metrology technology to improve resource management. Examples include optics, optoelectronics, and flat panel display (FPD) makers.

For more information about the research, please visit http://dx.doi.org/10.1109/TSM.2010.2089542. Contributors for the joint effort include K. Dhane, J. Han, J. Yan, O. Mahdavi, D. Zamani, B. Vermeire and F. Shadman.

SRC defines industry needs, invests in and manages the research that gives its members a competitive advantage in the dynamic global marketplace. For more information, visit www.src.org.

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North American semiconductor fab tool book-to-bill drops below parity in June

July 20, 2012

July 20, 2012 — North America-based manufacturers of semiconductor equipment posted $1.46 billion in orders, $1.55 billion in bookings, and a book-to-bill ratio of 0.94 worldwide in June 2012 (three-month average basis), reported SEMI. This is the first time the book-to-bill has dropped below parity (1.00) since January 2012.

The three-month average of worldwide bookings in June 2012 was $1.46 billion. The bookings figure is 9.8 percent lower than the final May 2012 level of $1.61 billion, and is 5.5 percent lower than the June 2011 order level of $1.54 billion.

The three-month average of worldwide billings in June 2012 was $1.55 billion. The billings figure is 1.0 percent more than the final May 2012 level of $1.54 billion, and is 5.2 percent less than the June 2011 billings level of $1.64 billion.

"Following seven months of increases, the three-month average bookings declined in June and likely reflects some slowing in investment plans attributed to weaknesses in the broader economy," said Denny McGuirk, president and CEO of SEMI. "While order activity may slow, equipment spending this year will continue to be directed towards advanced technologies in wafer processing and packaging assembly."

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars. A book-to-bill of 0.94 means that $94 worth of orders were received for every $100 of product billed for the month.

	Billings (3-mo. avg)	Bookings (3-mo. avg)	Book-to- Bill

Jan 2012	1,239.9	1,187.5	0.96
Feb 2012	1,322.8	1,336.9	1.01
March 2012	1,287.6	1,445.7	1.12
April 2012	1,458.7	1,602.8	1.10
May 2012 (final)	1,539.3	1,613.7	1.05
June 2012 (prelim)	1,554.9	1,455.6	0.94

Source: SEMI July 2012

The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

The data are contained in a monthly Book-to-Bill Report published by SEMI. The report tracks billings and bookings worldwide of North American-headquartered manufacturers of equipment used to manufacture semiconductor devices, not billings and bookings of the chips themselves. The Book-to-Bill report is one of three reports included with the Equipment Market Data Subscription (EMDS). SEMI is a global industry association serving the nano- and micro-electronic manufacturing supply chains. For more information, visit www.semi.org.

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Major semiconductor players increase capex in 2012, total capex falls 3%

July 18, 2012

July 18, 2012 — IC Insights’ latest survey and ranking of the major semiconductor capital spenders shows that only 6 of the 35 major semiconductor suppliers — Intel, Samsung, Hynix, TSMC, UMC, and Rohm — with significant capital expenditure budgets are expected to spend more in 2012 than they did in 2011.

Though only six companies are expected to increase their capital spending this year, the total semiconductor capital spending forecast figure for 2012 was raised to $63.3 billion from an earlier estimate of $60.7 billion; total 2012 semiconductor industry capital expenditures are now forecast to decline only 3% this year as compared to the previous expectations of an 8% decline.

Table 1. Major capital spenders planning 2012 increases in capex. SOURCE: IC Insights, company reports.

2012F	Company	2011 ($M)	2012F ($M)	12/11 change (%)
1	Intel	10,764	12,500	16
2	Samsung	11,755	13,100	11
3	TSMC	7,333	8,250	13
4	Hynix	3,165	3,680	16
5	UMC	1,585	2,000	26
6	Rohm	385	685	78
—	Total	34,987	40,215	15
—	Others	30,568	23,055	-25
—	WW Total	65,555	63,270	-3

The six major companies that plan to increase semiconductor capital spending this year are expected to collectively spend about $5.2 billion more in 2012 than in 2011. In contrast, the total of the remaining capital spending outlays are forecast to decline by about $7.5 billion this year.

With an increase of $1.7 billion, Intel is expected to post the biggest dollar increase in capex spending for 2012, though it is likely to trail Samsung in overall capex spending for the year.

A few of the major outsourced semiconductor assembly and test (OSAT) companies also plan to significantly increase capital spending this year. IC Insights believes that these increased spending budgets by some of the major OSAT companies indicates their belief that semiconductor unit volume shipments will be on the rebound this year.

Table 2. Major capital spenders in the OSAT sector planning 2012 capex increases. SOURCE: IC Insights, company reports.

Company	2011 ($M)	2012F ($M)	12/11 change (%)
Amkor	493	550	12
SPIL	376	585	56
STATS ChipPAC	304	400	32
Total	1,173	1,535	31

IC Insights will examine and provide further details on semiconductor capital spending in its 250+ page Mid-Year Update to The McClean Report, scheduled for release at the end of July. To review additional information about IC Insights’ new and existing market research products and services, visit: www.icinsights.com.

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MEMS oscillators: Better alternative to crystal oscillators?

July 17, 2012

July 16, 2012 — Since the early 19^th century, quartz crystals have been the core frequency reference for oscillators. However, due to the manufacturing complexity and reliability challenges posed by crystal oscillators, a great deal of work is going on in the industry and academia to find alternate frequency reference solutions. To overcome the known technical challenges for quartz crystals, including limitations on higher native frequencies, activity dips, aging, vibration sensitivity, etc., IDT recently introduced piezoelectric micro electro mechanical system (pMEMS) resonator-based oscillators. pMEMS resonators have a higher native frequency (~100 MHz) than quartz crystals and enable better-performing MEMS oscillators (sub-ps jitter), especially for high-performance communications, consumer, cloud, and industrial applications.

As part of higher reliability over quartz, MEMS oscillators demonstrate semiconductor-grade shock and vibration resistance. Standard quartz devices are fragile, since the crystal is housed within a metal or a ceramic package, allowing the crystal to be fractured by a shock of 50-100g. Manufacturers have to implement specific storage, packing, and shipping protocol for crystal devices to avoid damage. MEMS oscillators, on the other hand, sport a 50,000g shock resistance without special construction, packaging, and transportation techniques.

Figure 1. Wafer level packaged pMEMS die stacked on an IC Die in a plastic QFN package.

Figure 2. A typical quartz oscillator in a ceramic package.

Since the MEMS resonators are wafer-level packaged, these oscillators can use low-cost plastic packages, which provide an economical yet reliable timing component.

Another known issue for crystal oscillators — activity dips — can cause intermittent failures. These failures affect both the frequency and the resistance (i.e., the Q) of crystal resonators. Activity dips are usually caused by interfering modes (e.g., by high overtone flexure modes) and are strongly influenced by the crystal’s drive level and load reactance. These activity dips are not present with MEMS oscillators since the resonators are designed to suppress undesired modes over these temperature and process variations that can impair crystal-based oscillators.

pMEMS oscillators have also demonstrated aging comparable with crystal oscillators at room temperature (25°C) and significantly better aging than crystal oscillators under burn-in conditions (125°C).

Other advantages of MEMS-based products include natural compatibility with surface-mount assembly processes and short lead times; this enables suppliers and users (electronic manufacturers) to maintain a smaller device inventory with reduced risk of supply shortages.

IDT’s MEMS oscillators support low-voltage differential signaling (LVDS) and low-voltage positive emitter-coupled logic (LVPECL) outputs at frequencies of up to 625MHz, which is required in most communications, networking and high-performance computing applications.

Conclusion

There have been a lot of improvements in MEMS oscillators over the years, and the recent upgraded products, like IDT’s 4M MEMS oscillators, are ready to provide the performance and accuracy required in the high-performance communications, consumer, cloud computing, and industrial applications. In the foreseeable future, researchers, designers, an Harmeet Bhugra, managing director, Integrated Device Technology Inc. d manufacturers will continue to work together to enhance the MEMS oscillators to deliver more accurate, cost-effective, and higher performance frequency reference products.

Harmeet Bhugra, managing director, Integrated Device Technology Inc., is responsible for the vision, growth and general management of the MEMS business. Bhugra holds a Bachelor of Engineering degree from University of Victoria, Canada, Masters in Systems Engineering and MBA degrees (Magna Cum Laude) from San Jose State University and Managing Technical Organization certifications from MIT.

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SEMICON West takeaways: Seasonality over cyclicality, lithography and test trends

July 16, 2012

July 16, 2012 — SEMICON West kicked off with a surprise announcement regarding Intel’s strategic investment into ASML, but generally the event highlighted trends “as expected” in the semiconductor manufacturing supply chain, say Barclays Capital analysts.

Most semiconductor production equipment makers are seeing an order/shipment pull-back in Q3. Rising capital intensity, chip manufacturing complexities, Intel’s march to 14nm, and foundry’s 20nm investments contribute toward Q4 and 2013 capex optimism. Barclays investigates this trend further in Q3 semiconductor tool capex pull-back: Seasonal, expect Q4 uptick

Seasonality is now indeed winning over cyclicality, with Q3 drifting into a lull as it did in 2011 and 2010. Consensus estimates clearly are going to move lower given the cautious tone and the expectations for a near term pause in order.

Barclays is maintaining its wafer fab equipment capex estimate for 2012 at $31.5 billion (flattish over 2011) and for 2013 at $31.5 billion to 34.5 billion (flat to +10% over 2012).

Barclays is also keeping its lithography tool forecast for 2012 intact: immersion lithography demand is holding up with the lack of extreme ultraviolet (EUV) availability. Expect KrF lithography spending to taper in H2 2012.

SOC test is also going to taper in H2, but still tracking to be about $2.6 billion capex in 2012.

The surprise 450mm/EUV lithography tie up between ASML and Intel made a splash at SEMICON West. According to Bloomberg, sources reported that Samsung Electronics Co., Ltd. and TSMC are in talks to acquire about 10% stake in ASML as well. Look for more analysis on blogger Dick James’ page, in The Elephant Has Left the Room — 450 mm is a Go!

Intel continues to be the main driver of 450mm adoption, which could benefit more than ASML (look for Edwards Vacuum to also support the 450mm transisiton at Intel sometime in the 2018/2019 timeframe).

Cymer continues to the leader within the group of lithography light-source contenders, with Extreme/Ushio still experiencing reliability issues with its IMEC source and Gigaphoton yet to assemble an integrated source, Barclays concludes.

Read the full report at http://live.barcap.com/PRC/servlets/dv.search?contentPubID=FC1838914&bcllink=decode

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2012 ITRS update: Back-end packaging and MEMS

July 13, 2012

July 13, 2012 — At SEMICON West 2012, this week in San Francisco, CA, the working groups of the International Technology Roadmap for Semiconductors (ITRS) held 3 sessions (TechXPOTs) outlining 2012 updates to the roadmap. Check out the updates to the front-end, scaling roadmap working groups here.

The ITRS undergoes major revisions on odd-numbered years. 2012 being an even-numbered year, very little change occurred to the Overall Roadmap Technology Characteristics (ORTC). However, within the working groups, some updates were worth noting.

Also read: 2011 ITRS: DRAM, 3D Flash, MEMS, nano-scaling steal the show

First, the changes to the ORTC, presented at the TechXPOT by Bob Doering. Of interest were changes focused directly or indirectly on 450mm. ITRS has moved the forecast production start date to 2015-2016. The definition of

Interviews with CEA-Leti researchers at SEMICON West

July 12, 2012

July 12, 2012 — CEA-Leti co-located its research updates presentation with SEMICON West 2012 in San Francisco, CA, this week. After the talks on device architecture, 3D and 2.5 packaging interconnects, large-scale computing and power consumption, and more, CEA-Leti’s researchers joined Solid State Technology’s digital media editor Meredith Courtemanche to talk about their fields of interest.

Also read: Semicon West Day 1: FDSOI and TSV R&D with CEA-Leti by blogger Michael A. Fury, PhD.

Check out the videos for details on the research:

Hughes Metras, VP of strategic partnerships in North America, presented on cost and energy consumption in large-scale computing, and what technical innovations will meet the industry’s needs. Energy efficiency must improve at the circuit, interconnect, and system level, he said.

Silicon photonics waveguides are one way to significantly increase bandwidth in semiconductors. CEA-Leti is migrating to a 300mm Si photonics line in its research work. Laurent Fulbert, Integrated Photonics Program Manager at CEA-Leti, presented on the question of low-cost/low-power computing architectures, and the answers available in photonics.

Maud Vinet, LETI FDSOI Manager, IBM Alliance, shared the benefits of fully depleted silicon on insulator (FDSOI) transistor architecture. The performance? Excellent parasitic capacitance resistance because of the smaller gate length than bulk CMOS. The energy efficiency? Back bias allows tuning of the devices’ threshold voltage to reduce wasted power. (We cover energy efficiency of new transistors/interconnects in more detail here.) The manufacturing parameters? Easier than a FinFET, Vinet says, as the majority of processes are the same as today’s semiconductor fab methods. The one challenge is potential silicon loss, because planar FDSOI uses thin Si films on the order of a few nanometers.

Mark Scannell and Denis Dutoit both lead 3D interconnect operations at CEA-Leti, with Scannell focused on manufacturing and Dutoit on design. Unfortunately, we did not have time to interview Scannell, though his research is summarized here. The interview below is with Dutoit. Leti has both a 200mm and 300mm line for wafer-level 3D packaging research. 2.5D passive interposers and 3D active stacks are “cousins” in device packaging, and you will see both of them used for different purposes for quite some time. While both 3D and 2.5D technologies can appear in the same package, the supply/value chains for each technology are quite different.

What’s in store in this area? “Smart” interposers are being developed with integrated passives on the interposer. 3D partitioning is enabling scaling as you like it — preventing chips from being held back to a larger device node by one of the blocks involved. Also on the horizon is via-last through silicon vias (TSV), an old technology that could now come back to offer continued TSV diameter scaling past what via-middle architectures can provide. The enabling technology here is permanent bonding. Also on CEA-Leti’s agenda is direct bonding, which spreads the stress gradient over the entire copper daisy chain, unlike today’s TSVs, and has a lower contact resistance. Finally, the researchers are considering sequential or monolithic 3D to make 50nm stacked structures on a wafer.

Before the meeting ended, Laurent Malier, CEO of Leti, spoke with Solid State Technology about the research organization’s current goals.

Check out Solid State Technology’s coverage of SEMICON West 2012!