Tag Archives: Advanced Packaging

January 24, 2012 – Imec and PVA Tepla say they have achieved void detection in through-silicon vias at wafer level, after TSV copper plating, thanks to a nondestructive high-frequency scanning acoustic microscopy (SAM) technique. The method also can be applied to detect voids in TSVs during processing, they claim.

The initial focus of their work was to develop metrology for detecting voids after temporary wafer bonding of 3D wafers, which remains challenging because development of interface particles and voids can impact subsequent wafer thinning processes, as well as overall wafer thinning and tool performance.

To address this, PVA Tepla and imec developed an automated foup-to-foup, wafer-level process based on 200MHz SAM using Tepla

January 18, 2013 – Ziptronix Inc. says it has signed a licensing agreement with Novati Technologies Inc. for the use of its patented direct bonding technologies, "direct bond interconnect" (DBI) and "direct oxide bonding (ZiBond).

Novati, the former SVTC facility in Austin which was acquired and relaunched by Tezzaron Semiconductor last fall, will use the technology for 3D stacking services and test. Tezzaron itself recently licensed Ziptronix’s DBI and ZiBond patents for use in 3D memory.

"Adding Ziptronix 3D process technologies to Novati’s existing wafer fabrication and testing facilities enables Novati to become the first open-platform, full-line foundry in the world offering 3D stacking services and test to all its customers," stated Dave Anderson, CEO of Novati Technologies. "We believe 3D is the new cutting edge of product development and we intend to continue our heritage as a contract R&D and lab-to-fab production facility enabling customers to cost-effectively prototype and test both 2.5D interposer and 3D designs with true, 3D integration and TSV interconnect."

"With our DBI, which contains interconnect at the bond interface, Novati can now provide technologically advanced services in many different markets at a lower cost and better performance compared to competing technologies also attempting 3D integration," added Ziptronix CEO Dan Donabedian.

At the recent Georgia Tech-hosted International Interposer Conference, Matt Nowak of Qualcomm and Nagesh Vordharalli of Altera both pointed to the necessity for interposer costs to reach 1$ per 100mm2 for them to see wide acceptance in the high-volume mobile arena. For Nowak, the standard interposer would be something like ~200mm2 and cost $2. The question that was posed but unanswered was: "Who will make such a $2 interposer?"

Less than a month later, this question began to be answered as several speakers at the year-ending RTI ASIP conference (Architectures for Semiconductor Integration and Packaging) began to lift the veil on silicon interposer pricing.

Sesh Ramaswami, managing director at Applied Materials, showed a cost analysis which resulted in 300mm interposer wafer costs of $500-$650 / wafer. His cost analysis showed the major cost contributors are damascene processing (22%), front pad and backside bumping (20%), and TSV creation (14%).

Ramaswami noted that the dual damascene costs have been optimized for front-end processing, so there is little chance of cost reduction there; whereas cost of backside bump could be lowered by replacing polymer dielectric with oxide, and the cost of TSV formation can be addressed by increasing etch rate, ECD (plating) rate, and increasing PVD step coverage.

Since one can produce ~286 200mm2 die on a 300mm wafer, at $575 (his midpoint cost) per wafer, this results in a $2 200mm2 silicon interposer.

Lionel Cadix, packaging analyst of Yole D

December 19, 2012 – Singapore’s Institute of Microelectronics (IME), a research institute of the Science and Engineering Research Council of the Agency for Science, Technology and Research (A*STAR), has launched a new multiproject wafer service (MPW) for 2.5D through-silicon interposers, to provide a cost-effective platform for R&D prototyping and proof-of-concept in the technology.

The 2.5D interposer MPW service, supported by IME’s 3D through-silicon via (TSV) engineering line, includes the following modules:

  • Leveraging industry standard Electronic Design Automation (EDA) tools to perform 2.5D TSI design, extraction and verification;

  • TSV with critical dimension (CD), e.g. 10-50

December 17, 2012 – Tezzaron Semiconductor has licensed patents regarding Ziptronix’s direct bonding technologies, "direct bond interconnect" (DBI) and "direct oxide bonding (ZiBond), for use in 3D memory.

Bob Patti, CTO of Tezzaron, pointed to "a direct and robust synergy" between his company’s FaStack 3D technology and Ziptronix’s technologies, calling them "a formidable team." (The two companies have been partnering on 3D ICs since 2005.) This deal broadens Tezzaron’s capabilities in producing advanced 3D memories and extends the scope of 3D and 2.5D devices it can assemble for customers. "With this suite of powerful technologies, we offer a truly ‘one-stop’ solution for both 3D and 2.5D," he said.

Traditional die stacking requires die thinning and thinned-die handling and development of reliable interconnect processes. Ziptronix DBI combines proprietary wafer-level low-temperature oxide bonding and interconnection. It creates extremely strong low-stress bonds, allowing wafers to be processed and thinned after bonding, eliminating the need to handle thinned wafers and/or dies. Interconnect density and alignment accuracy are high, and the device profile is kept low, Ziptronix notes. The process is compatible with damascene interconnect processing, and various test and repair strategies.

DBI was originally used for backside imaging (BSI) sensors, where Ziptronix claims it delivers cost savings of up to 80% over copper thermo-compression bonding. Earlier this year the company helped a memory manufacturer use the new technology in place of standard die stacking, enabling wafer-level stacking to increase memory density and significantly reduce packaging costs. At the time the company had hinted more licensing deals outside the image sensor space were in the pipeline.

"With our DBI, which contains interconnect at the bond interface, Tezzaron can provide a technologically superior product in the memory market at a lower cost and better performance compared to competitors also attempting 3D integration of advanced memory devices," stated Ziptronix CEO Dan Donabedian. "Tezzaron stands alone today in its adoption of the most advanced interconnection technology and therefore will lead the industry in technology areas only imagined just a few short years ago."

Many of the world’s 3D IC elite met last week at the 2nd annual Georgia Tech 2.5D Interposer Conference which focused on the technology and performance of silicon and glass interposers.

Matt Nowak of Qualcomm, long a 3D advocate, reported that Qualcomm has now built "thousands of parts" and does not see anything stopping high-volume manufacturing (HVM) except cost. Nowak indicates that Qualcomm will require a price of ~ $2 for a 200mm2 silicon interposer. The former is just out of the reach of those proposing "coarse" interposer fabrication, and the latter is significantly out of the pricing structure for dual damascene foundry-based fine interposers

Nagesh Vordharalli of Altera quoted an IMEC study which shows that the sweet spot for maximum bandwidth will come from interposers with RDL lines/spaces ~ 3

November 13, 2012 – Alchimer SA says it is seeking partnerships with various semiconductor equipment and materials companies as it welcomes two top execs. Bruno Morel is the company’s CEO since May of this year, and product development director Fr

November 7, 2012 – Deca Technologies has introduced a new chip-scale packaging (CSP) product line offering a rugged, fully molded packaging technology in ball-grid array (BGA) style formats that eliminate the need for laminate substrates.

A year ago Deca launched its inaugural wafer-level chip-scale packaging (WLCSP) technology "derivatives," developed with help from solar tech firm SunPower, promising a combination of speed, low cost, and flexibility. Much of the technology behind its work, though, was customized and deeply proprietary, with few details made available.

Nonetheless, industry response to the WLCSP offering "has been very strong," with multiple customers now in production and many more undergoing qualification, claims Tim Olson, Deca president/CEO.

The company’s new M-Series CSP line, geared for applications where the WLCSP option isn’t a good fit, features an "Adaptive Patterning" design/patterning process that allows features such as vias and redistribution traces to dynamically align to shifting die within an embedded device structure — creating a unique design for each device during the manufacturing process. The company says the methodology integrates a fixed design pattern with an adaptive region to resemble classic wirebond, but realized through a wafer-level build-up flow. With an additional "dimensional inspection" step and processing through an automated design software, a unique design is created for every device within a molded panel, removing the barrier of a cost-effective embedded flow, the company claims.

The M-Series CSP is now sampling "to a limited set of customers," with broader availability planned for 2013, the company says.

Dr. Phil Garrou, SST‘s resident expert and blogger about all things advanced packaging, is digging into the details of Deca’s new CSP and "adaptive patterning" offering — look to his Insights from the Leading Edge (IFTLE) blog for an analysis in the coming days.

Keeping it Cool

Back in 2008 we addressed 3D cooling activities [see PFTLE 43, "Keeping it cool in the dog days of summer"] looking a the activities at IBM Zurich, GaTech, and CALCE (U Md) as the groups especially active in this area.

Since then we have looked further at the liquid cooling activities of Bakir at GaTech [see IFTLE 83, "Orange County IEEE CPMT 3DIC Workshop"] and Brunschwiler at IBM Zurich [see "IBM to use water cooling for future 3D IC processors"] and the fact that one of the drivers for 2.5D is that it offers better thermal performance that current 3D stack solutions [ see IFTLE 97, "DATE in Dresden, Synopsys 3D EDA solution"]. For the most part, though, IFTLE has taken the position that thermal would not be the roadblock for 3DIC and that initial products would be ones where the thermal solution was not driving the technology.

Now that we are quickly approaching full commercial production of a number of products, it’s probably a good time to focus more on proposed thermal solutions for the future. To update yourself on where things stand, I suggest Herman Oprins’ article "Modeling and experimental characterization of hot spot dissipation in 3D stacks." He concludes that thermal management issues in these 3D stacks are one of the main challenges for 3D integration since the use of polymer adhesives with low thermal conductivity, the presence of interconnection structures, back end of line (BEOL), redistribution layers (RDL), and through-Si vias (TSVs) increases the complexity of the conductive heat transfer paths in a 3D stack.

Oprins concludes that hot spot power dissipation results in significantly higher temperatures in 3D stacked chips compared to the same power dissipation in single 2D chips. This temperature increase is mainly due to the reduced thermal spreading in the thinned dies on the one hand, and to the use of adhesives with low thermal conductivity for the vertical integration of the chips on the other hand. To limit the temperature increase in 3D-ICs, "too thin chips should be avoided" because the thinner the silicon substrate, the higher the thermal spreading resistance is in the case of hot spots. Simulations show that a minimum die thickness of 50