Tag Archives: Advanced Packaging

June 12, 2012 – BUSINESS WIRE — UltraSource Inc., thin film circuits and ceramic interconnect device supplier, announced CopperVia, a process that fills vias with pure copper to yield low-cost, high-conductivity, reliable electrical and thermal interconnects in ceramic thin film circuit substrates.

The CopperVia process is based on the existing patented UltraVia process. CopperVia virtually eliminates epoxy or solder bleed-through while maximizing thermal and electrical conductivity and reliability. It can be used in planar, 2.5D, 3D, and multilayer thin film circuitry.

Solid filled vias provides a low inductance, microwave grounding path, allowing high performance RF circuits to be assembled in a thermally efficient surface mount configuration.

June 12, 2012 — Electronics manufacturing and design services provider ESCATEC added package-on-package (PoP) capability at its Heerbrugg, Switzerland, facility, adding a dipping unit for ball grid array (BGA) packages on its Siplace assembly line.

Figure 1. PoP stack before soldering.

The dipping unit wets about 50% of each ball on the package with paste/flux. Before reflow, both BGA components are stacked on each other and then both are soldered in one process step. During the soldering, the upper device sinks down, eliminating any gap between the stacked packages in the final assembly.

Figure 2. PoP stack after flow soldering.

Verification of accurate bonding between the layers of the PoP stack is checked using X-Ray inspection. Darker balls in Figure 3 are from the upper BGA and lighter balls are from the lower BGA.

Figure 3. Xray of PoP stack.

June 12, 2012 – PRNewswire — Terepac Corp. will produce high volumes of its proprietary micro circuits for Rockwell Automation, supporting the "Internet of Things" with radio frequency identification (RFID) tags. Rockwell Automation will support the infrastructure that Terepac uses, enabling it to miniaturize significantly more circuits than its current capability.

Terepac

June 8, 2012 – BUSINESS WIRE — Advantest Corporation (TSE:6857, NYSE:ATE) is developing a line of fully automated and integrated test and handling solutions for through silicon via (TSV)-based 2.5D and 3D packages. The concept model test cell, DIMENSION, integrates a high parallel test cluster along with singulated die and 3D die stack automated handling capabilities.

The concept test cell solution will be designed for die handling, test, and production line integration. From wafer to known good die (KGD) and known good stack (KGS), the DIMENSION concept shows the direction of 2.5D and 3D production-capacity, specification performance, and yield.

2.5D and 3D-stack technologies offer improvements to density, power and performance. The DIMENSION concept addresses challenges with delicate and thin die handling, active thermal management, and overall yield management with SmartDieCarrier (SmtDC) technology. SmtDC solutions provide die pick & place plus very fine pitch contact with both extreme precision and delicate soft touch handling. And Active Thermal Control (ATC) with real time power management achieves yield and specification compliance.

Advantest makes automatic test equipment (ATE) for the semiconductor industry and manufactures measuring instruments. More information is available at www.advantest.co.jp

Learn more about 2.5D/3D packaging technology developments in our report from The ConFab: 3D and 2.5D semiconductor packaging technologies

Visit the Advanced Packaging Channel of Solid State Technology, and sign up for our Advanced Packaging News e-newsletter!

June 8, 2012 — Semiconductor test tool maker Multitest has made its InCarrier Loader/Unloader available in a variety of configurations, e.g. for loading from tube, bowl, tray and for unloading into tube, bulk or metal mag in any combination. Additionally, partner solutions for loading from wafer ring or unloading into tape-and-reel are available.

The Multitest InCarrier is a test handling solution that combines elements of strip handling process and the standard test handling process. The concept of the InCarrier consists of a tray/carrier, into which singulated ICs are loaded to be tested in the InStrip, Multitest

June 7, 2012 — Day 3 of the 15th IITC (International Interconnect Technology Conference) opened Wednesday, June 6 at the Doubletree Hotel in San Jose, CA under clear sunny skies and a pleasant breeze. The herd thinned a bit, down to ~150 hearty souls from the original 230 the prior two days.

Read Fury’s reports from Day 1 and Day 2 of IITC.

Subramanian Iyer of IBM started the day with an invited talk on scaling in the 3rd dimension (not to be confused with The Adventures of Buckaroo Banzai Across the 8th Dimension) and prospects for silicon interposers and 3D integration. His retrospective introduction harkened back to IBM

June 7, 2012 — FormFactor Inc. (NASDAQ: FORM) introduced TrueScale Matrix probe cards for 200mm and 300mm Full Wafer Contact system-on-chip (SoC) test applications. TrueScale Matrix applies FormFactor