Tag Archives: Advanced Packaging

June 6, 2012 — The ConFab, taking place this week in Las Vegas, NV, is an invitation-only meeting of the semiconductor industry. As packaging has played a larger and larger role in chip performance, form factor, and capabilities, The ConFab has increased its focus on back-end processes. Cue

June 4, 2012 — Displaybank published a 2009-2014 analysis of light-emitting diode (LED) packages, the finished LED components used in various applications. While LED package units will grow steadily through the forecast period, revenues will remain mostly flat from 2010 to 2013.

Figure. LED package sector growth by units shipped and by revenue through 2014. SOURCE: LED Industry Outlook – Package (2009~2014), Displaybank.

LEDs are achieving near 100% penetration in mobile device displays, emerging as a major segment of lighting, and replacing CCFLs in television backlights. Market penetration is increasing for internal and external automotive lights, as well as signage applications.

LED light sources can offer higher performance and lower power consumption than traditional technologies. The technology is also considered more environmentally friendly, and can reduce costs for some applications.

The report,

June 4, 2012 – Marketwire — The New York State Center of Excellence in Small Scale Systems Integration and Packaging at Binghamton University (S3IP), and Applied DNA Sciences Inc. (OTCBB:APDN), both in NY, will collaborate on microelectronics research and commercialization and other projects, starting with forensic authentication and security based on Applied DNA Sciences’ technologies, under a new Memorandum of Understanding (MoU).

The partners

May 31, 2012 – PRNewswire — Xilinx Inc. (NASDAQ:XLNX) began shipping a 3D heterogeneous all-programmable FPGA, the Virtex-7 H580T FPGA, using its stacked silicon interconnect (SSI) technology to reach up to 16 28Gbps and 72 13.1Gbps transceiver bandwidth.

May 30, 2012 – BUSINESS WIRE — Semiconductor direct bonding technology provider Ziptronix Inc. is helping a 3D memory device maker replace standard die stacking with its DBI wafer-stacking technology. Memory stacking can enable higher memory density in a given footprint, and the wafer-level stacking technology could significantly reduce packaging cost for the 3D architecture.

Traditional die stacking requires die thinning and thinned-die handling and development of reliable interconnect processes. Ziptronix DBI combines proprietary wafer-level low-temperature oxide bonding and interconnection. It creates extremely strong low-stress bonds, allowing wafers to be processed and thinned after bonding, eliminating the need to handle thinned wafers and/or dies. Interconnect density and alignment accuracy are high, and the device profile is kept low, Ziptronix notes. The process is compatible with damascene interconnect processing, and various test and repair strategies.

DBI is used for backside imaging (BSI) sensors, where Ziptronix reports that it delivers cost savings of up to 80% over copper thermo-compression bonding. The new collaboration is founded on Ziptronix DBI