March 13, 2012 — ULVAC Inc. developed solder deposition processes for silicon device packaging, including power devices, that sputters solder to deposit it rather than printing or evaporating the materials. The 2 processes eliminate gold, or gold and nickel, from the step.

Electrodes on the back of power devices (IGBTs, MOSFETs) make ohmic contact with silicon substrates and provide heat sinks for solder joints. A typical deposition composition is formed from the layer closest to the Si substrate by an aluminum or silicide ohmic contact layer; a titanium barrier metal layer; a nickel bonding film layer; and a gold deposition layer, which prevents surface oxidation and improves soldering.

In current device manufacturing processes, these electrode layers are deposited by sputtering or evaporation; then, electrodes are taken out of the vacuum for solder deposition at a given thickness. Finally, they are joined to a heat sink substrate by reflow soldering. Efforts are being made to reduce the thickness of the Au deposition layer on the electrode surface as well as to use alternative materials.

The ULVAC solder sputtering method claims the same or higher joining strength than the conventional process, with reduced cost. Sputtering deposition occurs in the vacuum immediately after Ni film deposition, without Au film deposition on the surface of Si device electrodes.

Process 1: Solder pasting/solder sputtering/Ni/Ti/Al/Si wafer (no use of Au)
This process deposits a 0.5um tin/silver/copper (Sn-Ag-Cu, SAC) lead-free solder layer by vacuum sputtering immediately after depositing the Ni film layer. The Ni film layer serves the solder layer is used as the joining layer on the electrode surface. Sputter deposition of Ni and solder not only provides soldering with solder paste and the same joining strength, but also makes it possible to reduce material costs by approximately 50% compared with conventional electrodes with Au layers.

Process 2: Solder pasting/solder sputtering/Ti/Al/Si wafer (no use of Au or Ni)
This process eliminates the use of Au and Ni, further reducing electrode film material costs. A Ti film is an alternative to Ni, forming an alloy with Sn at a reflow temperature of about 230C for similar solder joints as those made conventionally.

ULVAC’s SRH series sputtering deposition systems are used in these new processes, and form backside electrodes for power devices, electroplating seed layers in wafer-level chipscale packages (WLCSP), barrier metals for under-bump metallization (UBM), and other devices.

Demonstrations of the newly developed processes will be performed at ULVAC’s Chigasaki Plant, Japan, starting in April.

The details of the newly developed technology will be presented at the 59th Spring Conference of the Japan Society of Applied Physics (6.4 Novel materials for thin films: 16a-F2-12) to be held at Waseda University’s Waseda Campus in Shinjuku-ku, Tokyo, March 15 to 17.

ULVAC, Inc., is a vacuum equipment manufacturer for flat panel displays, solar cells, semiconductors, electronic components, and general industrial equipment manufacturing. For more information, visit www.ulvac.co.jp/eng/

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March 9, 2012 — Kulicke & Soffa Industries Inc. (K&S, NASDAQ:KLIC) introduced its ConnX Plus high-speed ball bonder for semiconductor packaging.

The second-generation ball bonder is part of K&S’ Power Series, with higher productivity (more units per hour bonded and new tool features) than the previous generation in low pin count, discrete and cost/performance packaging applications, the company reports.

New features on the next-gen ball bonder include Interactive Programmable Look Ahead Vision to ease first time set-up; Power Series Xpress Loop to help increase the productivity of short wire applications; optional Dual Mag Optics Kit integration for stacked-die bonding; and 10% more units per hour (UPH) than the prior model. The ConnX Plus is field upgradable to the ConnX Plus LAPS, supporting an 87mm² bondable area.

The ConnX Plus will debut at the Semicon China show at the Shanghai New International Expo Centre from March 20-22, 2012. Also debuting at K&S’ booth: LUMOS Capillary for LED wire bonding and new AccuPlus Hub Blades for discrete semiconductor dicing.

Kulicke & Soffa (NASDAQ: KLIC) designs and manufactures semiconductor and LED assembly equipment. Internet: www.kns.com.

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March 9, 2012 — Kulicke & Soffa Industries Inc. (K&S, NASDAQ:KLIC) launched its AccuPlus Hub Blades product line, customizable blades for discrete wafer dicing.  

Discrete semiconductors are fabbed on thinned wafers, and die sizes are generally small. This presents die movement and blade loading challenges at the wafer dicing step, notes K&S.

To prevent die chipping and cracks during wafer dicing, key blade elements were optimized: diamond grit size, diamond concentration, and nickel bond hardness. The blades boast a shortened pre-cut process, two special nickel bond hardness series, multi-levels of diamond concentration, and a special hub material and design for high spindle frequency with lower vibration.

The Discrete Series

March 8, 2012 — AGC (Asahi Glass Co. Ltd.) developed ultra-high-speed processing technology for micro hole drilling of 0.1mm-thin glass, targeting leading-edge applications such as 3D semiconductor packages.

Ultra-thin glass has prospects for being applied to various products thanks to its thinness of 0.1mm in addition to the excellent features of glass including transparency, heat resistance and electrical insulation. Last year, AGC developed the thinnest (0.1mm) float glass, but these were difficult to process using ordinary processing methods, which led to this new drilling technology

AGC developed the micro hole drilling processing technology using a dielectric breakdown induced by electrical discharging. This technology has enabled precise drilling processing on ultra-thin glass with a very high processing speed, in the order of a few milliseconds.

This technology can be applied, for instance, to hole drilling processing of thin sheet glass for interposers for laminated stacked-die packages with interposers. This interposer needs many holes with a diameter of about 50

March 8, 2012 – PRNewswire-Asia/ — Semiconductor Manufacturing International Corporation (SMIC; NYSE:SMI; SEHK:0981.HK), China-based advanced semiconductor foundry, announced an ultra high density (UHD) library solution for its 0.11um copper back end of line (Cu-BEOL) manufacturing platform that can reduce chip size by an average of 31%.

SMIC’s comprehensive silicon-proven UHD IP solution incorporates SMIC’s in-house UHD IP library, based on smaller bit cells, and Mentor Graphics’ (NASDAQ: MENT) cool-memory IP library with MemQuestTM memory compiler, specifically designed for compatibility with SMIC’s UHD solution. SMIC’s in-house UHD library consists of a 6-track UHD standard cell library, UHD memory compiler, and UHD standard I/O library. Mentor Graphics’ UHD cool-memory IP library comprises coolSRAM-6T, coolREG-6T, coolREG-8T (Dual Port), coolREG-8T (Two Port), and coolROM. This unified library solution can generate different configurations to optimize power, speed, and density, and is available to SMIC customers free of charge.

SMIC’s 0.11um UHD IP solution enables a 31% chip size reduction for a typical SOC design, when compared to a design that uses a traditional IP library. This can bring cost advantages to users making SoCs for mobile storage devices, flash memory controllers, mobile multimedia players, digital televisions, and set-top boxes, among other applications.

"SMIC’s 0.11um Cu-BEoL process has long been recognized by our customers for its high stability. We have an accumulative shipment of more than 100,000 wafers adopting SMIC’s 0.11um IP library on our existing Cu-BEoL platforms," said Steven Chen, Senior Director of SMIC’s Product Marketing Division. "Our Beijing and Shanghai fabs provide customized service based on our customers’ chip size and quantities in order to meet their manufacturing requirements. Now with the release of SMIC’s 0.11um ultra high density IP solution, we can further help our customers lower their manufacturing costs and increase their market competitiveness."

"Mentor Graphics is very pleased to be able to offer its systemic, low-power and high density memory compiler technology to SMIC 0.11um users, to further optimize their design and embedded memory usage for additional density and cost gains," said Farzad Zarrinfar, Managing Director of the Novelics business unit at Mentor Graphics.

Semiconductor Manufacturing International Corporation (SMIC; NYSE:SMI; SEHK:981) is a semiconductor foundry in Mainland China, providing integrated circuit (IC) foundry and technology services at 0.35um to 40nm. Headquartered in Shanghai, China, SMIC has a 300mm wafer fabrication facility (fab) and three 200mm wafer fabs in its Shanghai mega-fab, two 300mm wafer fabs in its Beijing mega-fab, a 200mm wafer fab in Tianjin, and a 200mm fab under construction in Shenzhen. SMIC also has customer service and marketing offices in the U.S., Europe, Japan, and Taiwan, and a representative office in Hong Kong. In addition, SMIC manages and operates a 300mm wafer fab in Wuhan owned by Wuhan Xinxin Semiconductor Manufacturing Corporation. For more information, please visit http://www.smics.com/

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March 7, 2012 — Surrey NanoSystems raised third-round funding of