Tag Archives: Advanced Packaging

March 1, 2012 – Marketwire — Semiconductor test equipment supplier Verigy, an Advantest Group company (TSE: 6857, NYSE:ATE), installed multiple V93000 Smart Scale and Pin Scale Generation testers with Pin Scale digital channel cards at ISE Labs’ test and packaging facilities in CA and TX.

ISE Labs has a long history with Verigy tools. Its Austin, TX facility will begin using Verigy’s Pin Scale technology to develop advanced test methodologies for the latest generation of low-power ARM-based server processors with high-speed DDR3 memories, PCI Express interfaces and consumer ICs such as smart media system-on-chip (SOC) devices for next-generation media gateways and set-top boxes. The lab will run a V93000 Pin Scale Generation system with an L-Class test head, delivering more than 900 pins, based on Verigy’s Pin Scale 400 and Pin Scale 800 cards.

ISE Labs’ Fremont, CA semiconductor testing laboratory installed two V93000 Smart Scale Generation testers with Pin Scale 1600 cards for use in production-volume IC testing. One V93000 has a C-Class test head with over 1,000 pins using Pin Scale 1600 and Pin Scale 9G cards and the other unit is equipped with Verigy’s smallest A-Class test head, populated with 512 pins, and a MB-AV8 PLUS analog card. The systems also are upgradeable to provide increased pin counts or to add new measurement resources such as Verigy’s Port Scale RF solution.

These installations mark the first application of the company’s Smart Scale technology by a test-services provider in Silicon Valley. ISE Labs will use them for technology development and commercial testing services, noted Sanjeev Mohan, VP of North America sales and support at Verigy. The scalable test systems and pin cards target cost-efficient testing of advanced semiconductor designs, including 3D device architectures and 28nm technology node and smaller ICs.

The Pin Scale 1600 card opens a new dimension in test flexibility. With this card’s universal per-pin architecture, each channel is able to perform any function needed by the device under test, providing maximum flexibility. Per-pin capabilities such as individual clock domain, high accuracy DC and industry-leading digital performance are expanded with the Pin Scale 1600.

Verigy’s Pin Scale 9G card is the only fully integrated, high-speed, digital instrument covering the entire range from DC to more than 8 gigabits per second, making at-speed test affordable. The highly versatile Pin Scale 9G can test any combination of parallel or serial, single-ended or differential, and uni- or bi-directional interfaces.

The MB-AV8 PLUS analog card expands real-time analog bandwidth to cover emerging applications such as LTE Advanced for 4G wireless communications. It provides high throughput while maintaining compatibility with established MB-AV8 instruments.

ISE Labs, Inc. is a wholly owned subsidiary of Advanced Semiconductor Engineering, Inc., is an independent provider of semiconductor packaging and testing services. For more information, visit www.iselabs.com.

Verigy provides advanced semiconductor test systems and solutions used by leading companies worldwide in design validation, characterization, and high-volume manufacturing test. Additional information about Verigy, an Advantest Group company, can be found at www.verigy.com. Information about Advantest can be found at www.advantest.com.

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February 28, 2012 – BUSINESS WIRE — Wafer-level camera maker Nemotek Technologie uncrated a two-element wafer-level camera, Exiguus H12-A2. The two-element lense gives Exiguus H12-A2 high resolution and low (<0.5%) distortion in an ultra-small wafer-level package.

The camera is designed for mobile, laptop, and gaming applications.

Also read: Nemotek wafer-level camera integrates CMOS image sensors

The Exiguus H12-A2 is reflowable, and offers sophisticated camera functions, such as auto exposure control, auto white balance, black level calibration, noise reduction, flicker detection and avoidance. As a high end VGA CMOS wafer-level camera, the solution features an active pixel array of 640H x 480V and measures 1/10-inch. Moreover, the camera features color correction, color saturation, lens shading correction, software reset as well as chrominance control and maintains the ability to withstand extreme temperatures.

In addition, Nemotek marks its debut into the high-end (HE) VGA market with another new camera based on a 720P High End sensor.

Samples of Nemotek’s Exiguus H12-A2 and its High End VGA camera are currently available.

Nemotek Technologie designs, develops and manufactures customized Wafer-Level Cameras for portable applications. For more information, visit http://www.nemotektechnologies.com/.

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February 24, 2012 — With thermal issues accounting for half of all lighting failures, and costs too high for widespread adoption, assembly and packaging are keys to improving light emitting diodes (LEDs). In "High Brightness LED Assembly Trends, Materials and Issues," consulting firm TechSearch International tracks LED packaging materials and methods, as well as reliability and package efficiency. The report reviews high-brightness LED assembly trends and issues, materials used today, and requirements for the future. Critical issues, including thermal and optical, are addressed.

Packaging materials significantly affect the optical efficiency of LEDs. Reflectivity, transmissivity, and index of refraction can affect the lumens output. Thermal issues account for as much as 50% of the failures in lighting. Packaging material stability (encapsulants and lenses) is also affected by exposure to elevated temperatures, UV, and other wavelength radiation.

There are no standard LED packages. The variety of materials selected, packaging methods, and ultimately reliability make cost-reduction a complex decision-making process.

In the report, TechSearch International shares examples of various packages for high-brightness LEDs to illustrate the diversity in package options.

TechSearch International

February 23, 2012 — Wafer-level packaging tool maker NEXX Systems was awarded a $42,765 Workforce Training Fund grant from the state of Massachusetts, where NEXX Systems is headquartered. The grant will help provide training and professional development for more than 100 employees there, improving lean manufacturing techniques and adding to their skill sets.

NEXX will focus trainings on leadership, encouraging employees to enhance their skills, improve individual performance and increase overall productivity. Another major effort will go into continuous process improvement training, with practices based on 6 Sigma, lean manufacturing and the Five S’s. NEXX manufactures its semiconductor packaging equipment in the US, with emphasis on high performance tools for packaging lines and development work.

The Workforce Training Fund works with Massachusetts Governor Deval Patrick and Lieutenant Governor Timothy Murray, training over 85,000 Massachusetts employees since 2007. "With this training, companies create greater efficiencies in doing business, leading to more opportunities for jobs, increases in work capacity and business growth," said Murray.

NEXX Systems provides flip chip and advanced packaging equipment. Learn more at http://www.nexxsystems.com/.

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February 21, 2012 — Electronics System Integration Technology Conference (ESTC) 2012 seeks original papers describing research in all areas of electronic packaging, including LED packaging, flexible electronics, assembly and interconnect technologies, and more. ESTC takes place September 17-20 in Amsterdam, the Netherlands. Organized by IEEE-CPMT since 2006, in association with IMAPS-Europe, the ESTC conference series focuses on interconnect and packaging technologies for electronic system integration. Submit your abstract by April 1.
 
Paper abstracts may be submitted to the following tracks and application areas:

  • Assembly and Manufacturing Technology
  • Materials for Interconnect and Packaging
  • Reliability
  • Embedded Die and Wafer Level Packaging
  • 3D Integration Technology
  • Microsystem Packaging
  • Flexible and Stretchable electronics
  • Advanced and Emerging Technologies
  • Power Electronic Packaging
  • Optoelectronic Packaging
  • Thermal and Mechanical Modeling
  • Electrical Design & Modeling
  • Consumer Electronics
  • Automotive and Industrial Electronics
  • Avionics and Space Electronics
  • Medical Electronics
  • Solid State Lighting
  • Telecom System Electronics
  • Wireless Electronics
  • RF-ID and Smartcards
  • Display and Imager Electronics
  • Energy System Electronics

Submit a 300-500 word abstract that describes the scope, content and key points of your proposed paper. Abstracts must include results and graphics. Please visit www.estc2012.eu to upload your abstract. Submissions for poster presentations are also welcome. Submission deadline for abstracts is April 1, 2012.

ESTC will select the best paper and best poster presentations. For each, the author(s) will receive a personalized ESTC award and a monetary prize from the IEEE-CPMT Region 8 Director.

The official language of all presentations is English. All oral and poster presentation authors are invited to prepare a paper for the conference proceeding which will also be included in the IEEE XPLORE database after the conference.
 
Your submission must include the mailing address, business telephone number and email address of the presenting author and affiliations of all authors. All submitted abstracts will be reviewed by the committee to ensure a high-quality conference. At the discretion of the program committee, paper abstracts submitted may be considered for poster presentation. The work should be original and not previously published, and avoid inclusion of commercial content. Additional instructions about formatting the paper will be published on www.estc2012.eu.

Selected presenters will be notified on June 1, 2012. Final paper manuscript will then be due August 15, 2012.

Related story: Advanced packaging at the 2010 ESTC

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February 21, 2012 — The 2012 IMAPS Device Packaging Conference will take place March 6-8 in Fountain Hills, AZ, with sessions on 2.5/3D packaging, flip chip and wafer level packaging (WLP), micro electro mechanical systems (MEMS), high-brightness light-emitting diodes (HB-LEDs), and passive integration.

Dr. Robert Darveaux, SVP of Technology & Platform Development, Amkor Technology Inc., will keynote Flip Chip & Wafer Level Packaging with "Escalating Challenges in Developing Complex Solutions for Next Generation Package and Interconnect Technologies."

Amkor is also presenting in the technical sessions. IMAPS Device Packaging includes sessions, panel discussions, a poster session, professional development courses and a vendor exhibition and technology showcase.

To register or get more information on the show, visit WWW.IMAPS.ORG/DEVICEPACKAGING

Visit Amkor Technology at BOOTH #37.

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February 17, 2012 — The International Electronics Manufacturing Initiative (iNEMI) will hold the industry kick-off for its 2013 Roadmap in an open workshop immediately following IPC APEX EXPO in San Diego, CA, March 1-2.

Also read: 2011 ITRS: DRAM, 3D Flash, MEMS, nano scaling steal the show

The day-and-a-half workshop will begin with a review of the product sector key attribute spreadsheets, followed by break-out meetings of the technology groups as they begin the process of identifying technology and infrastructure needs for the electronics manufacturing supply chain. Packaging attendees will be interested in the Packaging & Component Substrates chapter of the roadmap especially.

Membership is not required to participate in the roadmap; non-member participation is encouraged to ensure a broad and accurate perspective of the supply chain.

The iNemi roadmap highlights processes and capabilities that will be needed for future products, including disruptive and emerging technologies. Every 2 years, the Roadmap is mapped out to identify key gaps in technology and infrastructure, R&D needs, and other activities needed for advanced electronics supply chains.

Check out the 2011 Roadmap: MEMS, 3D packaging major factors in iNEMI roadmap

Efforts are organized into Product Emulator Groups (PEGs) and Technology Working Groups  (TWGs).  The PEGs, each chaired by a major OEM in the specific sector covered, define the future technology needs of

February 15, 2012 — Finetech will donate a high-accuracy die bonder in a drawing this summer that is open to U.S. and Canadian qualified universities and colleges.

The multi-application FINEPLACER Pico MA bonder with 5

February 15, 2012 — Hesse & Knipps Inc., the Americas subsidiary of backend packaging equipment supplier Hesse & Knipps Semiconductor Equipment GmbH, opened a West Coast Demo and Applications Laboratory at its manufacturer rep Chalman Technologies, Anaheim, CA. Chalman Technologies has served as Hesse & Knipps