Tag Archives: Advanced Packaging

January 19, 2012 – BUSINESS WIRE — Hitachi Chemical Co. Ltd. (TOKYO:4217) filed a lawsuit against INNOX Corporation with the Intellectual Property Court of Taiwan, alleging infringement on Hitachi Chemical’s Taiwanese patent related to die bonding film used in semiconductor packaging processes.

Hitachi Chemical’s Taiwan Patent No. I298084 is the subject of the company’s patent case, alleging use in INNOX’s product WL-0020-05A, a die bonding film for wafer dicing steps. Hitachi Chemical has sent INNOX a warning letter concerning patent infringement based on Korean patent and further negotiated with INNOX in April 2011 without an amicable settlement. Hitachi Chemical has now filed a lawsuit against INNOX’s WL-0020 series products in Taiwan.

Hitachi Chemical developed a die bonding film in 1993, used for multi-laminate semiconductor attach, bonding semiconductor chips often in high density, multi-layer package designs. Hitachi Chemical offers die bonding film, dicing die bonding film and related products, and claims the largest global market share. The company has about 500 patents (including pending applications) related to die bonding films and dicing die bonding films in Japan and other countries.

Contact Hitachi Chemical Co., Ltd. (Japan) at http://www.hitachi-chem.co.jp/english/index.html.

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January 19, 2012 – BUSINESS WIRE — Optomec Inc., additive manufacturing systems provider, opened its new and expanded Advanced Applications Lab and Product Development Facility in St. Paul, MN. The facility will help Optomec grow its Aerosol Jet technology for advanced printed electronics applications.

The new facility comprises 7600 square feet of office and general laboratory space and will be utilized for both advanced development of Aerosol Jet Printed Electronics Applications and for new product engineering. Dr. Mike Renn will continue his role as Director of Aerosol Jet Advanced Application Development, and John Lees, recently appointed Director of Aerosol Jet New Product Development, will lead the product engineering team at the new facility. In conjunction with the expansion, Optomec is looking to double its local staff.

Optomec’s Aerosol Jet systems for Printed Electronics utilize a proprietary material deposition process to direct write high resolution electronic circuitry, components and even complete devices on 2D and 3D surfaces. The Aerosol Jet deposition process is highly efficient and supports a wide variety of electronic materials compared to traditional subtractive manufacturing processes. Aerosol Jet systems can be used to both lower costs and enhance performance of current electronic devices, as well as to enable the creation of next generation products, such as 3D semiconductor packaging, high efficiency solar cells and solid oxide fuel cells.

Also read: Optomec aerosol jet printing featured as wire bond, TSV alternative

Optomec provides of additive manufacturing solutions for high-performance electronics, solar, medical, and aerospace & defense applications using its Aerosol Jet printed electronics technology and LENS powder-metal fabrication technology. To learn more, visit http://www.Optomec.com

January 18, 2012 — The College of Nanoscale Science and Engineering (CNSE) of the University at Albany and Applied DNA Sciences (APDN) are partnering to enable nanotechnology to play a critical role in preventing the counterfeiting of computer chips–a collaboration in the groundbreaking area of "nanosecurity" that initially targets the $20 billion defense industry chip market and has the potential to impact nanoelectronics and aerospace markets well in excess of $300 billion. The nanosecurity technique, which uses DNA material, goes well beyond laser-based chip marking of security codes.

Also read:

 

Through joint research and development at CNSE’s Albany NanoTech Complex, CNSE and APDN, will accelerate the development of APDN’s SigNature DNA product that includes new methods for botanical DNA deposition on nanoelectronics wafers–including computer chips, CMOS, MEMS, photonics, and other device derivatives, as well as advanced packaging technologies such as 3D wafer-to-wafer and die-on-wafer–both prior to and during final packaging. The APDN system marks computer chips with uncopyable DNA codes that can then be used to authenticate the originality of chips anywhere along the supply chain, using a variety of chemical and photonic-based DNA sequence analysis instrumentation.

Dean Fuleihan, CNSE Executive Vice President for Strategic Partnerships, said, "The UAlbany NanoCollege is delighted to enter into this partnership with Applied DNA Sciences to enable innovative anti-counterfeiting technology that is vital to protecting American troops and U.S. military interests, both at home and abroad. This collaboration will accelerate research, development and commercialization to ensure the security and integrity of computer chips that drive our nation

January 18, 2011 — Die bonder supplier Hesse & Knipps Inc., the Americas subsidiary of Hesse & Knipps Semiconductor Equipment GmbH, will discuss "Wedge Bonding for RF and Microwave Devices" at the Advanced Technology Workshop and Tabletop Exhibition on RF and Microwave Packaging, February 7-8, 2012 in San Diego, CA.

The objective of the RF and Microwave Packaging Workshop is to provide a unique forum that brings together scientists, engineers, manufacturing, academia, and business people from around the world who work in the area of RF and Microwave packaging technologies. For a full program at the event, visit http://www.imaps.org/rf/index.htm.

RF and microwave device interconnection requires wedge bonding with ribbon wire, due to its ability to create flat, extremely low loop shape, and constant wire length. For high-frequency electrical signals, conduction occurs in the skin, or outer 0.5

January 16, 2012 — Mitsubishi Heavy Industries, Ltd. (MHI) launched a fully automated 12" (300mm) wafer bonding tool, Bond Meister MWB-12-ST, capable of producing 3D large-scale integration (LSI) circuits at room temperature. The 300mm bonder targets production of memory chips and microprocessor units (MPU).

The first system was installed at the National Institute of Advanced Industrial Science and Technology (AIST) in Japan.

The Bond Meister MWB-12-ST uses a fast atom beam (FAB) gun instead of a traditional ion beam gun. The FAB gun irradiates atoms to activate a material surface for bonding. Whereas an ion gun radiates an argon ion beam, an FAB gun radiates a neutral atom beam of argon, offering about 20x more energy per particle. The FAB gun effectively removes oxide film on the surface of the bonding metal. Up to 20-ton weight loading is applicable for bonding.

The system bonds up to 5 300mm wafers continuously, performing wafer transfer and alignment for automatic bonding. It can preliminarily set the bonding conditions for each wafer individually, for small lot, mixed type production. Room-temperature wafer bonding eliminates heat stress and strain, reduces wafer processing time, and could enable more miniaturization in LSI designs. The tool can bond silicon and various metals.

Also read: MHI 8" wafer bonder produces 3D LSI ICs at room temp and MHI ships first 200mm MEMS bonder

AIST is an advanced public research institute involved in industrial technology fields, with technical expertise in room-temperature bonding. The MHI wafer bonder will be used in semiconductor-related work. Learn more about AIST at http://www.aist.go.jp/index_en.html

Going forward, MHI will further intensify its proposal-based approach to potential customers to expand the adoption of room-temperature bonding as a key technology for 3-D LSI circuit production, the company reports.

MHI launched its room-temperature wafer bonding platform in 2006. MHI is involved in the engineering, manufacture and sale of ships, environmental improvement equipment, industrial machinery, aircraft, space systems, air-conditioner, etc. Learn more at http://www.mhi.co.jp/en/index.html.

January 11, 2012 — Zymet introduced the CN-1736 reworkable underfill encapsulant for 0.4mm-pitch package-on-package (PoP) assemblies.

Figure. Void-free underfill of 0.4-mm pitch POP with CN-1736.

The underfill boasts low viscosity and a lower CTE than its predecessors, and greater flux compatibility. The 650cps viscosity enables optimized flow speed with finer pitch devices. The CTE of 55 ppm/

January 11, 2012 — Increased I/O density on chips, power/performance requirements, yield/cost requirements and form factor constraints (mobile) are coming to push increased use of flip chip, 2.5D and 3D technologies. This trend benefits the packaging subcontractors in the semiconductor industry, argues Credit Suisse Taiwan Analyst Randy Abrams, as outsourcing rises.

Larger packaging subcontractors, like Amkor (AMKR), ASE, and SPIL, will take market share from smaller sub-contractors, Credit Suisse predicts. Large packaging houses like Amkor have invested in 3D packaging technologies, such as through silicon via (TSV) fabrication, silicon interposers, etc. They are also well-positioned for an industry shift occuring from wire bonding to flip chip, which enables higher I/O density.

Credit Suisse reports that the flip-chip trend has led to under-utilization of traditional wirebonder assets. Even if these assets are fully depreciated, they often carry fixed costs (labor, overhead). Amkor is responding to this trend by trying to penetrate the NAND market for wirebonding. It also is in talks to purchase old packaging assets from Toshiba. ASE and SPIL are migrating their capacity aggressively from gold to copper wire. ASE is also courting Japanese IDMs to outsource their discrete low-pin count in-sourced packaging needs.

The packaging houses will need to watch for foundry TSMC, which has made special references to chip on wafer on silicon (CoWoS) in its last earnings call, Credit Suisse notes. ElectroIQ.com contributor Dr. Phil Garrou reports that TSMC pushes for a pure foundry model for 2.5 and 3DIC — quoting Doug Yu, senior director of integrated interconnect, TSMC who said that TSMC was readying to take on full beginning-to-end interposer manufacturing. Read Garrou’s TSMC repeats call for foundry-centric 2.5/3D industry. Credit Suisse asserts that fabless chip companies may prefer the packaging houses over a foundry-based 3D packaging model, and companies will leverage various chip and foundry suppliers for the best commercial position, mixing and matching chips in 3D packages.

Other than the foundry encroachment, semiconductor assembly & test service (SATS) providers need to watch out for cyclical weakness in semiconductors, due to the inventory correction in H2 2011, Credit Suisse points out. Improving cyclical momentum through the year will improve absorption of wirebonder capacity discussed above, the analysts note.

Learn more about Credit Suisse at www.credit-suisse.com/global/en/.
 
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January 10, 2012 — The SMTA released its call for presenters for SMTA International (SMTAI) 2012, October 14-18 in Orlando, FL. The association, along with Chip Scale Review magazine, also announced the keynote for the International Wafer-level Packaging Conference (IWLPC), held November 5-8, San Jose, CA.

SMTAI papers are sought on electronics assembly as well as advanced packaging and components. Packaging papers can cover 0.3mm Pitch Area Array, 3D Packaging and Integration, BGA/CSP, Biomedical Packaging, Bumping, Chip on Board, Direct Chip Attach, Embedded and Miniature Passives, Failure Analysis, Fine Lead Pitch, Flip Chip, High Temperature Packaging, Lead Finishes, Leadless Packages (LGA/QFN/BTC), MEMS and Sensors, Package on Package (PoP), Photonics, Photovoltaics and Solar Packaging, Reliability, Solid and Collapsible Wafer Bumps, Through Silicon Vias (TSVs), Tin Whiskers, and Wafer Level Packaging (WLP). See SMTA’s Call for Papers site to check out all the suggested topics for emerging technologies, electronics assembly, supply chain/business papers, PCB technology, process control, and energy papers.

SMTA International offers Best of Conference Presentation, Best of Proceedings Paper, and Best International Paper awards at the show.

Abstracts (300 words) are due March 12, 2012, and can be submitted here: http://www.smta.org/smtai/call_for_papers.cfm. All abstracts must be submitted online and will not be accepted by e-mail.

Proposals are also solicited from individuals interested in teaching educational courses related to surface mount technology, advanced packaging, and electronics manufacturing.

Paper manuscripts and course workbooks are due by July 27, 2012. Papers should be 6-15 pages long (including graphics) and describe significant results from experiments, emphasize new techniques, or contain technical, economic, or appropriate test data. Presentation materials and papers must be original, unpublished, and non-commercial in nature.

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John Ellis will keynote IWLPC, discussing Cyber-Physical Terrorism in his presentation, "A Trojan Chip in Your Smartphone? It’s Coming…"

The topic is malicious circuits receiving commands via social networks. Hacking a few highly-followed celebrity accounts would provide a perfect avenue for distributing ‘self-destruct’ codes to millions of Trojan chips. A widespread, cyber-physical attack, which would have been almost impossible to pull off just a few years ago, could soon become reality.  

After graduating from the University of Texas with a Master’s in Mechanical Engineering, John worked at Sandia National Labs, where he focused on R&D projects for the Department of Energy, Department of Defense, National Institute of Standards and Technology, and other federal agencies. His experience includes nuclear weapons testing, missile guidance (Advanced Cruise Missile), air-borne and space-borne imaging systems (Predator UAV), and semiconductor manufacturing. John

January 10, 2012 – Marketwire — Teledyne Microelectronic Technologies, a business unit of Teledyne Technologies Incorporated, will expand its optical packaging portfolio in a partnership with Zephyr Photonics. The companies will package Zephyr Photonics’ proprietary vertical-cavity surface-emitting laser (VCSEL) technology with Teledyne Microelectronics Technologies’ multi-chip module (MCM) and fiber optic assembly technologies.

The companies’ resulting optical interconnect technologies will meet bandwidth and harsh-environment requirements for defense, aerospace, commercial aviation, and oil and gas applications. Zephyr Photonics’ proprietary high-temperature VCSELs can withstand temperatures over 155

January 10, 2012 — Inari Berhad, semiconductor packaging services provider, signed a memorandum of understanding (MOU) to acquire 100% of the equity of Amertron Global, an investment holding company incorporated in the Cayman Islands. The businesses, Amertron Incorporated in the Philippines and Amertron Technology (Kunshan) Co. Ltd in China, provide microelectronics and optoelectronics manufacturing services.

The Amertron Global Group employs approximately 3700 employees in facilities located in the Philippines and China with about 26,700 square metres of manufacturing floor space. Based on audited financial statements for the 6 months financial period ended 30 June 2011, Amertron Global registered net sales of USD66.2 million and profit after tax of USD2.9 million for the half year period. Learn more about Amertron at http://www.amertron-global.com/index.html.

The acquisition of Amertron Global is in line with the Inari Group