Tag Archives: Advanced Packaging

November 1, 2011 – Invensas and Allvia have agreed to a patent asset transfer and collaborative development of 3D IC packaging technology, though the description and terms are somewhat nebulous. (We’re awaiting further clarification from both companies.)

Here’s what we know from the official PR statement:

— Invensas is buying 64 patents from Allvia, mostly involving 3D ICs and packaging — namely through-silicon via (TSV) and silicon interposer ("2.5D") technology.
— The two firms have entered into "a two-year collaborative partnership" to further develop technology and IP in 3D IC packaging.

Updated 11/2:  Here’s what we know from a quick email back-and-forth with Invensas and Allvia reps:

— The patent transfer is for everything Allvia owns: silicon interposer for system-on-silicon, TSV, plus micro bumping for wide IO mobile and 3DS DRAM, confirmed Invensas president Simon McElrea. However, Allvia retains a "back license" to offer the IP to other customers. Essentially it’ll continue as a foundry business for any licensees, including Invensas. (McElrea adds that Invensas will hire 3-5 extra 3D engineers.)

— Allvia will continue as an "independent" and "separate" entity. CEO Sergey Savastiouk sees this deal as a way to "allow our interposer and TSV technology to reach the market more broadly and more quickly," adding "support and marketing outreach" to help it get more customers. Moreover, Allvia cleaves off the IP side of its business plan to focus on the manufacturing side. "Someone else will have a task to monetize Allvia IP and to aggressively license and enforce it as well as co-develop future IP," he noted.

"2.5D and 3D are the next technology nodes on DRAM and mobile technology roadmaps," McElrea explained in an email. The Allvia patent purchase & dev agreement will "strengthen our position to license our existing and new customers in our served markets — in short, where they go, we will be."

November 1, 2011 — 2.5D, 3D and Beyond – Bringing 3D Integration to the Packaging Mainstream will take place November 9 in Santa Clara, CA. The MEPTEC conference follows the trend of 3D (through-silicon vias [TSV]) and 2.5D packaging (side-by-side die interconnection on a silicon interposer) moving from roadmap to factory production.

Large, vertically integrated and volume-driven companies are using these advanced packaging technologies for new products, like stacked memory, or ASIC, ASSP, FPGA, and standard product designs. Opportunities include solving latency and bandwidth issues in high-end systems and combining different silicon processes or disparate functions such as MEMS, image sensors, and optics.

MEPTEC

October 31, 2011 — ON Semiconductor Corporation (Nasdaq:ONNN) believes that its SANYO Semiconductor division’s Thai operations in the Rojana Industrial Park in Ayutthaya, Thailand have been severely damaged by the flood. Another facility in Bang Pa In, previously unaffected, is now flooded. ONNN says none of its employees in Thailand have been endangered by flood waters on-site.

Operations at Rojana remain suspended, and ONNN has not been able to enter the 160000sq.ft. site, which employs 2000 people. The company believes it will be unable to re-start semiconductor probe, assembly and test operations at Rojana indefinitely. The flood damage is likely to exceed On Semi’s $50 million of potential insurance proceeds at Rojana.

Production is being moved to other facilities within and outside the global ON Semiconductor manufacturing network. Certain products will be sourced from alternative assembly and test locations beginning in Q4 2011, while more complex production transfers may take multiple quarters to be restored to full production capacity.

The newly flooded Bang Pa In location has had to suspend operations and evacuate. The ONNN equipment is located above the ground floor, but the company is not yet able to assess damage to the 8000sq.ft. location. 150 employees work here.

Rojana Industrial Park produced approximately 10-12% of ON Semiconductor

October 31, 2011 – PRNewswire — Flash memory provider Spansion Inc. (NYSE:CODE) will consolidate its 2 semiconductor assembly and test services (SATS) operations, closing its facility in Kuala Lumpur, Malaysia, to reduce costs by about $30 million annually.

John Kispert, Spansion president and CEO, referenced the "global economic challenges" in announcing the cost-cutting measure. Spansion emerged from bankruptcy in May 2010. TI took over a Spansion fab in Japan later that year.

Spansion released operating results for its third fiscal quarter ended September 25, 2011. On a U.S. GAAP basis, Spansion reported net sales of $258.2 million, operating income of $23.2 million, and net income of $7.3 million. On a non-GAAP basis, net sales totaled $258.2 million, adjusted operating income was $46.7 million and adjusted net income was $30.3 million. For the fourth quarter of 2011, Spansion estimates U.S. GAAP net sales in the range of $205 million to $225 million, GAAP net loss per share of ($1.12) to ($0.53).

Upon emergence from bankruptcy on May 10, 2010, Spansion adopted fresh start accounting in accordance with U.S. GAAP. The adoption of fresh start accounting resulted in Spansion becoming a new entity for financial reporting purposes, whereby the U.S. GAAP financial statements on or after May 10, 2010 are not comparable to the financial statements prior to that date. Fresh start accounting required resetting the historical net book values of Spansion’s assets and liabilities to the related fair values. References to "Successor" refer to Spansion and its consolidated subsidiaries after May 10, 2010, after giving effect to the cancellation of old common stock issued prior to May 10, 2010, the issuance of new common stock and settlement of existing debt and other adjustments in accordance with the reorganization plan, and the application of fresh start accounting. References to "Predecessor" refer to Spansion and its consolidated subsidiaries prior to May 10, 2010.

Spansion (NYSE: CODE) offers a broad Flash memory product portfolio. For more information, visit http://www.spansion.com.

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October 28, 2011 — Semiconductor test equipment maker Multitest debuted the Quad Tech concept, next-generation vertical contact technology with a barrel-less architecture.

The design has 4 continuously engaged internal contact points. Quad Tech features high current capabilities, high bandwidth and low inductance. A large mechanical compliance window accommodates stack height tolerances.

Probe life and cleaning intervals are improved by the design, which enables excellent plating, Multitest reports.

Currently, Multitest offers Mercury, Gemini, and Gemini Kelvin probes based on Quad Tech.

Multitest is a designer and manufacturer of final test handlers, contactors and load boards used by integrated device manufacturers (IDMs) and final test subcontractors worldwide. For more information about Multitest

October 28, 2011 – PRNewswire — Global Unichip Corp. (GUC; TW:3443) refined its business and technology model to become a full-service, flexible ASIC company. President Jim Lai refers to the model as GUC’s branded Flexible ASIC Model, covering SoC integration, implementation methodologies, and integrated manufacturing.

"Going forward, we will focus on penetrating specific segments inside the mobile, networking, computing, and consumer electronics markets where we are establishing design expertise and domain knowledge," Lai said.

Also read: Design your own ASIC

The company works with traditional ASIC designs and customized projects, providing 28nm and 40nm designs. Over the past few years, GUC has dedicated resources to developing advanced technology, low-power design expertise, a robust segment-specific IP portfolio and system-in-package (SiP) technology. Global Unichip Corp. can provide the integrated services of an IDM and a la carte services (IP licensing and customization, system-on-chip [SoC] design, physical implementation, design consultation and licensing, design for test [DFT]/design for manufacturing [DFM], package design, and supply chain management).

GUC is strongly aligned with TSMC as a foundry partner and has developed close relationship with packaging and testing companies. On the IP and tool side, GUC has strengthened its ARM hardening capabilities and has developed strong ties with Synopsys and Cadence.

GUC was ranked 14th largest ASIC company in 2010, with $327 million revenue, by the Gartner Group. GUC jumped 2 spots in the rankings from 2009.

GUC will continue to provide local ASIC, design, and business services through its global operations in China, Europe, Japan, Korea, North America, as well as from its headquarters in Taiwan. For more information, go to www.globalunichip.com.

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October 27, 2011 — ACM Research Shanghai, Ltd., introduced the integrated Ultra iSFP stress-free polishing (SFP) semiconductor manufacturing tool for 65-45nm copper (Cu) interconnects, improving through silicon vias (TSV) with better heat dissipation. SFP’s electrochemical mechanism is combined with ultra low down force chemical mechanical planarization (ULCMP) and thermal flow etch (TFE) to avoid damaging the underlying device structure while boosting performance.

The Ultra iSFP LDCMP uses endpoint detection to ensure a continuous 150nm Cu film, protecting the underlying low-k structure. A brush clean removes large particles and a space-alternating phase shift (SAPS) megasonic clean removes tiny particles and oxide. An in-tool non-contact component measures Cu thickness. SFP then selectively removes the non-recess Cu to the barrier, followed by a bevel cleaning step. The wafer finally enters the TFE process where the barrier is removed after pre-heat, and the wafer is cooled. An equipment front end module (EFEM) brings the wafer to the front opening unified pod (FOUP).

The Ultra iSFP forms SiO2-based air gap interconnect structures with a traditional SiO2 dielectric and damascene process and an automatic alignment structure, with no hard mask required. SFP is able to control global Cu line recess and dishing by using a pre-measured Cu film thickness map. There is no erosion or deformation to the dielectric layer and barrier during SFP. Air-gap interconnect structures are selectively formed in narrow line spaces for reportedly better heat dissipation and mechanical strength. Air gap interconnect structures can be fabricated with copper line-widths of less than 0.2

October 27, 2011 – Marketwire — Levi & Korsinsky is bringing a class action lawsuit against OmniVision Technologies Inc. (NASDAQ:OVTI) on behalf of stockholders that allege that OmniVision failed to disclose properly the loss of an exclusive contract with Apple for image sensors, in-house production delays, as well as other counts.

The complaint alleges that OmniVision and certain of its officers and directors misrepresented and/or failed to disclose that: (a) the Company had lost its exclusive contract with Apple Inc. ("Apple") regarding the supply of imaging sensors for the Apple iPhone; (b) delays in the development of its 8-megapixel product line threatened its financial prospects; (c) competition within the smartphone industry threatened the Company’s leadership position; (d) as a result of the aforementioned, defendants lacked a reasonable basis for their positive statements about the Company and its prospects.

Also read: Ziptronix accuses Omnivision, TSMC of patent infringement  and OmniVision brings wafer-level lens fab in-house, for $45 million

On August 25, 2011, OmniVision announced its results for the fiscal first quarter of 2012, provided guidance for the fiscal second quarter of 2012 that was well below analyst expectations and also disclosed delays in the production of its new 8-megapixel product line. The next day, OmniVision’s stock declined $7.55 per share, 30.4%, on heavy trading volume.

The case is brought in the United States District Court for the Northern District of California on behalf of purchasers of OmniVision Technologies Inc. common stock between August 27, 2010 and October 13, 2011. For more information, visit http://zlk.9nl.com/omnivision-technologies or contact Joseph E. Levi, Esq. at [email protected] or (877) 363-5972.

Levi & Korsinsky has expertise in prosecuting investor securities litigation and extensive experience in actions involving financial fraud and represents investors throughout the nation, concentrating its practice in securities and shareholder litigation. Internet: www.zlk.com.

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EV Group (EVG) launched a suite of temporary bonding and debonding (TB/DB) equipment modules that support ZoneBOND technology.  ZoneBOND defines two distinctive zones on the carrier wafer surface with strong adhesion in the perimeter (edge zone) and minimal adhesion in the center zone.  As a result, low separation force is only required for carrier separation once the polymeric edge adhesive has been removed by solvent dissolution or other means.

EVG is also pursuing an

October 26, 2011 — North Dakota State University, Fargo, researchers have developed a packaging technology using Thermo-Mechanical Selective Laser Assisted Die Transfer (tmSLADT) to reduce the size and cost of microelectronics packages.

Laser-Enabled Advanced Packaging (LEAP) can be scaled to high volumes, and is a contactless assembly method for ultrathin semiconductor chips onto rigid and flexible substrates. NDSU researchers have successfully implemented LEAP to fabricate a functional electronic device on a flexible substrate.

Figure 1. Microelectronics packaging developed at North Dakota State University, Fargo. Laser-Enabled Advanced Packaging (LEAP) uses Thermo-Mechanical Selective Laser Assisted Die Transfer (tmSLADT).

The technology has been under development by the Advanced Electronics Packaging research group at the North Dakota State University Center for Nanoscale Science and Engineering (CNSE), Fargo, N. D., since 2008. The research group is led by Dr. Val Marinov, associate professor of manufacturing engineering; and includes Dr. Orven Swenson, associate professor of physics at NDSU; Ross Miller, research engineer apprentice; and CNSE research staff, graduate students and undergraduate research assistants.

The laser-assisted packaging process selectively and rapidly places ultra-thin (<50