Tag Archives: Advanced Packaging

September 29, 2011 — Samsung Electronics Co. Ltd. developed a high-performance 64GB embedded memory with 64Gb NAND. The package contains an 8 die stack in a low profile for smartphones, tablets and other mobile devices.

Samsung showcased the package at the 8th annual Samsung Mobile Solutions Forum held at the Westin Taipei. The company also introduced a 32nm dual-core application processor, Exynos 4212; an ultra high-speed LPDDR3 memory; and advanced CMOS image sensors, including a 1/8.2-inch 1.2 Megapixel (Mp) imager and a 1/2.3-inch 16Mp high-sensitivity imager.

The 64GB embedded multimedia card (e-MMC) houses Samsung

September 27, 2011 — Seiko Epson Corporation (TSE:6724) introduced the IP-2000 inkjet semiconductor marking system to print identification data, such as the manufacturer’s name or a production number, on the surface of a semiconductor package.

The system prints faster and more clearly than laser engraving, protecting the chip inside the semiconductor package from damage. Semiconductor packages are "smaller and thinner," said Hideo Hirao, responsible for Epson’s Factory Automation Division, and require protection from die breakage and chipping, and cuts from lasers engraving too deeply. Since the system does not need printing plates, it can be used for small-lot production.

The IP-2000 cleans the package surface, then uses Epson’s proprietary Micro Piezo technology to apply high-visibility white ultraviolet (UV)-cured ink, also developed by Epson. Ultraviolet irradiation is undertaken simultaneously with printing to solidify the ink.

Epson is a global imaging company offering printers and 3LCD projectors for business and the home, to electronic and crystal devices. The Epson Group is led by the Japan-based Seiko Epson Corporation. Learn more at http://global.epson.com/

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September 27, 2011 – Marketwire — Cascade Microtech Inc. (NASDAQ:CSCD) completed the sale of its test socket manufacturing business for a purchase price of $550,000 to R&D Interconnect Solutions, a wholly owned subsidiary of R&D Circuits, based in Brooklyn Park, MN.

Cascade’s board of directors also authorized a stock repurchase program under which up to $2,000,000 of its common stock may be repurchased. Shares may be purchased from time-to-time in the open market or in privately negotiated transactions. The timing and actual number of shares purchased will depend on a variety of factors, including market conditions, corporate and regulatory requirements, and alternative business and investment opportunities. Repurchases under the program will be funded from available cash. The program does not require the Company to acquire any particular amount of common stock, and the program may be commenced, suspended or terminated at any time or from time-to-time at the Company’s discretion without prior notice.

Cascade Microtech will not purchase any stock under the repurchase program until it announces its financial results for its third quarter on November 1, 2011.

The sale of CSCD’s test socket business, and this share repurchase program, will help bring Cascade Microtech’s stock value up and build long-term value for shareholders, said Michael Burger, president and CEO.

Cascade Microtech Inc. (NASDAQ:CSCD) makes precision contact, electrical measurement and test products for integrated circuits (ICs), optical devices, etc. For more information, visit www.cascademicrotech.com.

R&D Interconnect Solutions specializes in design and production of high-performing sockets and interconnect products for testing of packaged ICs. It is wholly owned by R&D Circuits. For more information on R&D Circuits, visit www.rdcircuits.com.

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September 27, 2011 — Ziptronix announced just before SEMICON Taiwan that its low-temperature direct oxide bonding technology — Zibond, used for constructing backside-illuminated (BSI) structures in image sensors — was licensed by Sony. In a podcast interview with ElectroIQ.com, Ziptronix president & CEO, Daniel Donabedian, and company CTO, Paul Enquist, discussed both the wafer bonding technology and what the Sony deal means in the podcast below.


 

Because adhesives do not have high bonding energy at low temperatures, the result is high distortion, therefore, these materials are not usable for scaling smaller pixel sizes, said Enquist. Conversely, the company

September 26, 2011 – Earlier this month, Invensas Corp., a wholly-owned subsidiary of Tessera Technologies (Nasdaq: TSRA) demonstrated the dual-face down (DFD) implementation of its new multi-die face-down (xFD) packaging technology at the Intel Developer’s Forum (IDF, San Francisco, CA). The new technology targets the increased DRAM capacity and performance now needed by data centers because of rapid growth in multi-core processing and computing virtualization. The company is also targeting notebook computers, tablets and smart phones that need better battery life with a reduced form-factor.

Simon McElrea, president of Invensas, spoke with SST in a podcast interview about the wire bond-based packaging technology that mounts integrated circuits (ICs) upside down and staggers them in a "shingle-like" configuration, so the wire bonds poke through the bottom of the substrate. This gives an electrical advantage: "Because we remove spacers and face-up wire bonds, you get a super thin package that aids in heat transfer," he said. "And because you’ve staggered the die, you get heat transfer through the bottom chip as well as the top chip, without having to take all the heat through the die stack." The company says that heat transfer in the DFD package is improved 20%-30% in comparison to conventional dual-die packages (DDPs).

The company reports that the new packaging decreases the overall component size with a 25%-35% savings in vertical height over conventional solutions, and enhances electrical performance with a 50%-70% improvement in speed-bin yield (Figure 1). "This is based on data from thousands of parts," McElrea told SST. Keeping both die with very short interconnects results in the equivalent of single-die performance, though there are multiple die in the package: "Instead of dumbing down the performance of the multi-chip package to your slowest chip — the top chip — you get the performance of the silicon itself," he said.



Figure 1: Sort yield advantage comparing DFD packaging vs. conventional DDP packaging. (Source: Invensas)

McElrea explained that xFD technology costs less to manufacture than conventional multi-die DRAM packages because it uses a parallel process flow — i.e., all the chips are stacked at the same time in one station, and then all the die are wire-bonded at the next station, so all of the pads are exposed in the stacking structure. Cost reductions also come from a significant reduction in gold and other material usage. Furthermore, the package is manufactured on existing wire bond assembly lines (Figure 2).



Figure 2: Dual-die DRAM package structure comparison. (Source: Invensas)

September 23, 2011 — Research and Markets released "Wafer Packaging Fab Database," providing a global overview over 150 companies’ 250+ mid-end semiconductor packaging houses. Small R&D and prototype lines are also listed. Data includes wafer-level packaging (WLP) activity and installed capacities.

Flip chip wafer bumping and wafer-level chipscale packaging (WLCSP) make up the mainstream of WLP. On the leading edge are through silicon via (TSV) for 3D WLP, 2.5D interposers, fan-out WLP (FOWLP) and other technologies that require new capacities and capabilities.   

The database references more than 250 fab locations worldwide with technical information on wafer bumping, re-distributed layers (RDL), passivation, through-silicon via (TSV), and "mid-end" capabilities, and wafer-level packaing capabilities in general.

The database targets equipment & material suppliers looking for customer opportunities, fabless/fab-lite semiconductor companies looking to outsource, and other users.

WLP technologies distribution can be sorted by players, technology type, country, business model, investment & growth evaluation. Users can view the companies performing a certain packaging technology, and study players manufacturing/outsourcing strategy and supply chain. Others can identify and source new WLP service suppliers for their wafer-scale packaging needs. 20+ graphs are included to illustrate global trends.

Sample of companies listed in the database (IDMs, OSAT, foundries, MEMS, R&D Lab, etc.)
Wafer bumping houses:   
NEPES  

ChipBond  

FCI

 OSAT:   
ASE   

SPIL   

STATS ChipPac  

Wafer packaging houses:   
Xintec  

China WLCSP   

Nemotek  

OptoPac

 R&D Lab & prototype lines:   
CEA LETI  

IMEC  

RTI

MEMS IDM/foundries:   Silex  

Dalsa   

APM

 TSV foundries:   
ALLVia  

EPWorks 

 IC manufacturers (IDM):   
Texas Instruments  

STMicroelectronics 

Samsung 

 CMOS foundries:   
TSMC   

Globalfoundries   
UMC

For more information, visit
http://www.researchandmarkets.com/product/5def06/wafer_packaging_fab_database

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September 22, 2011 — Rogers Corporation’s (NYSE:ROG) Board of Directors elected Bruce D. Hoechner as the materials company’s new president and CEO, effective October 3, 2011. Hoechner’s past positions were with Rohm and Haas and Dow Chemical.

Hoechner also will join Roger’s Board of Directors. Current company leader Robert D. Wachob will become Chairman of the Board of Directors in this transition. Wachob and the Board of Directors have been executing this CEO succession plan for about 2 years. Wachob plans to retire sometime in 2012.

Hoechner comes to Rogers after 5 years in Shanghai, China, with Rohm and Haas Company and Dow Chemical, which acquired Rohm and Haas in 2009. Hoechner spent 28 years with Rohm and Haas.

His roles have included president, Asia Pacific region, Dow Advanced Materials Division with regional revenues of more than $2 billion, and a number of specialty chemical global business units.

Wachob set the strategic direction of Rogers, said William E. Mitchell, Lead Director of the Rogers Corporation Board of Directors. Hoechner’s experience and global business expertise make him "well suited to continue to successfully execute the Company’s vision."

Hoechner holds a Bachelor of Science degree in Chemical Engineering from Penn State University and is a graduate of the Wharton Management Certificate Program at the University of Pennsylvania.

Rogers Corporation (NYSE:ROG) is a global technology leader in specialty materials and components that enable high performance and reliability of consumer electronics, power electronics, mass transit, clean technology, and telecommunications infrastructure. For more information, visit www.rogerscorp.com.

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September 22, 2011 — X-RAY WorX GmbH introduced electronically controlled venting valves for open X-ray tubes. This avoids the manual venting typically performed during X-ray tool maintenance. The new venting method considers the turbo pump’s rotation speed and automatically optimizes tube venting.

X-RAY Worx asserts that the automatic venting process protects the turbo pump from damage and reduces downtime for X-ray system maintenance.

The company is also introducing 240kV microfocus X-ray tubes, the XWT-series with 240kV acceleration voltage, for computed tomography (CT) systems and penetration of higher wall-thicknesses in two- and three-dimensional X-ray analysis.

The high voltage technology used for the new 240kV X-ray tubes has been certified by the original supplier. The acceleration voltage of 240kV is available for almost all types of microfocus X-ray tubes of the XWT-series offered by X-RAY WorX.

X-RAY WorX makes microfocus X-ray tubes for high-resolution X-ray analysis of electronics, aerospace and automotive products. X-RAY WorX supports users of microfocus X-ray systems with a broad range of services ranging from preventive maintenance and repair to the supply of spare parts and trainings. Go to www.x-ray-worx.com

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September 21, 2011 – BUSINESS WIRE — Samsung LED’s mid-power 2323 LED package exceeded 6,000 hours of independent, EPA-recognized 3rd-party IES LM80 testing. Samsung LED will provide LM80 test data upon request.

The standard IES LM-80-2008 defines the method for testing LED lamps, arrays, and modules to determine their lumen depreciation characteristics. It aims to establish uniform test methods for LED comparisons. The standardized test also enables LED luminaire and lamp manufacturers to satisfy ENERGY STAR Lumen maintenance requirements and lessens the qualification time for ENERGY STAR qualification while using the Samsung LED 2323 LED package.

Also read: LED test standards, packaging material challenges

Samsung LED

September 20, 2011 — The first annual Global Interposer Technology Workshop (GIT 2011) will take place November 14-15 at Georgia Institute of Technology (GA Tech), convening industry experts, global academic researchers, and student leaders to share interposer technology research, development, applications, markets and manufacturing infrastructure.

Interposers are used to create "More than Moore" 3D or 2.5D semiconductor packaging.

To present at the conference, submit a title for consideration (presentation or poster) by October 2 at http://www.prc.gatech.edu/git2011/papers.html. Selected submitters will be notified by October 15.

Technical sessions will cover electrical and mechanical design, silicon and glass interposers, chip- and board-level interconnect, interposer applications and markets, and the manufacturing infrastructure for these technologies.

The plenary keynote lineup is as follows:

  • Subramanian Iyer, IBM – "Silicon Inteposers: The First Step Towards Three Dimensional Integration"
  • Doug C.H. Yu, TSMC – "Semiconductor Paradigm Shift and the Advantages of Foundry Integration"
  • Suresh Ramalingam, Xilinx – "Stacked Silicon Intereconnet: Road to Production"
  • Jerome Baron, Yole – "Interposer markets and Applications"
  • Rao Tummala, Georgia Tech – "3D Packaging Perspective at Georgia Tech 3D ICs vs 3D Interposer"

The event will feature posters presented by students along with the industry, research, and academia speakers.

GIT 2011 is sponsored by IEEE, CPMT, IMAP, iNEMI, and SEMI. Learn more at www.prc.gatech.edu/git2011.

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