Tag Archives: Advanced Packaging

July 13, 2012 — At SEMICON West 2012, this week in San Francisco, CA, the working groups of the International Technology Roadmap for Semiconductors (ITRS) held 3 sessions (TechXPOTs) outlining 2012 updates to the roadmap. Check out the updates to the front-end, scaling roadmap working groups here.

The ITRS undergoes major revisions on odd-numbered years. 2012 being an even-numbered year, very little change occurred to the Overall Roadmap Technology Characteristics (ORTC). However, within the working groups, some updates were worth noting.

Also read: 2011 ITRS: DRAM, 3D Flash, MEMS, nano-scaling steal the show

First, the changes to the ORTC, presented at the TechXPOT by Bob Doering. Of interest were changes focused directly or indirectly on 450mm. ITRS has moved the forecast production start date to 2015-2016. The definition of

July 13, 2012 — SEMICON West, this week in San Francisco, CA, hosted 3 TechXPOT sessions on the International Technology Roadmap for Semiconductors (ITRS, http://www.itrs.net/) 2012 update. At the back-end technologies session, roadmapping for More than Moore was addressed as both a philosophical and technical matter.

Also read: 2011 ITRS: DRAM, 3D Flash, MEMS, nano-scaling steal the show

Introducing the back-end-focused working group presentations, Bob Doering, representing the Overall Roadmap Technology Characteristics (ORTC), said that the Roadmap is not just about scaling anymore. Patrick Cogez, presenting More than Moore, picked up this thread, saying that the long-time focus on semiconductor scaling now has a partner, diversification, in More than Moore process technologies. More than Moore — encompassing advanced wafer-level and 3D packaging, micro electro mechanical systems (MEMS), and related microelectronics technologies — are harder to roadmap than CMOS technologies. Scaling semiconductor nodes has always offered the combined benefits of faster, cheaper, smaller, lower-power chips (Moore

July 11, 2012 – PRNewswire – SEMICON West — International consortium SEMATECH qualified the GEMINI automated wafer bonding system from EV Group (EVG) through its systematic, rigorous Equipment Maturity Assessment (EMA) implemented within SEMATECH’s 3D Interconnect program and ISMI’s EMA team. The assessments of several tools are designed to determine equipment readiness for high-volume manufacturing (HVM) of 3D integration technologies. EVG

July 10, 2012 — ULIS, a manufacturer of high-quality infrared (IR) imaging sensors, marked its 10-year anniversary with a EUR20 million investment in a new state-of-the-art facility to meet increasing market demands for IR technology.

The IR sensor facility will boost ULIS

July 9, 2012 – PRNewswire — Ultratech Inc. (Nasdaq:UTEK), a leading supplier of lithography and laser-processing systems used to manufacture semiconductor devices and LEDs, formed ‘exclusive supplier’ and ‘preferred tool vendor’ agreements with several top-tier advanced packaging companies around the world.  Combined, these companies account for almost 60% of the electroplated flip chip market that Ultratech addresses.

Also read: Challenges in Flip Chip Assembly

These agreements, along with the recent acquisition of over 200 U.S. and foreign advanced packaging patents, strategically position Ultratech to meet the lithography packaging requirements for the future device nodes of its global customer base.  They additionally underscore Ultratech’s ongoing commitment to provide its customers with leading-edge technology solutions and low cost-of-ownership advantages.

Ultratech Vice President, Advanced Packaging Technology/Nanotechnology Markets Manish Ranjan explained, "Ultratech has maintained its leading position in AP for almost 10 years.  Several of our customers have signed multi-year agreements that range from ‘exclusive supplier’ to ‘preferred tool vendor’ because they understand the technical and economic advantages our tools deliver for advanced volume manufacturing.  These agreements highlight the close working relationship that Ultratech has with its strategic customers.  These long-term relationships provide valuable insight for the development of market-specific features that enable our customers’ next-generation devices.  Building on the recent acquisition of AP patents and the multi-year vendor agreements, Ultratech will continue to work to develop lithography systems that meet its customers’ leading-edge, advanced packaging needs."

The AP300 300-mm lithography system is built on Ultratech’s customizable Unity Platform

July 9, 2012 — STATS ChipPAC Ltd. (SGX-ST:STATSChP), a leading semiconductor test and advanced packaging service provider, brought its fcCuBE advanced flip chip semiconductor packaging technology with copper column bumps, bond-on-lead (BOL) interconnection, and enhanced assembly processes into high-volume manufacturing (HVM) for multiple customers. STATS ChipPAC expanded its assembly processing capabilities to address a wider spectrum of bump pitch ranges from >200

July 9, 2012 — Semiconductor test equipment supplier Multitest installed the first Multitest Plug & Yield integrated hardware set up for testing 3D semiconductor packages at a customer. The Plug & Yield design enables highly parallel electrical in-process test of stacked dies during the assembly process of 3D packages.

The hardware set up comprises a Multitest InStrip3D, a test interface board, and a contacting solution based on vertical spring technology. The system will be used to electrically test partial stacks during assembly of a mobile SoC.

The integrated test solution uses a Multitest load board, which has fine-pitch, high layer count PCBs to support this 0.4mm pitch array application in a high-pin-count multi-site configuration. In close cooperation with the customer, the mechanics of the test were redesigned to accommodate the increased forces from the highly dense pogo array of approximately 6000 pins.

The InStrip3D, part of Multitest