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By James Amano, International Standards, SEMI

The SEMI International Standards Committee, at their SEMICON West 2017 meeting, approved the transformation of the existing 3D Stacked IC Committee and Assembly & Packaging Committee into a single, unified 3D Packaging and Integration Committee. Emerging technologies will be accommodated into the scope of the new committee, as North American TC Chapter Co-Chair Sesh Ramaswami (Applied Materials) explains: “Multi-die integration, horizontally and vertically, leveraging substrate, fan-out, interposer and TSV technology is our future. Hence, the new charter and scope will enable the committee to be of more value to the industry.”

Charter:

To explore, evaluate, discuss, and create consensus-based specifications, guidelines, test methods, and practices that, through voluntary compliance, will:

  • include the materials, piece parts, and interconnection schemes, and unique packaging assemblies that provide for the communication link between the semiconductor chip and the next level of integration, either single- or multi-chip configurations. It relates to the technologies for heterogeneous and other multi-chip packaging such as Fan-out/Fan-in Wafer Level Packaging, Panel Level Packaging, Three-Dimensional Stacking IC, device embedded packaging, flexible electronics technology
  • promote mutual understanding and improved communication between users and suppliers, equipment, automation systems, devices, and services
  • enhance the manufacturing efficiency, capability and shorten time-to-market and reduce manufacturing cost

Scope:

To develop standards for semiconductor devices, including processed wafers, chips, or multi-chip configurations to the next level of integration, either in single- or multi-chip configurations.

  • materials needed for 3D applications, including prime silicon and glass wafers, temporary and permanent bonding material, specifications needed for processed wafers and/or chips to enter an integration step, etc.
  • the materials related to the elements of, interconnection schemes, and unique packaging assemblies that provide for the communication link between device and packaging.
  • the technologies for heterogeneous and other multi-chip packaging such as Fan-out/Fan-in Wafer Level Packaging, Panel Level Packaging, Three-Dimensional Stacking IC, device embedded packaging, and flexible electronics technology
  • metrologies to support these 3D integration and packaging technologies

Masahiro Tsuriya (iNEMI), Japan Co-Chair, further emphasizes “The new 3D Packaging & Integration Committee will be able to contribute to the advance of new, innovative semiconductor packaging technologies.”

The global committee currently has chapters active in Japan, North America, and Taiwan, which all meet throughout the year. To get involved, please join the SEMI International Standards Program at: www.semi.org/standardsmembership.

Synopsys, Inc. (NASDAQ: SNPS) today announced that the Synopsys Design Platform has been fully certified for use on Samsung Foundry’s 28FDS (FD-SOI) process technology. A Process Design Kit (PDK) and a comprehensive reference flow, compatible with Synopsys’ Lynx Design System, containing scripts, design methodologies and best practices is now available. For Samsung Foundry’s latest differentiated process offering, support for bias throughout the Design Platform flow has been thoroughly verified and certified to achieve optimal power and performance tradeoffs.

“FD-SOI technology offers one of the best power, performance, and cost tradeoffs,” said Jaehong Park, senior vice president of the Foundry Solutions Team at Samsung Electronics. “Samsung Foundry’s 28FD-SOI technology allows designs to operate both at high and low voltage making it ideal for IoT and mobile applications. Moreover, the FD-SOI technology exhibits the best soft error immunity, and, therefore, is well suited for applications that require high reliability such as automotive. Availability of certified Synopsys Design Platform, PDK and reference flow will allow our mutual customers to accelerate adoption of our 28FDS technology.”

“Our long standing, close collaboration with Samsung Foundry starts very early, allowing Synopsys to refine tools and flows enabling customers to achieve desired performance and power targets,” said Michael Jackson, corporate vice president of marketing and business development for the Design Group at Synopsys. “Certification of the Synopsys Design Platform, complete with PDK and reference flow helps our mutual customers to rapidly design with confidence for Samsung Foundry’s 28-nm FD-SOI process.”

Flex Logix Technologies, Inc., a supplier of embedded FPGA IP and software, today announced it has won the TSMC Open Innovation Platform’s Partner of the Year Award 2017 in the category of New IP for its EFLX embedded FPGA IP product.

“We are honored to win this prestigious award as it highlights the close alignment with TSMC that Flex Logix has achieved with its EFLX platform: EFLX embedded FPGA is available for TSMC 40nm, 28nm and 16nm process nodes with array sizes from 100 to >100K LUTs with options for DSP and any size/type of embedded RAM,” said Geoff Tate, CEO and co-founder of Flex Logix. “Flex Logix has worked closely with TSMC since the company was founded in 2014 and is proud to meet TSMC’s rigorous standards as an IP Alliance Member.”

Embedded FPGA is a new type of semiconductor IP enabling high-volume chip designers to incorporate reconfigurable logic to allow chips to be updated even in-system to adapt to new standards, new protocols, new algorithms and to customize chips for customers faster and more cost effectively than mask changes.

The award was presented during a ceremony at this year’s TSMC Open Innovation Platform Ecosystem Forum on September 13, 2017 in Santa Clara. Tate and Senior Vice President of Engineering Cheng Wang accepted the award on behalf of Flex Logix.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced new capabilities that complete its holistic, integrated design flow for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology. Additionally, Cadence has unveiled enhancements for TSMC’s chip-on-wafer-on-substrate (CoWoS) advanced packaging technology. The complete InFO flow and enhanced CoWoS design methodologies enable design teams to efficiently complete the development process, from planning to analysis across multiple dies.

Completed InFO Design Flow

The Cadence® tools that have been enhanced to complete the TSMC InFO flow include the Quantus™ QRC Extraction Solution, Physical Verification System (PVS), and the Voltus™ Sigrity™ Package Analysis solution. Additional tools in the flow include OrbitIO™ Interconnect Designer, System-in-Package (SiP) Layout, Sigrity XtractIM™ technology, Tempus™Timing Signoff Solution, Sigrity PowerDC™ technology and Sigrity PowerSI® 3D-EM Extraction Option. With the completion of the flow, system-on-chip (SoC) designers can now:

  • Create virtual interface blocks and automate parasitic extraction, enabling package-level cross-die timing analysis: Cadence provides the first available platform that offers cross-die coupling extraction via the Quantus QRC Extraction Solution and PVS, enabling InFO designers to efficiently complete timing analysis with the Tempus Timing Signoff Solution at the package level.
  • Perform power DC and root mean square (RMS) electromigration (EM) and signal EM analysis: The Voltus Sigrity Package Analysis solution provides an integrated platform for power analysis across multiple dies and InFO designs.

CoWoS Reference Flow Enhancements

Cadence has also developed enhancements to the TSMC CoWoS reference flow. The new capabilities within the CoWoS refence flow enable designers to perform:

  • Integrated electromagnetic interference (EMI) analysis that enables analysis of the CoWoS system: Cadence is now offering an updated Sigrity EMI flow with automatic design merging, enabling integrated EMI analysis, as well as broadband-frequency-dependent S-parameter simulation, allowing for E/H-field analysis of the CoWoS system.
  • Static/dynamic IR analysis from a single environment: Voltus IC Power Integrity Solution now allows designers to do static/dynamic IR analysis across die and silicon interposers concurrently, while also analyzing power EM (dynamic/static) and signal EM (peak/RMS/average) for both dies and interposers within a single tool environment.
  • Correct cross-die interface alignment among dies and interposers: The PVS design rule checking (DRC) and layout versus schematic (LVS) capabilities provide cross-die DRC and power/signal connectivity checks, ensuring the cross-die interface has the correct alignment among the dies and interposers.
  • Thermal analysis across the CoWoS package, allowing accurate thermal runway predictions and reduced EM pessimism: The Voltus IC Power Integrity Solution and Sigrity PowerDC technology enable designers to do layer-based thermal analysis across the CoWoS package, which includes automated power map generation for all die within the solution and layer-based temperature map generation.
  • Parasitic extraction for silicon interposers, enabling timing and electrical analysis: The Quantus QRC Extraction Solution offers performance RC extraction, generating Standard Parasitic Exchange Format (SPEF) data for cross-die timing analysis. Additionally, Cadence Sigrity XcitePI™ technology provides RCLK extraction for frequency domain, signal integrity and power integrity simulation.

“We see a strong demand from both mobile and high-performance computing customers wanting to quickly deploy systems based on TSMC’s advanced packaging technologies,” said Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group at Cadence. “Through our close working relationship with TSMC, we have completed TSMC InFO design flow and enhanced TSMC CoWoS reference flow, enabling our mutual customers to further shorten design and verification cycle times so they can get to market faster.”

“The Cadence solution for InFO technology enables our customers to deliver designs with increased bandwidth within small form factors,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “With these enhancements, the integrated full-flow addresses the market need for faster design and verification cycles. Additionally, the new capabilities added to the Cadence solution for CoWoS supports our customers who want to utilize this holistic reference flow for advanced packaging projects.”

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $33.6 billion for the month of July 2017, an increase of 24.0 percent compared to the July 2016 total of $27.1 billion and 3.1 percent more than the June 2017 total of $32.6 billion. All major regional markets posted both year-to-year and month-to-month increases in July, and the Americas market led the way with growth of 36.1 percent year-to-year and 5.4 percent month-to-month. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Worldwide semiconductor sales increased on a year-to-year basis for the twelfth consecutive month in July, reflecting impressive and sustained growth for the global semiconductor market,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Sales in July increased throughout every major regional market and semiconductor product category, demonstrating the breadth of the global market’s recent upswing, and the industry is on track for another record sales total in 2017.”

Year-to-year sales increased in the Americas (36.1 percent), China (24.1 percent), Asia Pacific/All Other (20.5 percent), Europe (18.9 percent), and Japan (16.7 percent). Month-to-month sales increased in the Americas (5.4 percent), Asia Pacific/All Other (2.8 percent), China (2.7 percent), Japan (2.1 percent), and Europe (1.2 percent).

To find out how to purchase the WSTS Subscription Package, which includes comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, please visit http://www.semiconductors.org/industry_statistics/wsts_subscription_package/. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2017 SIA Databook: https://www.semiconductors.org/forms/sia_databook/.

Jul 2017

Billions

Month-to-Month Sales                              

Market

Last Month

Current Month

% Change

Americas

6.59

6.94

5.4%

Europe

3.16

3.20

1.2%

Japan

2.98

3.04

2.1%

China

10.41

10.69

2.7%

Asia Pacific/All Other

9.50

9.77

2.8%

Total

32.64

33.65

3.1%

Year-to-Year Sales                         

Market

Last Year

Current Month

% Change

Americas

5.10

6.94

36.1%

Europe

2.69

3.20

18.9%

Japan

2.60

3.04

16.7%

China

8.61

10.69

24.1%

Asia Pacific/All Other

8.11

9.77

20.5%

Total

27.13

33.65

24.0%

Three-Month-Moving Average Sales

Market

Feb/Mar/Apr

May/Jun/Jul

% Change

Americas

6.08

6.94

14.2%

Europe

2.99

3.20

7.3%

Japan

2.88

3.04

5.7%

China

10.13

10.69

5.6%

Asia Pacific/All Other

9.21

9.77

6.0%

Total

31.29

33.65

7.5%

Flex Logix Technologies, Inc., the supplier of embedded FPGA IP and software, today announced that it has joined the TSMC IP Alliance Program included in TSMC’s Open Innovation Platform.

Flex Logix has worked closely with TSMC since Flex Logix was founded in 2014 and now has its EFLX Embedded FPGA IP and software tools available for TSMC 16FFC/FF+, TSMC 28HPM/HPC and TSMC 40ULP/LP. For each EFLX IP core in each process, Flex Logix has designed, fabricated and validated a validation chip to demonstrate full-speed, high utilization performance and power specs over the full temperature and voltage operating ranges. Flex Logix has worked with TSMC to ensure its documentation, design methodology, validation chip architecture and testing all meet TSMC’s rigorous standards to become an IP Alliance Member.

EFLX embedded FPGA arrays are available on these TSMC processes in a wide range of sizes from 100 LUTs to >100,000 LUTs with options for DSP/MAC and any type/size RAM. Flex Logix will implement EFLX embedded FPGA on any additional TSMC process node as TSMC customers request. Over time, Flex Logix expects EFLX to be available on every node from 180nm to 7nm.

“Flex Logix offers high density, high performance, scalable embedded FPGA,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “We see good customer activity and interest in this emerging Semiconductor IP category and are pleased to have Flex Logix as an IP Alliance Member.”

Embedded FPGA is a new type of semiconductor IP enabling high-volume chip designers to incorporate reconfigurable logic to allow chips to be updated even in-system to adapt to new standards, new protocols, new algorithms and to customize chips for customers faster and more cost effectively than mask changes. Applications for embedded FPGA exist for networking, wireless base station, data center, deep learning, microcontroller, IoT, aerospace/defense and a range of other markets.

“We are proud to be joining the TSMC IP Alliance and appreciate TSMC’s support in helping us achieve membership,” said Geoff Tate, CEO of Flex Logix. “Our customers are in fab, in design, and in evaluation of EFLX embedded FPGA for a wide range of applications and our IP Alliance membership will enable us to support them even better going forward.”

FlexTech, a SEMI strategic association partner, will host a one-day Flexible Hybrid Electronics and Sensors Automotive Industry workshop in Detroit, Michigan on September 13, 2017 to explore how FHE adds functionality, decreases weight and impacts design. Automotive and electronics industry leaders will gather to discuss the market demands and challenges with automotive technology and present disruptive changes brought by flexible hybrid electronics (FHE) and sensors.

The forum will breakdown the topic into four key areas: OEM applications; market analysis and forecasts; challenges to integration; and solutions for Tier 2 and Tier 3 suppliers. Speakers include representatives from SBD Automotive, Fiat-Chrysler Group LLC, Velodyne LiDAR, Lumitex, Alpha Micron, NextFlex, Auburn University, Universal Instruments, Interlink Electronics, Georgia Institute of Technology, DuPont Photovoltaics & Advanced Materials and more.

“This forum is an excellent opportunity to discover the possibilities of flexible electronic systems incorporating advanced semiconductors, MEMS, and sensors, which will provide lightweight, sensor networks that conform, curve, and possibly more.  New automotive applications in this area will enable wholly new approaches for the in-cabin driving experience,” said Dr. Melissa Grupen-Shemansky, CTO for Flexible Electronics & Advanced Packaging at SEMI | FlexTech.

Company tours to Ford and a networking dinner are scheduled for September 12, 2017. For more information on the forum and how to register visit the event websiteat www.semi/org/en/FHE-forum-summary.

STMicroelectronics (NYSE: STM) has announced the integration of its contactless NFC technology with MediaTek’s mobile platforms. This creates a complete solution for handset developers to design next-generation smartphones capable of supporting tightly integrated NFC mobile services.

Mobile payments are expected to see triple-digit growth in the coming years, with contactless transport ticketing also rising fast in Asia, notably in China’s largest cities.

By integrating ST’s NFC chipset with the MediaTek mobile platforms, the two partners help mobile OEMs overcome key technical challenges such as antenna design and integration, antenna miniaturization, and bill-of-material optimization while assuring interoperability with payment terminals in locations like retailers and transportation hubs.

MediaTek is the world’s second-largest supplier of mobile-handset solutions, and with the addition of ST’s technology can demonstrate high contactless performance relative to alternative platforms.

“ST will provide its NFC technology to MediaTek, to deliver high contactless performance solutions to OEMs with a focus on cost and integration optimization through smaller antennas and reduced bill of materials,” said Marie-France Florentin, Group Vice President, General Manager, Secure Microcontroller Division, STMicroelectronics. “While ST has for years been providing to customers its own robust NFC and RFID technology, the ST21NFCD is the first device from ST to integrate the market-proven booster technology ST recently acquired.”

About ST’s Mobile-Transaction (NFC) Technology:

Mobile payments and other contactless applications are primarily enabled by Near-Field Communication (NFC) technology, as found in contactless-payment cards and payment terminals. ST’s NFC chipset, or System-in-Package, solves the challenges of achieving a robust wireless connection over extended communication distances to make mobile payments easy, dependable, and private, while protecting against cybersecurity threats including eavesdropping and hacking.

ST’s latest NFC Systems-in-Package ST54F and ST54H comprise the ST21NFCD NFC controller with active load modulation for extended range with ST33G1M2 and ST33J2M0 embedded secure element (eSE), and operating system.

 

Toshiba Corporation (TOKYO:6502) (Toshiba) is in continuing negotiations with three consortia of potential purchasers of Toshiba Memory Corporation (TMC): the Innovation Network Corporation of Japan, Bain Capital Private Equity LP and Development Bank of Japan consortium; a consortium that includes Western Digital; and a consortium that includes Hon Hai. At this point, Toshiba has not made any decision to reduce the pool of candidate purchasers of TMC.

There have been media reports speculating that Toshiba will make a decision on Aug 31 at Toshiba’s Board of Directors meeting. While Toshiba exercised its best efforts to reach a mutually satisfactory definitive agreement with one of the consortia seeking to purchase TMC, the negotiation with each consortium has not reached the point which will allow Toshiba’s Board of Directors could make a decision regarding the sale of TMC.

The memory business requires timely investments, accelerated product development, and the ability to quickly ramp-up large-scale production capacity; Highly reliable memory devices are essential to meet growing demand for storage. Accordingly, Toshiba is looking for a purchaser of TMC that is able to deliver flexible, rapid decision-making and enhanced financial options, and to promote further growth of TMC’s memory business, while also being capable of contributing enough value from the sale of TMC to return the Toshiba group to positive equity.

Toshiba intends to continue negotiations with possible bidders to reach a definitive agreement which meets Toshiba’s objectives at the earliest possible date, and will announce material changes in status in a timely manner.

Silego Technology today announced shipping three billion units since its introduction of the pioneering Configurable Mixed-signal ICs (CMICs). In addition, Silego announced it shipped more than one hundred million units in the month of July.

Silego created not only the world’s first family of Configurable Mixed-signal ICs but also enabled a paradigm shift for designers. Reaching these dual milestones are further validation of the Configurable Mixed-signal IC category and how enthusiastically customers have embraced this novel approach to Mixed-signal design for volume applications.

John Teegen, Silego’s CEO, remarked, “Reaching these milestones was made possible by the innovative Silego team and our dedicated manufacturing and channel partners. It also demonstrates the trust our customers have put in Silego’s world-class operations team to get them to market quickly with quality and volume.”

Mike Noonen, Silego’s VP of WW Sales and Business Development added, “Over the past year, we have grown our business with existing customers and introduced CMICs to many new customers. These customers have discovered Silego’s clever combination of analog, digital, Non-Volatile Memory and software tools and are benefiting from a better way to design, prototype and go to production.”

Silego’s CMICs use Non-Volatile Memory to configure each device and integrate analog, digital logic, and power functions, which allows design engineers to eliminate traditional standard linear, passive and discrete components from their system. CMICs enable original equipment manufacturers, or OEMs, in high-volume applications to cost-effectively deliver their products to market faster and with greater design flexibility.

Since the introduction of the CMIC, Silego has developed five generations of CMIC silicon and design tools.

Recently Silego announced the new SLG46580, further expanding the GreenPAK™ (GPAK) family of Configurable Mixed-signal Integrated Circuits (CMICs). This newest GPAK is targeted to support power systems in wearable and handheld market segments. This device is both highly integrated and highly flexible, and can provide a rich set of features, including voltage monitoring, power sequencing, reset functions and low drop-out regulators (LDOs), that are configurable in settings and interconnect. This device is the second in the series of parts designed to create “Flexible Power Islands” (FPI).