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Global DRAM revenue reached a new historical high in the second quarter of 2017, reports DRAMeXchange, a division of TrendForce. Compared with the first quarter, the undersupply situation was not as severe, and OEM clients in the downstream were able to gradually extend their inventories. Nevertheless, the global ASPs of PC and server DRAM products rose by more than 10% sequentially in the second quarter, while the global ASP of mobile DRAM products showed a less than 5% gain. The smaller price increase for mobile DRAM was due to Chinese smartphone brands lowering than annual shipment targets.

“The DRAM market benefitted from the upswing in ASPs and continuing progress in suppliers’ technology migrations,” said Avril Wu, research manager of DRAMeXchange. “At the same time, suppliers do not appear to have plans to expand their production capacities in a significant scale between now and the end of the year.” The global DRAM revenue has thus kept growing, registering a 16.9% sequential increase for this second quarter.

In the third quarter, the releases of new flagship devices from first-tier smartphone brands, together with the traditional peak sales season, will trigger another wave of mobile DRAM demand. DRAM prices in general will stay on an upward trend for the remainder of 2017.

DRAMQ22017

The second-quarter revenue ranking shows Samsung firmly in its first place position. Samsung’s revenue for the second quarter came to another historical high, growing by 20.7% sequentially to US$7.6 billion. Second-place SK Hynix also posted an impressive sequential increase of 11.2%, totaling US$4.5 billion. Samsung’s and SK Hynix’s global market shares for the second quarter were 46.2% and 27.3%, respectively. Together, the two South Korean suppliers accounted for 73.5% of the world’s DRAM market. Third-place Micron’s second-quarter revenue totaled US$3.6 billion, an increase of 20.2% versus the first quarter and representing 21.6% of the global market.

In terms of operating margins, Samsung had the highest in the industry for the second quarter at 59%. Samsung benefitted from rising DRAM prices and its lead in manufacturing technology. Likewise, SK Hynix raised its operating margin from 47% in the first quarter to 54% in the second. Micron too increased its operating margin from 32.5% to 44.3% between the quarters. Since DRAM prices will keep rising and the production capacity expansion will be limited in the second half of 2017, suppliers can expect further increases in their operating margins.

In the aspect of technology migration, Samsung remains focused on developing its 18nm process. With the increase and stabilization of the yield rate, Samsung expects the 18nm to represent nearly half of its total DRAM output by the end of 2017. As for SK Hynix, the supplier is raising the yield rate and output share of its 21nm process. However, SK Hynix has also arranged for the mass production its 18nm process at the end of 2017. By the first half of 2018, SK Hynix wants to significant expand the DRAM production based on its 18nm technology.

Micron’s Taiwanese subsidiaries Micron Memory Taiwan and Micron Technology Taiwan (formerly known as Inotera) are respectively on the 17nm and the 20nm technology. Micron Memory Taiwan has steadily increased the yield rate for its 17nm process and expects at least 80% of its total DRAM output by the end of this year will be based on this technology. Micron Technology Taiwan, on the other hand, has no plan to transition to a more cutting edge technology this year. However, this subsidiary has set the target of attaining at least 50% output share for the 17nm process in 2018.

Regarding the Taiwanese DRAM suppliers, Nanya’s second-quarter revenue grew by 5.9% sequentially on the back of rising prices for specialty DRAM products. Nanya has formally begun mass producing DRAM on its 20nm process and is on track to achieve a total DRAM capacity of 30,000 wafer starts per month by the end of 2017.

Powerchip’s DRAM revenue for the second quarter fell by 2.5% compared with the prior quarter because of wafer loss caused by the moving of its 25nm processing equipment.

Winbond’s second-quarter DRAM revenue rose by 3.7% sequentially as the supplier also profited from rising prices for specialty DRAM products. Winbond has no immediate plan to increase DRAM wafer starts as it is focused on meeting the strong NOR Flash demand. However, the supplier has scheduled the mass production of DRAM on its 38nm technology for the second half of 2017. The increase in output due to the ramp-up of the 38nm process will make a positive contribution to Winbond’s future DRAM revenue results.

Top five product segments driving the first annual double-digit IC market upturn since 2010.

IC Insights has revised its outlook and analysis of the IC industry and presented its new findings in the Mid-Year Update to The McClean Report 2017, which originally was published in January 2017. Among the revisions is a complete update of forecast growth rates of the 33 main product categories classified by the World Semiconductor Trade Statistics organization (WSTS).

ICInsights1

Figure 1 shows the complete ranking of IC products by forecasted growth rate for 2017. Topping the chart of fastest-growing products is DRAM, which comes as no surprise given the strong rise of average selling prices in this segment throughout the first half of 2017.  IC Insights now expects the DRAM market to increase 55% in 2017 and lay claim as the fastest-growing IC product segment this year. This is not unfamiliar territory for the DRAM market.  It was also the fastest-growing IC segment in 2013 and 2014. Remarkably, DRAM has been at the top and near the bottom of this list over the past five years, demonstrating its extremely volatile nature (Figure 2).

ICInsights2

The Industrial/Other Special Purpose Logic segment is projected to grow 32% and two automotive-related IC categories—Automotive Special Purpose Logic (48%) and Automotive Application Specific Analog (18%)—are also on course for growth that will exceed the 16% expected of the total IC market. There are more IC categories that are forecast to show positive growth in 2017 (29) compared to 2016 (21), but only the top five market segments mentioned above are forecast to exceed the total IC market growth in 2017, indicating top-heavy market growth. Another five segments (two analog categories, two MCU segments, and Computer and Peripherals—Special Purpose Logic) are forecast to show double-digit growth in 2017, though less than the 16% forecast for the total IC market this year.

Additional details and discussion regarding the updated IC forecasts for the 2017-2021 timeperiod are covered in IC Insights’ Mid-Year Update to The McClean Report 2017.

The global semiconductor advanced packaging market is expected to grow at a CAGR of 8.45% during the period 2017-2021, according to the “Global Semiconductor Advanced Packaging Market 2017-2021” report by Research and Markets.

The latest trend gaining momentum in the market is changes in wafer size. The semiconductor industry has seen a drastic transition in wafer size over the last five decades (1910-2016). The industry is focusing on producing larger diameter wafers, which is expected to cut down the manufacturing cost by 20%-25%.

According to the report, one of the other major drivers for this market is complex semiconductor IC designs. The number of features and functionalities offered by consumer electronic devices is on the rise as electronic device manufacturers look to differentiate their offerings from those of competitors.

Further, the report states that one of the major factors hindering the growth of this market is rapid technological changes. The rapid technological advancements in wafer processing have always been a major challenge faced by vendors in the semiconductor advanced packaging market. The semiconductor industry is continuously seeing transitions, such as the miniaturization of nodes and the increase in wafer sizes with respect to ultra-large-scale integration (ULSI) fabrication technology.

Worldwide semiconductor capital spending is projected to increase 10.2 percent in 2017, to $77.7 billion, according to Gartner, Inc. This growth rate is up from the previous quarter’s forecast of 1.4 percent, due to continued aggressive investment in memory and leading-edge logic which is driving spending in wafer-level equipment (see Table 1).

“Spending momentum is more concentrated in 2017 mainly due to strong manufacturing demand in memory and leading-edge logic. The NAND flash shortage was more pronounced in the first quarter of 2017 than the previous forecast, leading to over 20 percent growth of etch and chemical vapor deposition (CVD) segments in 2017 with a strong capacity ramp-up for 3D NAND,” said Takashi Ogawa, research vice president at Gartner.

According to Gartner’s latest view, the next cyclical down cycle will emerge in 2018 to 2019 in capital spending, compared with 2019 to 2020 in the previous quarter’s forecast. “Spending on wafer fab equipment will follow a similar cycle with a peak in 2018. While the most likely scenario will still keep positive growth in 2018, there is a concern that the growth will turn negative if the end-user demand in key electronics applications is weaker than expected,” said Mr. Ogawa.

Table 1: Worldwide Semiconductor Capital Spending and Equipment Spending Forecast, 2016-2020
(Millions of Dollars)

2016

2017

2018

2019

2020

Semiconductor Capital Spending

70,568.9

77,794.5

77,443.5

71,814.8

73,239.5

Growth (%)

9.1

10.2

-0.5

-7.3

2.0

Wafer Fab Equipment, Including Wafer-Level Packaging

37,033.1

43,661.0

43,690.4

40,515.8

41,342.7

Growth (%)

11.4

17.9

0.1

-7.3

2.0

Other Semiconductor Capital Spending

33,535.8

34,133.5

33,753.2

31,299.0

31,896.8

Growth (%)

6.8

1.8

-1.1

-7.2

1.9

Source: Gartner (July 2017)

This research is produced by Gartner’s Semiconductor Manufacturing program. This research program, which is part of the overall semiconductor research group, provides a comprehensive view of the entire semiconductor industry, from manufacturing to device and application market trends.

For an increasing number of designs, companies are finding it beneficial to design their own ASICs with system-on-a- chip (SoC) complexity. For reasons of cost reduction, quality improvement, IP protection and security, a full turn-key ASIC can be achieved for $1-5 million, particularly if the design can be built using mature technology nodes.

To further explore this topic, we asked questions from three leading experts in the field. Participating in the Q&A are:

• Michel Villemain, CEO, Presto Engineering, Inc.
• Guillaume Etorre, VP Engineering, Devialet
• Venkata Simhadri, CEO, Gigacom Semiconductor

Q: What is the decision-making process for deter- mining which applications are best addressed with an ASIC vs standard, off-the-shelf components? How does one calculate non-recurring engineering (NRE) costs, for example, and how does the anticipated part volume impact the decision?

Etorre: In many cases, particularly for IoT or other space-constrained designs, going with multiple standard compo- nents is simply not an option. A single chip must embed the microcon- trollers, sensors, battery management system, radios, etc. required by the application, in the smallest possible form factor.

When space is available, a standard component approach can be more appropriate to meet tight deadlines or to address situations where demand for the product is unproven. It can also serve as a stop-gap to serve the market immediately while a lower-cost ASIC solution is being designed.

If demand for the product is proven, a net present value calculation over a range of scenarios (best, typ., worst case for volumes and schedule for instance) will provide guidance on the best approach. An ASIC typically carries higher NRE (design, tapeout, qualification, test) but yields lower unit cost than an off-the-shelf solution. Depending on anticipated volumes and cost of capital, the lower unit cost of an ASIC will outweigh the higher NRE.

Simhadri: Primarily two factors can impact a company’s decision to design its own ASIC.
1. Competitive advantage – If the company is building its system using off-the- shelf components, competition can quickly reproduce it and you are only left with software as the differentiating factor. In this situation, you must have your own ASIC to protect your IP.
2. Cost – When addressing large volume markets the unit cost becomes an important factor and the only way to cut down the cost is to integrate/optimize the off-the-shelf components.

The typical NRE cost includes the cost of design, proto- typing (shuttle) and qualifying the part. Companies typically use a few benchmarks to justify the upfront cost.

For example, NRE cost is primarily dependent on the infrastructure (staff and tools) the customer already has in place. If the company already has a design team, EDA tools, etc. then the incremental cost might not be too high. However, without a design infrastructure already in place, it’s going to be a lot more time- consuming and costly. In this case, it is much easier to work with an ASIC design house to have all the infra- structure and some of the building blocks put in place.

Villemain: NRE is somewhat challenging to calculate since the duration of the project is often underestimated and unpredicted issues (who really does anticipate them!) bring additional cost to such a project. One way of mitigating this is to use external sources provided on (primarily) fixed- cost engagements. Beside ROI on NRE (function of margins and volume, indeed), drivers for using ASICs include: form factor, reliability, IP, power consumption and security.

Q: What are the tools and supply chain partners needed to successfully design an ASIC solution, including EDA software, foundry, packaging and test house?

Simhadri: You need the standard EDA tools for both Analog/ Digital, if you are designing a mixed-signal chip. Typically, you will have to work with at least two EDA vendors, such as Synopsys, Cadence, or Mentor Graphics. Many of the foundries will also work with small companies, provided you show a path to volume. However, in terms of design support (pdks, libraries, etc) foundries with better design infrastructure can save significant time. If you are a start-up or doing it for the first time, it can be quite daunting to setup the relationships and you can lose quite a bit of time to get the process going. But there are ways to save time and cost by outsourcing some of the work to the right design companies and echo system partners.

Villemain: Success is a function of a combination of multiple competencies that need to work coher- ently throughout the life of the product, especially post-design: industrialization, supplier management, quality, planning, logistics and product sustaining. This typically represents more than ten different skillsets that need to be part of the extended product team.

Etorre:
• Availability of proven IP (CPU, peripherals, interconnects, digital & analog I/O,…) for the chosen technology node.
• Affordable EDA software, with specific packages for companies designing only one or two chips at any given time, for specific end-user products vs. fabless IC companies which can spread the EDA license cost over many different chip designs every year.
• Efficient turn-key supply chain partner that can abstract out the complexity of foundry, packaging, test, storage and logistics for companies that lack critical mass.

Q: With the rise of IoT, IIoT and wearables, there’s much interest in analog/mixed-signal ASICs. How are their requirements different from traditional digital designs?

Villemain: Analog/RF designs tend to be smaller in size and to require less aggressive wafer fab processes. From a design standpoint, they demand less expensive EDA tools and less costly verification. However, their characterization and test is typically more complex and requires more expertise than a purely digital equivalent. Finally, yield management can be more demanding as the equation design window vs. process window is left more to the engineers than digital products, which can use semi-automated tools.

Simhadri: The primary difference in the require- ments is power and connectivity. If the ASICs must be connected to the internet, determining which protocols you need to incorporate on to the chip makes a big difference. Power is going to be a huge differentiating factor for the wearables, and designers are looking at various power saving techniques in an effort to optimize the power. Also, the foundries are offering special process nodes like SOI to address these markets.

In addition to the standard low power techniques like voltage islands and power shut off modes, the ASIC can further optimize the power by custom- izing the IP blocks for the specific applications. For, example, serial interfaces that burn lot of power, can be optimized.

Etorre:
• Design cycle is longer for analog IP than for digital.
• It is therefore critical to choose a foundry and a node for which all or most of the required IP are available.
•Analog IP is typically not portable between foundries or between nodes without significant rework.• •Custom analog IP is therefore a significant investment that will be depreciated if a foundry change or node change is required.
• The best nodes for analog, MEMS, RF, high- voltage and digital are usually not the same.
• Selecting the most appropriate node for the applications is not a trivial task.
• Introducing new functionality in a subse- quent version of an ASIC can require a node change and therefore major redesign of analog / mixed signal circuits. Anticipating future requirements can help make better technology choices.

Q: How do mask set costs of more mature technologies (180-40nm node) compare with those of 28nm and below, and how do mask costs enter into the overall cost equation?

Simhadri: I strongly advise our customers to use shuttles to prototype the ASIC and completely qualify it before spending a huge amount on the full mask. As expected, the 180-40nm shuttle costs are signifi- cantly lower than 28/16nm.

Villemain: With verification being less of a factor for analog/RF designs, mask sets can become a significant part of NRE below 90nm. Process technology is obviously a leading factor, but in addition, process routes can be costly because of additional options or IP, implying the addition of a mask/process layer, and thus, decreasing ROI in smaller geometries. Also, cost plateaus do exist (depending on the foundries) due to equipment transition (wafer size, lithography technol- ogies, etc.)

Etorre: The mask cost ratio between older technol- ogies and more recent ones can reach 20:1. For a 180nm design, once design, qualification and test fixtures are factored in, mask cost is not a significant contributor to the overall NRE.

Q: Out of the various advantages of ASIC design — cost reduction, quality improvement, IP protection and security – how would you rank their importance. Are there other advantages to ASIC solutions?

Villemain: What we see in the industry is a combi- nation of those factors (cost reduction, quality to architect an ASIC that replaces the discrete compo- nents in the system, which can reduce the BOM improvement, IP protection and security) as a function of the market our customers are operating in. The most common drive is, of course, that of cost (ASICs usually bring a dramatic product cost reduction), although for infrastructure applications, reliability is a key criterion, while for battery-operated applica- tions, power consumption reduction is mandatory— and all are benefits of using an ASIC.

In addition, more and more IoT segments require security in order to be even just a contender in the market, and an ASIC-based solution offers both a certifiable source of design and a cost benefit as compared to standalone secured elements.

Finally, in very competitive markets, the IP differen- tiation that an ASIC provides is a huge benefit.

Simhadri: IP protection and security shall rank first, followed by cost reduction. In some cases, off-the-shelf chips may not meet the performance requirements.

Etorre:
1. Real estate savings – an ASIC-based design is much smaller than an off-the-shelf approach;
2. Cost reduction
3. IP protection
4. Quality improvement, if any – combining various
functions and technologies (analog, digital, RF, power, MEMS, etc.) on the same die can lead to lesser quality.

Q: How has your company benefitted from an ASIC approach?

Etorre: Devialet’s Analog-Digital Hybrid (ADH) audio amplification technology was first implemented with discrete components. This discrete design is used in our high-end Expert Pro amplifiers and it supports the widest range of operating conditions.

In our Phantom speakers, we had to fit the same technology is a much smaller area. We specialized the analog circuit for the specific speaker drivers used in the Phantom and we designed an ASIC to deal with the analog part of the ADH technology.

Simhadri: Gigacom has been working with a company in the industrial IoT space and building systems for sensing gases and air quality. We have worked together by 10x and reduce the area and power significantly at the same time.

Q: How has the supply chain evolved to meet this new kind of demand?

Villemain: The supply chain needs to evolve in order to focus more on the backend than the frontend. If SoC brought RFCMOS to mass adoption with connected product, IoT, relying on a sensor-specific package, must integrate a companion ASIC driver and a transceiver; System in Package back-end technologies are gaining tremendous momentum. More and more companies will design their own ASICs, on well-proven, stable fab processes. However, packaging, reliability, test and security will become prime drivers, defining not only product costs, but also the ability to ramp, yield and scale up in volume. Supply chains (and especially the management of supply chains) is evolving accordingly.

For example, until recently, building an ASIC for an IoT device required the assembly of a team of experts, each with expertise in a different part of the process. The design might be created in-house or through an outside firm, and large companies, like automotive manufacturers, might assemble whole organizations, often called “operations” departments, with the sole task of managing the production of the specialized devices they needed. For a small company, with a game-changing new product idea, the cost and delay of assembling such a team can be fatal. If a competitor beats you to market you might not get a second chance. This need for manufacturing expertise led to the creation of “outsourced operations” companies, like Presto Engineering, that can manage the entire semiconductor manufacturing process from the completion of the design to the delivery of the tested product. By reducing the risk, cost, and difficulty of the production process, companies, such as Presto, are playing a key role in accelerating the proliferation of application specific semiconductor solutions.

Etorre: By design, ASICs run in lower volumes that standard parts. The supply chain must adapt to deal with more customers running lower volumes. This creates an opportunity for companies providing turn-key supply chain services to bridge the gap between numerous mid-volume customers and tradi- tional foundries and packaging houses who only address the largest fabless IC vendors.

Simhadri: The supply chain needs some improve- ments in the following areas. The older process nodes from 180nm to 40nm have suddenly become popular for IoT applications. However, most of the PDKs and other collateral were developed for older EDA tool versions and they need to be updated. Also, most of the IP vendors are targeting their resources for developing the IP for the latest process nodes where they get the best returns on their investment. Some of this IP has to be ported back to enable the ASICs in older nodes.

Also, to bring up these ASICs, the industry needs good support for packaging and testing facilities and all the top vendors are focused on high volume and leading- edge ASICs. Companies like Presto can potentially fill the needs.

North America-based manufacturers of semiconductor equipment posted $2.29 billion in billings worldwide in June 2017 (three-month average basis), according to the June Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.

SEMI reports that the three-month average of worldwide billings of North American equipment manufacturers in June 2017 was $2.29 billion. The billings figure is 0.8 percent higher than the final May 2017 level of $2.27 billion, and is 33.4 percent higher than the June 2016 billings level of $1.72 billion.

“Through the first half of the year, 2017 equipment billings are 50 percent above the same period last year,” said Dan Tracy, senior director, Industry Research & Statistics, SEMI.  “While month-to-month growth is slowing, 2017 will be a remarkable growth year for the semiconductor capital equipment industry.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
January 2017
$1,859.4
52.3%
February 2017
$1,974.0
63.9%
March 2017
$2,079.7
73.7%
April 2017
$2,136.4
46.3%
May 2017 (final)
$2,270.5
41.8%
June 2017 (prelim)
$2,288.9
33.4%

Source: SEMI (www.semi.org), July 2017
SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.

 

Veeco Instruments Inc. (NASDAQ: VECO) announced today that CrayoNano AS, research company for ultraviolet short wavelength light emitting diodes (UV-C LEDs), has ordered the Propel Power Gallium Nitride (GaN) Metal Organic Chemical Vapor Deposition (MOCVD) System. CrayoNano will use the system to grow semiconductor nanowires on graphene for water disinfection, air purification, food processing and life science applications.

UV-C LEDs are free of harmful mercury compared to typically 20-200 milligrams of mercury found in traditional UV lamps used in these applications. They also require minimal energy to operate and have longer life cycles compared to other purification and disinfection lighting methods. The value of the global market for UV-C LEDs used in sterilization and purification equipment is growing at a CAGR of 56% from US$28 million in 2016 to US$257 million in 2021, according to the 2016~2021 UV LED and IR LED Application Market Report by LEDinside, a division of TrendForce.

“We see enormous opportunity in our focused markets and we need superior MOCVD technology to accomplish our goals,” said Mr. Morten Froseth, Chief Executive Officer, CrayoNano. “Veeco’s Propel system offers us the unique opportunity to scale to 200 mm graphene wafer sizes while maintaining superior uniformity, low manufacturing costs and long run campaigns.”

Veeco’s Propel Power GaN MOCVD system is capable of processing single 200 mm wafers or smaller (e.g., two-inch) in batch mode. The system is based on Veeco’s TurboDisc® technology including the IsoFlange™ and SymmHeat™ breakthrough technologies, which provide homogeneous laminar flow and uniform temperature profile across each wafer, up to 200 mm in size.

“The Propel Power GaN system is the best choice to deposit advanced GaN-based structures, including complex semiconductor nanowires on graphene substrates with strict process demands,” said Peo Hansson, Ph.D., Veeco’s Senior Vice President, General Manager, MOCVD. “Our Propel system offers industry leading uniformity and process cycle time, therefore providing superior productivity compared to other technologies. As a global supplier of MOCVD systems, we look forward to supporting CrayoNano and their research activities.”

Worldwide PC shipments totaled 61.1 million units in the second quarter of 2017, a 4.3 percent decline from the second quarter of 2016, according to preliminary results by Gartner, Inc. The PC industry is in the midst of a 5 year slump, and this is the 11th straight quarter of declining shipments. Shipments in the second quarter of this year were the lowest quarter volume since 2007.

“Higher PC prices due to the impact of component shortages for DRAM, solid state drives (SSDs) and LCD panels had a pronounced negative impact on PC demand in the second quarter of 2017,” said Mikako Kitagawa, principal analyst at Gartner “The approach to higher component costs varied by vendor. Some decided to absorb the component price hike without raising the final price of their devices, while other vendors transferred the costs to the end-user price.”

However, in the business segment, vendors could not increase the price too quickly, especially in large enterprises where the price is typically locked in based on the contract, which often run through the quarter or even the year,” Ms. Kitagawa said. “In the consumer market, the price hike has a greater impact as buying habits are more sensitive to price increases. Many consumers are willing to postpone their purchases until the price pressure eases.”

HP Inc. reclaimed the top position from Lenovo in the worldwide PC market in the second quarter of 2017 (see Table 1). HP Inc. has achieved five consecutive quarters of year-over-year growth. Shipments grew in most regions, and it did especially well in the U.S. market where its shipments growth far exceeded the regional average.

Table 1
Preliminary Worldwide PC Vendor Unit Shipment Estimates for 2Q17 (Thousands of Units)

Company

2Q17 Shipments

2Q17 Market Share (%)

2Q16 Shipments

2Q16 Market Share (%)

2Q17-2Q16 Growth (%)

HP Inc.

12,690

20.8

12,285

19.2

3.3

Lenovo

12,188

19.9

13,305

20.8

-8.4

Dell

9,557

15.6

9,421

14.7

1.4

Apple

4,236

6.9

4,252

6.7

-0.4

Asus

4,036

6.6

4,501

7.0

-10.3

Acer Group

3,850

6.3

4,402

6.9

-12.5

Others

14,546

23.8

15,710

24.6

-7.4

Total

61,105

100.0

63,876

100.0

-4.3

Notes: Data includes desk-based PCs, notebook PCs and ultramobile premiums (such as Microsoft Surface), but not Chromebooks or iPads. All data is estimated based on a preliminary study. Final estimates will be subject to change. The statistics are based on shipments selling into channels. Numbers may not add up to totals shown due to rounding.
Source: Gartner (July 2017)

Lenovo’s global shipments declined 8.4 percent in the second quarter of 2017, after two quarters of growth. Lenovo recorded year-over-year shipment declines in all key regions. Ms. Kitagawa said the 2Q17 results could reflect Lenovo’s strategic shift from unit share gains to margin protection. The strategic balance between share gain and profitability is a challenge for all PC vendors.

Dell achieved five consecutive quarters of year-on-year global shipment growth, as shipments increased 1.4 percent in 2Q17. Dell has put a high priority on PCs as a strategic business. Among the top three vendors, Dell is the only vendor which can supply the integrated IT needs to businesses under the Dell Technologies umbrella of companies.

In the U.S., PC shipments totaled 14 million units in the second quarter of 2017, a 5.7 percent decline from the second quarter of 2016 (see Table 2). The U.S. market declined due to weak consumer PC demand. The business market has shown some consistent growth, while early indicators suggest that spending in the public sector was on track with normal seasonality as the second quarter is typically the peak PC procurement season. However, the education market was under pressure from strong Chromebook demand.

The Chromebook market has been growing much faster than the overall PC market. Gartner does not include Chromebook shipments within the overall PC market, but it is moderately impacting the PC market. Worldwide Chromebook shipments grew 38 percent in 2016, while the overall PC market declined 6 percent.

“The Chromebook is not a PC replacement as of now, but it could be potentially transformed as a PC replacement if a few conditions are met going forward,” Ms. Kitagawa said. “For example, infrastructure of general connectivity needs to improve; mobile data connectivity needs to become more affordable; and it needs to have more offline capability.”

Table 2
Preliminary U.S. PC Vendor Unit Shipment Estimates for 2Q17 (Thousands of Units)

Company

2Q17 Shipments

2Q17 Market Share (%)

2Q16 Shipments

2Q16 Market Share (%)

2Q17-2Q16 Growth (%)

HP Inc.

4,270

30.5

4,008

27.0

6.5

Dell

3,874

27.7

3,801

25.6

1.9

Lenovo

1,848

13.2

2,207

14.9

-16.3

Apple

1,649

11.8

1,825

12.3

-9.6

Asus

447

3.2

754

5.1

-40.7

Others

1,921

13.7

2,257

15.2

-14.9

Total

14,009

100.0

14,852

100.0

-5.7

Notes: Data includes desk-based PCs, notebook PCs and ultramobile premiums (such as Microsoft Surface), but not Chromebooks or iPads. All data is estimated based on a preliminary study. Final estimates will be subject to change. The statistics are based on shipments selling into channels. Numbers may not add up to totals shown due to rounding.
Source: Gartner (July 2017)

PC shipments in EMEA totaled 17 million units in the second quarter of 2017, a 3.5 percent decline year over year. There were mixed results across various countries. Uncertainty around the U.K. elections meant some U.K. businesses delayed buying, especially in the public sector. In France, consumer confidence rose more than expected after Emmanuel Macron was elected president, however spending on PCs remains sluggish. PC shipments increased in Germany as businesses invest in Windows 10 based new hardware, and the Russian market continued to show improvement driven by economic stabilization.

In Asia/Pacific, PC shipments surpassed 21.5 million units in the second quarter of 2017, down 5.1 percent from the same period last year. The PC market in this region was primarily affected by market dynamics in India and China. In India, the pent up demand after the demonetization cooled down after the first quarter, coupled with the absence of a large tender deal compared to a year ago and higher PC prices, brought about weak market growth. The China market was hugely impacted by the rise in PC prices due to the component shortage

These results are preliminary. Final statistics will be available soon to clients of Gartner’s PC Quarterly Statistics Worldwide by Region program. This program offers a comprehensive and timely picture of the worldwide PC market, allowing product planning, distribution, marketing and sales organizations to keep abreast of key issues and their future implications around the globe.

 

Boston Semi Equipment (BSE), a global semiconductor test handler company, announced today it has received a follow on order for multiple Zeus gravity test handling systems for pressure MEMS. The order comes from a major manufacturer of tire pressure monitoring system sensors, which selected Zeus’ pressure MEMS solution for its high accuracy and throughput.

“The Zeus handler applies the pressure stimulus directly to the device while it is at the handler’s test site,” said Kevin Brennan, vice president of marketing for BSE. “This eliminates the need to hand off the package to a separate pressure unit for testing. The tool also reaches desired pressure set points faster, cycles through pressure levels in shorter times and offers a faster index time than other solutions. Combined, these advantages result in higher throughput for pressure MEMS devices, making Zeus an ideal solution.”

The Zeus is a tri-temperature handler that can be configured with up to eight test sites. Cold temperature testing is achieved using LN2 or a BSE-designed, two-stage chiller, the MR2. The Zeus offers the features and performance needed by today’s test cells at a more affordable price point.

By Paula Doe, SEMI

SEMI adds a new speaker program called “Meet the Experts” at SEMICON West (July 11-13) in San Francisco this year. Complementing the more formal TechXPOTs, “Meet the Experts” is on a smaller scale, more relaxed format, with more time for discussion, and a wider variety of speakers. We’ve invited 25 diverse experts to speak on the challenges and opportunities for the semiconductor supply chain from smart automobiles and the Internet of Things, and the smarter next-generation manufacturing technology needed to enable this smart, connected future.

What does the IoT really mean for the semiconductor world?

The exciting emerging opportunities for smart connected objects ─ from cars to industrial systems ─ that are changing our lives also mean change for our semiconductor manufacturing business, suggests Tom Walsh, president of Tokyo Electron NEXX, who will speak on the issue in the new Meet the Experts program at SEMICON West on July 12. “These new applications require many and various new materials and packaging solutions,” he says. “But the technical challenges are not as big as the economic ones —these automotive and consumer products need equipment that is cheaper than the typical advanced front end tools, and fewer tools will be required to manufacture some of the smaller die.” That means more standardized baselines platforms for packaging, and more options for creative solutions to retrofit existing tools for new applications. “Maybe we can remove some unneeded features — sort of like taking out the heated seats,” he quips, to meet a specific technical need at lower cost.

The wildcard for this new reality is augmented reality headsets. “If eye-glasses come to replace the mobile phone as consumers’ main device, that changes the world,” he notes.

Emerging industrial applications for virtual reality

In the past year the automotive industry has increasingly come to rely on virtual reality for mockups and design reviews to save the time and cost involved in making clay models, and the technology is also finding use in employee training and the semiconductor supply chain, notes David Chang, HTC director of Corporate Development and Partnerships, another speaker in the SEMICON West “Meet the Experts” program. “We’re starting to see some users in the semiconductor industry use VR for exposition displays,” he says, noting the appeal of the more immersive working demonstrations of equipment without the cost and limitations of bring actual equipment to a show. “Virtual reality isn’t just for gaming any more, but for serious business,” he contends. HTC will be demonstrating automotive and manufacturing applications of virtual reality in the Smart Journey area at SEMICON West.

Chang says the 2Kbit resolution and 90 frames/second refresh of the HTC VIVE system is now close to that of human vision, and the lighthouse base-station system that tracks the position and orientation of the head adjusts appropriately for a realistic view that makes the system sufficiently precise for serious industrial applications. It integrates with Dassault Système’s CATiA CAD software so designers can physically view their designs without extra effort.

New data base tracks packaging technologies across the changing OSAT sector

As the OSAT industry matures, the way we do packaging and assembly is changing dramatically, as advanced packaging moves more to a wafer-level technology in a more fab-like environment, and much of the growth moves to China, notes Jan Vardaman, president of TechSearch International, speaking in the Advanced Packaging program.  She’ll introduce the new Worldwide OSAT Manufacturing Site Database, developed by SEMI and TechSearch, which tracks what types of packages are made in which facilities of 120 OSATs worldwide. Based on two years of factory visits and personal interviews, this detailed analysis allows fabless companies to easily see the full options for the packaging and assembly technologies they need, and equipment and materials suppliers to quickly see the needs of customers worldwide. “I think this is one of the greatest services that SEMI can offer its audience, says Vardaman. “It will save people a huge amount of time.”

Big changes from artificial intelligence

A number of other speakers at SEMICON West will focus on the use of data analytics, machine learning, and other types of AI in enabling the emerging generation of both semiconductor applications and semiconductor manufacturing. GE Global Research Lead Machine learning researcher Weina Ge, Ericsson Research director of IoT & Analytics Zsolt Parnaki, and NVIDIA technical marketing lead Tim Wong will cover automotive and IoT applications, while Coventor CTO David Fried, Nanotronics CRO Justin Stanwix, Motivo Data Analytics CTO Luigi Capodieci, and Siemens director, Industry Solutions, PLM Software, Tim Hewitt will address uses in semiconductor manufacturing.

Speakers from Lawrence Livermore National Lab, Multibeam Corp, NeoSpectra, NXP, Quarnergy Systems, SAE, Synopsis, andYole Développement are also talking on automotive and IoT technologies. ASE, ASM Pacific Technology, Edwards Vacuum, EV Group, SPTS, and the Heterogeneous Integration Roadmap will cover next generation IC process and packaging issues.

These SEMICON West 2017 programs, included in the basic Expo Only pass, run all day within the Smart Journey demonstration area in West Hall, with its virtual and augmented reality experiences which highlight the smart, connected future.