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SUNY Polytechnic Institute (SUNY Poly), in partnership with Empire State Development (ESD), the American Institute for Manufacturing Integrated Photonics (AIM Photonics), and the New York Power Electronics Manufacturing Consortium (NY-PEMC) today announced that a number of the institution’s leading researchers, scientists from a number of SUNY Poly’s corporate partners, and New York State economic development experts will share research and development updates at the globally recognized SEMICON West 2017 conference, which is taking place July 11 through 13 in San Francisco, California.

During this year’s engagement, researchers based at SUNY Poly’s Albany campus will present progress reports for a number of initiatives it is spearheading across New York State, including updates on AIM Photonics and the NY-PEMC, which are ramping up capabilities related to the development of next-generation photonics-based technologies, quantum computing, and silicon carbide-based power electronics, respectively, in addition to spurring economic engagement activities throughout New York State.

“Empire State Development is proud to once again collaborate with our partners at SUNY Poly and Upstate New York’s economic development organizations to showcase New York State’s high-tech research, development and business growth opportunities at SEMICON West,” said Empire State Development President, CEO & Commissioner Howard Zemsky. “Our strategic approach and improved business climate are successfully attracting innovative firms and entrepreneurs, and we’re looking forward to sharing our story with attendees and business leaders from around the world, particularly those who can benefit from the cutting-edge work being done in power electronics and photonics.”

“As a leading member of the AIM Photonics and NY-PEMC initiatives that are driving R&D in key areas, SUNY Poly is proud to work with Empire State Development at SEMICON West 2017 to share current progress with industry leaders who will be attending this year’s conference and exhibition,” said SUNY Poly Interim President Dr. Bahgat Sammakia. “By partnering with world-leading corporations, institutions, and organizations in the high-tech arena to share how further collaboration can help drive innovation and growth in New York State, SUNY Poly is thrilled once again to play a significant role at SEMICON West.”

At this year’s SEMICON West conference, SUNY Poly presenters, including SUNY Poly Vice President for Research and CEO of AIM Photonics Dr. Michael Liehr and SUNY Poly Associate Vice President for Business, Wafer Processing and CMO of AIM Photonics Frank Tolic will provide updates on the SUNY Poly-led AIM Photonics initiative as it begins building and equipping the Rochester-based photonics Test, Assembly, and Packaging (TAP) facility. To date, AIM Photonics has seen increasing interest in membership, with more than 80 signed members and additional interested collaborators from across the United States, including those representing areas ranging from industry and academia to government. More specifically, AIM Photonics and SUNY Poly leaders will provide presentations on topics such as, “The integrated silicon photonics 21st century revolution,” and “Leveraging state-of-the-art fabrication to advance quantum computing technologies,” among others. In addition, presentations will also detail AIM Academy and workforce development efforts meant to ensure that AIM Photonics-related jobs will be filled from a pool of diverse, highly qualified candidates.

“As the national AIM Photonics initiative hits its stride, initializing important research and development work and the high-tech infrastructure to drive New York State’s innovative ecosystem, as well as significant R&D nodes across the United States, we are thrilled to be able to share AIM’s opportunities with the many researchers and business leaders at SEMICON West,” said Dr. Liehr. “During this year’s engagement, AIM Photonics is eager to share updates related to the development of the TAP facility in Rochester, New York, as well as its latest offerings which can enable meaningful, cost-effective collaborations via the leveraging of the initiative’s PDK (Process Design Kit) and MPW (Multi Project Wafer) capabilities.”

A New York Nanotechnology Summit, scheduled to take place Wednesday, July 12, from 8am – Noon at the PARC55 Hotel, will provide SEMICON West participants with an opportunity to network and learn more about New York State’s research and business opportunities in the nanotechnology sector, especially as it relates to semiconductor, integrated photonics, power electronics, packaging, and other nanotechnology-related R&D and commercialization efforts. Representatives from AIM Photonics, NY-PEMC, SUNY Poly, New York Economic Development Agencies, and industry leaders IBM, GE, TEL, Mentor, Infinera, Coventor, Cadence, and Eastman Business Park will offer key technology insights, program updates, and information about future partnership and business opportunities, in addition to details about shovel ready, cost-effective and efficient locations for companies that are looking for growth.

Additionally, at this year’s SEMICON West engagement, NY-PEMC representatives will also provide presentations detailing the initiative’s progress as SUNY Poly, in partnership with General Electric, drive the high volume manufacturing and packaging of power electronic devices and systems that are smaller, faster, and more efficient than current silicon-based computer chips. The presentations will offer details related to the successful first production of silicon carbide-based patterned wafers at the NY-PEMC’s 150mm SiC foundry, which was announced in February. For example, NY-PEMC’s Brian Sapp will present, “The New York Power Electronics Manufacturing Consortium: Enabling the Power Electronics Revolution,” which will offer further insight into SUNY Poly’s Albany NanoTech Complex and its power electronics capabilities, as well as the state-of-the-art power electronics packaging facility at SUNY Poly’s Computer Chip Commercialization Center (Quad-C) fab, which is located in Utica, New York, where partner Danfoss Silicon Power will package modules and power blocks for industrial, automotive, and renewable energy applications.

Complementing the various research-based presentations by AIM Photonics and NY-PEMC-focused researchers and partners, the more than 26,000 expected attendees of the SEMICON West 2017 conference and exhibition will also be able to learn more about those initiatives and SUNY Poly’s top tier resources and capabilities by visiting the New York State Pavilion in Booth #7837, which will feature representatives from SUNY Poly, Empire State Development, NY Loves Nanotech, AIM Photonics, and NY-PEMC, as well as a patterned 150mm SiC wafer produced by the consortium. At the prominently located exhibition booth, program leaders, scientists, and others will provide information about New York State’s high-tech corridor and related economic engagement incentives, as well as opportunities for interested organizations in a number of innovation-based industries. Booth number 7837 will be located in the Moscone Center’s West Hall, Level One, and representatives will be available from Tuesday, July 11 through Wednesday, July 12 from 10 a.m. to 5 p.m. and on Thursday, July 13 from 10 a.m. to 4 p.m.

SEMICON West is an annual tradeshow for the microelectronics manufacturing industries and their supply chains. There, researchers present their cutting-edge work via keynote addresses, executive panels, and technical and business sessions to attendees from around the world. In addition to the more than 600 expected exhibitors and hundreds of product displays, the event also features applications and topics ranging from micro-electromechanical systems (MEMS) to nanoelectronics and the internet of things (IoT).

Umicore’s business unit Precious Metals Chemistry today inaugurated its production unit for advanced metal organic precursor technologies used in the semiconductor and LED markets, respectively TMGa (Trimethylgallium) and TEGa (Triethylgallium). The event was attended by European and overseas customers as well as local and regional politicians. The guest of honor was Dr. Barbara Hendricks, Germany’s Federal Minister for the Environment, Nature Conservation, Building and Nuclear Safety.

Umicore’s TMGa manufacturing process is innovative and unique. It offers a more sustainable and ecological production method by minimizing hazardous side streams and material losses and optimizing yield to nearly 100%.

Dr. Lothar Mussmann, Vice-President of Umicore Precious Metals Chemistry said, “I am proud that this patented innovation has now become a world-class and industrial scale manufacturing plant. It will provide benefits for our customers and the environment and underlines Umicore’s position as a pioneer in sustainable technologies.”

Umicore Precious Metals Chemistry is the only European manufacturer of TMGa and TEGa and supplies customers across the world from its Hanau manufacturing base. Umicore Precious Metals Chemistry helps to reduce cost of ownership through its innovative approach to process chemistry and its collaborative approach with customers and end users.

About Trimethylgallium and Umicore’s manufacturing process

Trimethylgallium (TMGa) is a colorless liquid with very high vapor pressure, which boils at low temperatures. Umicore’s new production process increases the yield of TMGa in comparison with current production technologies. In this way, organic solvents can be completely dispensed with. The TMGa is prepared by chemically reacting gallium trichloride with a more efficient methylating agent in molten salt. This reduces the amount of waste per kilogram of TMGa by more than 50%, with the resulting intermediates being recycled in the process. The finished product is then used in the semiconductor industry, where it evaporates in closed systems onto a substrate. This creates, for example, environmentally friendly LED lamps.

Presto Engineering, Inc., an outsourced operations provider to semiconductor and Internet of Things (IoT) device manufacturers, announces a management expansion: Cedric Mayor has been named Chief Operating Officer (COO) and Martin Kingdon has been appointed VP Sales.

“We have experienced growing demand for IoT and related turnkey production & operations outsourcing,” said Michel Villemain, CEO, Presto Engineering. “Our expanded management team will complement our talented employee base to help meet this market demand and advance Presto Engineering into the next phase of innovation and growth.”

Mayor was previously the Chief Technology Officer for Presto Engineering. In his new role as COO, he will work with Presto’s Europe and Asia-based facilities to take customers’ new product releases from prototype to high-volume production, and through wafer procurement to finished goods. He has been with the company for more than seven years and has over a decade of experience in semiconductor design and manufacturing. A graduate of Ecole Centrale Marseille, France, Mayor has a Master’s degree in Physics and Electrical Engineering and holds several patents in chip design.

Kingdon has more than 20 years of experience in sales and marketing of semiconductor devices, IP, and test & manufacturing. Prior to joining Presto as VP Sales, Kingdon served as European sales director for the test and manufacturing services division of TT Electronics plc. Kingdon graduated from the University of York, UK, and holds a Master’s degree in Electronic Systems Engineering.

Each year at SEMICON West, the “Best of West” awards are presented by Solid State Technology and SEMI. More than 26,000 professionals from the electronics manufacturing supply chain attend SEMICON West and the co-located Intersolar. The “Best of West” award was established to recognize new products moving the industry forward with technological developments in the electronics supply chain.

Selected from over 600 exhibitors, SEMI announced today that the following Best of West 2017 Finalists will be displaying their products on the show floor at Moscone Center from July 11-13:

  • Mentor, a Siemens Business: Tessent® Cell-Aware Diagnosis – With FinFETs in high volume, finding systematic yield issues at the transistor level is important. The Tessent Cell-Aware Diagnosis technology significantly improves diagnosis of defects beyond the inter-connect and inside the logic cells. (Process Control, Metrology and Test Category; North Hall Booth #6661)
  • Microtronic Inc.: EAGLEview 5 Macro Defect Management Platform – EagleView 5 is the new, yield-enhancing, breakthrough macro defect inspection platform that was developed – and deployed in production — through collaboration with several leading device manufacturers who wanted to standardize and unify wafer defect management throughout their fab. Innovations include: dramatically improved defect detection; level-specific sorting; and integration with manual microscopes. (Process Control, Metrology and Test Category; North Hall Booth #5467)
  • SPTS Technologies Ltd: SentinelTM End-Point Detection System for Plasma Dicing after Grind – The Sentinel™ End-Point Detection System improves the control of plasma dicing processes and protects taped wafers for improved yields.  In addition to signaling exposure of the tape, Sentinel™ also detects loss of active cooling during the process to enable intervention to prevent yield loss. (Process Control, Metrology and Test Category; West Hall Booth #7617)
  • TEL: Stratus P500 – The Stratus P500 system electroplates panel substrates with wafer level processing precision.  As redistribution layers (RDL) reduce to widths below 10 µm line/space, and package sizes increase, conventional plating systems are challenged to meet system-on-package requirements. The P500 makes panel scale fine line RDL and feature filling applications possible. (Assembly/Packaging Solutions Category; North Hall Booth #6168)

Congratulations to each of the Finalists. The Best of West Award winner will be announced during SEMICON West (www.semiconwest.org) on Wednesday, July 12, 2017.

GLOBALFOUNDRIES and ON Semiconductor (Nasdaq: ON) today announced the availability of a System-on-Chip (SoC) family of devices, on GF’s 55nm Low Power Extended (55LPx), RF-enabled process technology platform. ON Semiconductor’s new RSL10 products are based on a multi-protocol Bluetooth 5 certified radio SoC capable of supporting the advanced wireless functionalities in IoT and “Connected” Health and Wellness markets.

“Bluetooth low energy technology continues to advance as the key enabler for connecting IoT devices, especially with low power consumption requirements,” said Robert Tong, vice president of ON Semiconductor’s Medical and Wireless Products Division. “GF’s 55LPx platform – with its low power logic and highly reliable embedded SuperFlash memory combined with proven RF IP – was an ideal match. The RSL10 family offers the industry’s lowest power consumption in Deep Sleep Mode and Peak Receiving Mode, enabling ultra-long battery life, and supporting functionalities like Firmware Over the Air updates. ON Semiconductor’s new RSL10 SoCs use these advanced features to address a wide range of applications including wearables and IoT edge-node devices such as smart locks and appliances.”

“GF’s 55LPx platform, combined with ON Semiconductor’s design, has delivered wearable SoC technology at 55nm, with industry leading energy efficiency,” said David Eggleston, vice president of embedded memory at GF. “This is another proof point that 55LPx is becoming the preferred choice for SoC designers that are seeking cost effective performance, low power consumption, and superior reliability in extreme environments.”

GF’s 55nm LPx RF-enabled platform provides a fast path-to-product solution that includes silicon qualified RF IP and Silicon Storage Technology’s (SST) highly reliable embedded SuperFlash memory featuring:

  • Very fast read speed (<10ns)
  • Small bitcell size
  • Superior data retention (> 20 years)
  • Superior endurance (> 200K cycles)
  • Fully qualified for Auto Grade 1 operation (AEC-Q100)

GF’s 55LPx eFlash platform has been in volume production at the foundry’s 300mm line in Singapore since 2015. The 55LPx eFlash platform is a cost effective solution for a broad range of products, ranging from wearable devices to automotive MCUs.

Customers can start optimizing their chip designs with GF’s process design kits, enabling designers to develop differentiated eFlash solutions that require cost effective performance, low power consumption, and superior reliability in extreme environments.

Queen’s University Belfast researchers have discovered a new way to create extremely thin electrically conducting sheets, which could revolutionise the tiny electronic devices that control everything from smart phones to banking and medical technology.

Through nanotechnology, physicists Dr Raymond McQuaid, Dr Amit Kumar and Professor Marty Gregg from Queen’s University’s School of Mathematics and Physics, have created unique 2D sheets, called domain walls, which exist within crystalline materials.

The sheets are almost as thin as the wonder-material graphene, at just a few atomic layers. However, they can do something that graphene can’t – they can appear, disappear or move around within the crystal, without permanently altering the crystal itself.

This means that in future, even smaller electronic devices could be created, as electronic circuits could constantly reconfigure themselves to perform a number of tasks, rather than just having a sole function.

Professor Marty Gregg explains: “Almost all aspects of modern life such as communication, healthcare, finance and entertainment rely on microelectronic devices. The demand for more powerful, smaller technology keeps growing, meaning that the tiniest devices are now composed of just a few atoms – a tiny fraction of the width of human hair.”

“As things currently stand, it will become impossible to make these devices any smaller – we will simply run out of space. This is a huge problem for the computing industry and new, radical, disruptive technologies are needed. One solution is to make electronic circuits more ‘flexible’ so that they can exist at one moment for one purpose, but can be completely reconfigured the next moment for another purpose.”

The team’s findings, which have been published in Nature Communications, pave the way for a completely new way of data processing.

Professor Gregg says: “Our research suggests the possibility to “etch-a-sketch” nanoscale electrical connections, where patterns of electrically conducting wires can be drawn and then wiped away again as often as required.

“In this way, complete electronic circuits could be created and then dynamically reconfigured when needed to carry out a different role, overturning the paradigm that electronic circuits need be fixed components of hardware, typically designed with a dedicated purpose in mind.”

There are two key hurdles to overcome when creating these 2D sheets, long straight walls need to be created. These need to effectively conduct electricity and mimic the behavior of real metallic wires. It is also essential to be able to choose exactly where and when the domain walls appear and to reposition or delete them.

Through the research, the Queen’s researchers have discovered some solutions to the hurdles. Their research proves that long conducting sheets can be created by squeezing the crystal at precisely the location they are required, using a targeted acupuncture-like approach with a sharp needle. The sheets can then be moved around within the crystal using applied electric fields to position them.

Dr Raymond McQuaid, a recently appointed lecturer in the School of Mathematics and Physics at Queen’s University, added: “Our team has demonstrated for the first time that copper-chlorine boracite crystals can have straight conducting walls that are hundreds of microns in length and yet only nanometres thick. The key is that, when a needle is pressed into the crystal surface, a jigsaw puzzle-like pattern of structural variants, called “domains”, develops around the contact point. The different pieces of the pattern fit together in a unique way with the result that the conducting walls are found along certain boundaries where they meet.

“We have also shown that these walls can then be moved using applied electric fields, therefore suggesting compatibility with more conventional voltage operated devices. Taken together, these two results are a promising sign for the potential use of conducting walls in reconfigurable nano-electronics.”

By Paula Doe, SEMI

Fabs and tool makers are starting to pay a lot more attention to suppliers of components and subsystems– as defects in these materials start to impact yields at 14nm and below. Solving these emerging issues, though, will take a collaborative effort to determine what parameters matter, how to measure them, and how to trace them back across an extended supply chain, suggests Pawitter Mangat, GLOBALFOUNDRIES director of Global Incoming Quality, one of the speakers who’ll discuss these issues in the program on component impact on yields at advanced nodes, July 11, at SEMICON West 2017.

“As we move below 22nm, even the composition of the materials in the subcomponents become critical,” he says. “But currently there is no general agreement on what the important parameters are to control for particular applications, or on how to measure these parameters with the same methods for consistent results.” The issues are often with the industrial grade raw materials from which the subcomponents are made, and these industrial chemical suppliers may be reluctant to invest in controls as the semiconductor industry represents only a tiny percentage of their business. “This means we need to look beyond our immediate suppliers to a wider ecosystem of components and material suppliers, and to extend digital traceability through this wider ecosystem as well,” he notes. “If we have an issue, we need to be able to quickly trace it back to the cause.”

“The 7nm world tends to forget that all subcomponents, everything, has been developed for other industries, not the semiconductor industry, and the makers of all these basic pumps and valves and O-rings have no way of knowing what the important parameters are to prevent defects in the final semiconductor devices,” notes Dalia Vernikovsky, CEO, Applied Seals North America, and co-chair of the SEMI Semiconductor Components, Instruments, and SubSystems (SCIS) special interest group.

She suggests the major users and suppliers get together to come up with the basic parameters for things like metal contamination, surface cleanliness or outgassing for specific components for specific processes, and then agree on a common way to measure these parameters, to enable tracing and characterizing the defects in the final devices.   This is also the first step towards specifying and controlling the parameters of the raw materials used in the components and subsystems that also matter. “If I am going to push my supplier, I have to be able to show him what the end customers’ requirement is,” notes Vernikovsky.  “This is not about individual companies’ intellectual property. It’s the basic requirement of the IC industry that we all need to meet, and then we can compete on a higher level.”

Other speakers at the Semiconductor Components, Instruments and Subsystems (SCIS) session include Norm Armour, Micron Technology, Managing Director Worldwide Facilities and Corporate EHSS; Sanchali Bhattaharjee, Intel, Engineering Manager, Global Supply Chain Management; and a panel with the speakers moderated by Dan Hutcheson, VLSI Research, CEO and Chairman. The SEMI SCIS special interest group will also have an open meeting on their current collaborative efforts July 13 at the Marriott Marquis. See www.semiconwest.org/programs-catalog/enabling-hvm-advanced-process-nodes.

Mentor, a Siemens business, today announced that it has launched the Mentor OSAT (outsourced assembly and test) Alliance program to help drive ecosystem capabilities in support of new high-density advanced packaging (HDAP) technologies like 2.5D IC, 3D IC and fan-out wafer-level packaging (FOWLP) for customer integrated circuit (IC) designs. By launching this program, Mentor will work with OSATs to provide fabless companies with design kits, certified tools, and best practices to aid in smoother adoption of these new packaging solutions that require a much tighter link between chip and package design. Mentor also announced Amkor Technology, Inc. as its first OSAT Alliance member.

Through the Mentor OSAT Alliance, members work with Mentor to create certified design kits to help customers speed up IC and advanced package development with Mentor’s Tanner L-Edit AMS design cockpit, Calibre IC physical verification platform, HyperLynx SI/PI and HyperLynx full-wave 3D tools, Xpedition Substrate Integrator and Xpedition Package Designer tools, and Mentor’s newly announced Xpedition HDAP flow.

“Mentor’s customers are pioneering technologies at the heart of IoT, autonomous driving and next-generation wired and wireless networks,” said Joe Sawicki, vice president and general manager of the Design to Silicon Division at Mentor. “Many of these companies are designing ICs that use advanced packaging from OSATs to achieve their design goals. Like the Mentor Foundry Alliance program did for accelerating foundry design kit creation, the Mentor OSAT Alliance program will help our mutual customers use Mentor’s world-class EDA portfolio to more easily implement ICs with advanced packaging technologies.”

Members of the Mentor OSAT Alliance will receive software, training, and reference flow best practices from Mentor, in addition to the opportunity for co-marketing mutual offerings.

“The next generation of IC packaging will require increased heterogeneous die integration, incorporating reduced size, weight, and improved performance and reliability,” said Ron Huemoeller, corporate vice president, research and development at Amkor. “Amkor’s Silicon Wafer Integrated Fan-out Technology (SWIFT™) package technology is designed to provide increased I/O and circuit density within a significantly reduced footprint and profile for single and multi-die applications. Being an integral part of the Mentor OSAT Alliance program will allow us to fast-track PDK development and delivery, and enable our customers to design more efficiently and predictably.”

With alliance programs for both foundries and OSATs, Mentor continues to enable the semiconductor ecosystem. The OSAT Alliance program will drive global design and supply chain adoption of these emerging advanced packaging technologies.

Amkor Technology, Inc. (Nasdaq: AMKR) today announced that it has completed the acquisition of NANIUM S.A., a provider of wafer-level fan-out (WLFO) semiconductor packaging solutions.

In its press release, Amkor said that the acquisition of NANIUM will strengthen its position in the fast growing market of wafer-level packaging for smartphones, tablets and other applications. NANIUM has developed a high-yielding, reliable WLFO technology, and has successfully ramped that technology to high volume production.

“Amkor is a leader in wafer-level CSP and high-density integrated fan-out technologies,” said Steve Kelley, Amkor’s president and chief executive officer. “With the acquisition of NANIUM, we will have an equally compelling value proposition in the low-density fan-out area. NANIUM is widely viewed as the fan-out technology leader as well as a very capable manufacturer, having shipped more than one billion WLFO packages utilizing a state-of-the-art 300mm wafer-level packaging production line.”

NANIUM employs approximately 650 people and is based in Porto, Portugal.

Racyics GmbH announced today it has launched makeChip, a design service platform, developed using GLOBALFOUNDRIES’ 22FDX process technology and supported by Cadence. Available to start-ups, design experts, research institutes, and universities, makeChip is a central gateway to design integrated circuits based on advanced semiconductor technologies.

The platform provides an IT infrastructure with a full set of EDA tool installations and technology data setup such as PDKs, foundation IP, and complex IP. All tools and design data are linked by Racyics’ silicon-proven design flow and project management system. The turnkey environment enables any makeChip customer to realize complex systems on chips (SoCs) in the most advanced technology nodes.

GF’s 22nm FD-SOI technology, 22FDX, provides advantages in power efficiency and production cost. One key factor to a successful design, leveraging the full potential while achieving shortest time-to-market, is the support of a highly experienced design enablement team.

As a part of GF’s FDXcelerator Partner Program, Racyics  makeChip will provide comprehensive support for the most advanced technologies and thus helps smaller players to realize their enormous innovative potential.

“We want to move start-ups, small and medium sized businesses, and academia to the leading-edge of the game. With makeChip, we enable them to quickly execute analog, mixed-signal and digital designs in GF’s 22FDX technology, so they can develop the hardware basis for high-volume applications in the fields of IoT and Industry 4.0,” stated Holger Eisenreich, CEO of Racyics.

“Our 22FDX technology is quickly becoming a platform of choice for market-focused applications that require low power and operational efficiency with an affordability advantage,” said Alain Mutricy, senior vice president of Product Management at GF. “This collaboration with Racyics and Cadence will help lower the barrier of entry for SMEs, start-ups, and academia.”

Access to makeChip includes a complete digital design flow with advanced silicon-proven solutions from Cadence without additional costs for non-commercial academic projects. For commercial projects, different contract agreements will be applied.

“The Cadence full-flow digital solution, is a perfect match for the makeChip design platform. Users are enabled to meet their power, performance and area targets, “ said Jens Werner, Vice President, Technical Field Operation, at Cadence. “The makeChip platform will help to grow design starts in Europe and beyond.”

Racyics provides its in-house 0.4V IP for 22FDX to makeChip customers. It is free of charge in the frame of non-commercial projects and enables platform users to be the first in the world to explore an ultra-low voltage design space and uses its unparalleled potential for energy-efficient operation.