Tag Archives: letter-ap-business

Synopsys, Inc. (Nasdaq:  SNPS) today announced that its IC Validator was successfully deployed on some of the industry’s largest and most advanced designs to accelerate design rule checking (DRC) closure. Through near-linear distributed processing and efficient resource management, IC Validator delivers industry-leading turnaround time, enabling physical signoff within hours on designs with 10 billion+ transistors. Technology advancements in the latest releases of IC Validator reduce both memory and disk usage requirements by 2x. This significant improvement in resource efficiency enables excellent performance scaling to several hundreds of CPUs by taking advantage of the smaller and more readily available machines in the customers’ existing compute farms.

“Increasing manufacturing complexity at advanced nodes makes it challenging for customers to complete physical signoff within schedule,” said Bijan Kiani, vice president, product marketing, Design Group at Synopsys. “Through high-performance scalability and readily available, optimized runsets from all major foundries, IC Validator is providing our customers with the fastest path to production silicon.”

IC Validator, part of the Synopsys Digital Design Platform, is a comprehensive and highly scalable physical signoff solution including DRC, LVS, programmable electrical rule checks (ERC), dummy fill and DFM enhancement. IC Validator is configured for today’s extremely large designs by enabling 8 CPUs with a single license. It uses both multi-threading and distributed processing over multiple machines to provide near linear scalability benefits that extend to several hundreds of CPUs. IC Validator enables coding at higher levels of abstraction and is architected for scalability to maximize utilization of mainstream hardware, using smart memory-aware load scheduling and balancing technologies.

IC Validator is a companion product to Synopsys IC Compiler™ II In-Design physical signoff. In-Design allows place-and-route engineers to perform independent signoff-quality analysis earlier, before the design is finalized and while correction can be automated. In-Design technology enables new high-productivity functionality within the place-and-route environment, including automatic DRC repair, improved timing quality-of-result with timing-aware metal fill, and rapid ECO validation. In-Design physical signoff eliminates expensive iterations with downstream analysis tools and maintains a convergent design flow to physical signoff.

StratEdge Corporation, a designer of high performance semiconductor packages for microwave, millimeter-wave, and high speed digital devices, announces the opening of its Amazon Store to sell its off-the-shelf high-frequency packages.

“It is a relatively new concept to use Amazon to sell such a highly technical and complex product,” said Tim Going, StratEdge president. “Many things have to be considered when selecting a package for a semiconductor chip. However, we believe that by providing the frequency, cavity size, number of leads, and specific information for each package, along with the photo, that this will make it easier for our customers and potential customers to purchase their packages through the store. Of course, we are also available to answer any questions via phone or email.”

StratEdge’s Amazon store is initially offering 11 packages that include hermetic molded ceramic flatpacks with combo lids, leaded surface mount DC-18 GHz packages with plastic lid and epoxy, leaded amplifier packages for both KA band and DC-23 GHz including the plastic lid with epoxy, and leadless DC-63 GHz packages including a plastic lid with epoxy. Lot sizes include either 10 or 25 pieces. The packages are shipped from StratEdge’s facility in San Diego, California and usually arrive within a week.

Additional products will be added to StratEdge’s Amazon store.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $30.9 billion for the month of March 2017, an increase of 18.1 percent compared to the March 2016 total of $26.2 billion and 1.6 percent more than the February 2017 total of $30.4 billion. Sales from the first quarter of 2017 were $92.6 billion, up 18.1 percent compared to the first quarter of 2016 but down 0.4 percent compared to the last quarter of 2016. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales saw solid sales growth in March, increasing sharply compared to last year and more modestly compared to last month,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Global sales are up 18 percent compared to last year, the largest increase since October 2010, with all major regional markets posting double-digit year-to-year growth. All major semiconductor product categories also experienced year-to-year growth, with memory products continuing to lead the way.”

Year-to-year sales increased across all regions: China (26.7 percent), the Americas (21.9 percent), Asia Pacific/All Other (11.9 percent), Europe (11.1 percent), and Japan (10.7 percent). Month-to-month sales increased in Europe (5.0 percent), Japan (3.6 percent), Asia Pacific/All Other (2.9 percent), and China (0.2 percent), but decreased slightly in the Americas (-0.5 percent).

March 2017

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.99

5.96

-0.5%

Europe

2.82

2.96

5.0%

Japan

2.77

2.87

3.6%

China

10.05

10.07

0.2%

Asia Pacific/All Other

8.77

9.02

2.9%

Total

30.39

30.88

1.6%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

4.89

5.96

21.9%

Europe

2.67

2.96

11.1%

Japan

2.59

2.87

10.7%

China

7.95

10.07

26.7%

Asia Pacific/All Other

8.05

9.02

11.9%

Total

26.15

30.88

18.1%

Three-Month-Moving Average Sales

Market

Oct/Nov/Dec

Jan/Feb/Mar

% Change

Americas

6.33

5.96

-5.8%

Europe

2.80

2.96

5.6%

Japan

2.84

2.87

0.9%

China

10.17

10.07

-0.9%

Asia Pacific/All Other

8.86

9.02

1.7%

Total

31.01

30.88

-0.4%

Rudolph Technologies, Inc. (NYSE: RTEC) announced today that two of the industry’s leading suppliers of advanced packaging services have purchased multiple Firefly Inspection Systems. The Firefly System, with Rudolph’s patented Clearfind Technology, can detect defects that are almost impossible to find using conventional imaging techniques – helping to significantly reduce yield-robbing failures in both the front- and back-end of the semiconductor manufacturing process.

“Advanced packaging is rapidly becoming a critical differentiator for mobile and Internet of Things (IoT) device manufacturers with growth in multiple technology segments. This includes fan-out wafer level packaging, which Yole Développement estimates will have a compound annual growth rate as high as 50 percent over the next three years. We are excited to enable this rapid growth in advanced packaging through reduced cost and improved reliability of next generation technologies with our new Firefly inspection solution,” said Mike Goodrich, vice president and general manager of Rudolph’s Process Control Group. “The Firefly System provides a unique combination of defect sensitivity and substrate flexibility, in a single platform, which helps our customers reduce their capital investment requirements. By including our automatic defect classification TrueADC software and yield management Discover software, these systems will deliver a complete solution for process control and quick yield learning at critical steps in advanced packaging processes.”

Mike Plisinski, chief executive officer added, “Rudolph collaborates extensively with customers early in the development cycle in order to gain a deeper understanding of their specific challenges. In doing so, we are able to leverage Rudolph’s broad technology portfolio and experience to provide a more comprehensive solution to our customers. In recent years, Rudolph has made a conscious effort to cultivate strategic relationships across our customer base to transform our focus from supplying equipment to being a process control solution partner.”

Two manufacturing service providers, a foundry and an outsourced assembly and test (OSAT) facility, have placed orders for multiple Firefly Systems for fan-out and wafer-level chip scale packaging (WLCSP) applications. The Firefly System’s Clearfind Technology, which can see critical defects that may otherwise escape detection, was an important consideration in all cases. Such defects, including un-etch metal residues that can be obscured by graininess and low-contrast organic residues, are becoming increasingly important as vias and redistribution line (RDL) features continue to shrink. A total of seven systems have been ordered, all of which will ship this year.

The new Samsung Galaxy S8 equipped with 64 gigabytes (GB) of NAND flash memory carries a bill of materials (BOM) cost that comes out to US$301.60, much higher than for previous versions of the company’s smartphones, according to a preliminary estimate from IHS Markit (Nasdaq: INFO).

After $5.90 in basic manufacturing costs are added, Samsung’s total cost to make the Galaxy S8 rises to $307.50; the unsubsidized price for a 64GB Galaxy S8 starts at around $720. The preliminary estimated total at this point is $43.34 higher than that of the Galaxy S7 previously performed by IHS Markit, and is $36.29 higher than the total build cost of the Galaxy S7 Edge, considered a better comparison to the Galaxy S8. IHS Markit has not yet performed a teardown analysis on the larger Galaxy S8 Plus.

“The higher total BOM costs for the Galaxy S8 seem to be part of a trend that reflects something of an arms race in features among Apple, Samsung and other phone manufacturers, as they all try to add new and distinguishing hardware features,” said Andrew Rassweiler, senior director of cost benchmarking services for IHS Markit. “While there are new non-hardware features in the Galaxy S8, such as a virtual assistant called Bixby, from a teardown perspective the hardware in the Galaxy S8 and that of the forthcoming new iPhone is expected to be very similar.”

The introduction of the Galaxy S8 comes at a delicate time for the embattled South Korean electronics giant, which is eager to put behind the challenges associated with the Galaxy Note 7, whose exploding batteries prompted a worldwide recall.

The latest salvo from Samsung shows how it’s keen to regain consumer confidence and attain leadership in the smartphone landscape, a nearly saturated but still highly competitive space that remains key to retaining subscriber loyalties and winning new converts.

First smartphone capable of gigabit-LTE speeds

Both the Galaxy S8 and S8 Plus feature a 10-nanometer (nm) system-on-chip (SoC) along with CAT-16 LTE modem and radio. The CDMA version of the S8, intended for use in the United States as well as in China, will feature the Snapdragon 835 chipset from San Diego-based Qualcomm. In comparison, a version of the phone featuring Samsung’s homegrown Exynos 8895 chipset will be used for the rest of the world.

The CAT-16 LTE radio allows the new Galaxy phone to aggregate three carriers of up to 20 megahertz each. Combined with 4×4 MIMO antennas and higher-order modulation of 256 QAM, the LTE modem is capable of reaching peak theoretical speeds of one gigabit per second. “Gigabit LTE is very much the marquee specification for 2017 flagship smartphones,” said Wayne Lam, principal analyst of smartphone electronics, IHS Markit. “Keep in mind that gigabit speeds are a best-case scenario and that a user’s real-world experience will be limited to what mobile networks can provide.”

New “Infinity Display” design fits better in hand

The redesigned Galaxy S8 has a tall, narrow shape that is 1.5 millimeters narrower than the previous Galaxy S7, providing slick new ergonomics while also optimizing screen real estate. The screen curves around the edges, and Samsung designers have maximized the display, relative to the size of the phone, with a 5.8-inch 2960×1440 AMOLED display and an elongated aspect ratio of 18.5:9. Compared to conventional 16:9 aspect-ratio Quad HD smartphone displays, the Galaxy S8 features an additional 15 percent more pixels in a form factor that is easier to hold in the hand. The device’s haptic engine, which provides the “click” feel for users, also has been improved for longer-duty cycles and a more dynamic response.

Double the base-model storage

Both the Galaxy S8 and S8 Plus feature 4GB of RAM and built-in storage of 64GB—twice the standard built-in storage found in the Galaxy S7 as well as the iPhone 7. Storage for the new Samsung phones can also be expanded, up to 256GB, via a microSD card. The Samsung NAND flash memory and DRAM on the S8 come in at a cost of $41.50. Rassweiler said: “While in previous years the cost per gigabyte has generally fallen in both the NAND flash and DRAM areas, we have seen rising prices in both DRAM and NAND flash recently due to some tightness in the marketplace. The cost of memory in the S8 reflects these recent market dynamics, even though we expect the erosion in memory pricing—something that occurs regularly in the memory market—to resume during the course of the year.”

Battery

The battery capacity on the Galaxy S8, at 3000 milliamp hour (mAh), is the same as that found in last year’s Galaxy S7. However, compared to the Galaxy S7 Edge, which had a 3600mAh battery, Samsung played it safe after the Note 7 incident and included a considerably less dense battery pack. Overall cost estimate for the Galaxy S8 battery pack is $4.50.

Single camera lens

Although the Galaxy S8 and S8 Plus come with new features and the latest components, each still has only a single camera in the back—essentially the same as the camera module found in last year’s Galaxy S7. Apple’s iPhone 7 Plus, the newly launched LG G6 and many Chinese OEMs are now promoting dual cameras as a key feature. Owing to the asymmetric placement of the rear fingerprint sensor, it would have been likely that a dual-camera design was scrapped at the last minute in the design cycle.

At SEMICON Southeast Asia 2017, Dr. Chen Fusen, CEO of Kulicke & Soffa Pte Ltd, Singapore, will give a keynote on digital transformation in the manufacturing sector. Chen believes that Smart Manufacturing, or Industry 4.0, is no longer hype but real, and Asia needs to get on board sooner rather than later. SEMICON Southeast Asia (SEA) 2017, held at the SPICE arena in Penang on 25-27 April, is Asia’s premier showcase for electronics manufacturing innovation.

“Digital transformation has proven to provide solutions for addressing challenges in the manufacturing industry but there is still the issue of acceptance as well as lack of skills and knowledge that needs to be addressed,” said Chen. “With disruptive technology changing our world, I expect that more companies will see the value of their investments realised as this technology accelerates the creation of more individualised products and services.”

Dr. Hai Wang from NXP Semiconductors Singapore Pte Ltd agreed that more consumer-related innovations would stem from digital transformation as demand for solutions that provide efficiency and security increases. “At NXP, we look at developing advanced cyber security solutions for the automotive industry, such as tracking and analysing intelligence around connected and automated vehicles, which will help to counter any adverse threats in real time. These innovations are real and will soon mark a shift in the future of automation and manufacturing. It is vital that we embrace the change and adapt accordingly,” he said.

Other speakers at SEMICON SEA also feel strongly about the importance of Smart Manufacturing and digital transformation. David Chang of HTC Corporation, Taiwan, sees a dramatic shift in the value of being a “smart” manufacturer to address to the rising demand in consumer products and services innovation. “We have seen virtual reality technology offered by products such as HTC VIVE(TM) really shaping the future of the world. Transformative innovations such as this will pave the way for disruptive technology to be coupled into business models to benefit consumers in the long term,” he said.

These three speakers will join a long list of thought leaders from the electronics manufacturing sector – including Jamie Metcalfe from Mentor Graphics U.S., Chiang Gai Kit from Omron Asia Pacific Singapore, Ranjan Chatterjee from Cimetrix U.S. and Duncan Lee from Intel Products Malaysia – to speak at SEMICON SEA 2017. Topics discussed will cover issues relevant to the transformation of the manufacturing industry ranging from next-generation manufacturing to system-level integration, including exhibitions that will highlight the market and technology trends that are driving investment and growth in all sectors across the region.

The conference also aims to champion regional collaboration through new business opportunities for customers and foster stronger cross-regional engagement through reaching buyers, engineers and key decision-makers in the Southeast Asia microelectronics industry, including buyers from Malaysia, Singapore, Thailand, Indonesia, the Philippines, and Vietnam.

Learn more about SEMICON Southeast Asia 2017 in Penang, Malaysia on 25-27 April: http://www.semiconsea.org/.

Optomechanical devices, which simultaneously confine light waves and mechanical waves to permit interaction between them, can be used both to study fundamental questions in physics and to sense motion in a way similar to electromechanical accelerometers. In smartphones, these electronic components switch the touchscreen between portrait and landscape when they detect rotation by the user.

According to experts in the field, however, the use of optomechanical devices to study macroscopic quantum phenomena – in which the large-scale properties of matter such as mechanical vibration are subject to the laws that govern atoms (quantum mechanics) – or to identify very subtle movements requires extremely high levels of interaction, or coupling, between light waves and mechanical waves.

A group of researchers led by Thiago Pedro Mayer Alegre and Gustavo Silva Wiederhecker at the University of Campinas’s Gleb Wataghin Physics Institute (IF-UNICAMP) in São Paulo State, Brazil, have developed an optomechanical device with a novel design that boosts the coupling between light waves and mechanical waves to higher levels than those reported for similar devices developed in the laboratory. Their work was part of research projects supported by FAPESP.

The new optomechanical device and an experimental demonstration of its functioning are described in an article published in the Optical Society of America’s journal Optics Express.

“The way we designed the device allows the levels of interaction between light waves and mechanical waves to be increased,” Alegre told.

“This means the device can both have practical applications and assist us in our basic research by helping us answer certain questions, such as what happens in the transition between the quantum microscopic world and the classical macroscopic world.”

The device created by the researchers, based on a 24-micron silicon disk supported by a silicon dioxide central pedestal so that the disk can vibrate, has a similar shape to a bullseye at the center of a shooting target, with concentric circular grooves.

Thanks to this shape, light waves and mechanical waves can be confined within the device by separate mechanisms.

The light waves are confined only at the edge of the disk by total internal reflection, an optical phenomenon whereby light within a medium such as water or glass is completely reflected from the surrounding surfaces (such as the air interface) back into the medium, provided the angle of incidence is greater than a certain limiting angle called the critical angle.

Light waves are therefore compressed near the disk edge and travel around the rings for a long time, whereas mechanical vibrations can propagate throughout the material.

However, the concentric rings create frequency regions in which mechanical waves cannot propagate, so that they are confined to the outside edge of the disk, where they interact directly with the light waves.

“Confining light waves and mechanical waves to the disk edge enables us to boost their interaction, which is useful for exploring quantum phenomena in macroscopic objects,” Alegre explained.

In devices developed by other research groups, the concentric circular grooves are used to confine light waves in the central region and not at the edge, as in the case of the device designed by the researchers at IF-UNICAMP.

Based on the finding that, like optical vibrations, mechanical vibrations can be understood as waves, Alegre’s group had the idea of using the concentric rings to confine mechanical waves at the edge of the device and make them interact more intensely with light waves in the same region.

“The point of developing the disk with this bullseye design was to prevent the mechanical mode from ‘seeing’ the central pedestal that supports the disk and allow the entire structure to vibrate, eliminating mechanical losses,” he said.

The device is highly customizable, he added, and compatible with existing industrial fabrication processes, making it a solution for the enhancement of sensors that detect force and motion, for example.

One of its potential applications is in telecommunications as an optical modulator, Alegre explained. Because the device can sense and excite mechanical vibration, it could be used as an optical switch, turning on or off a laser beam that passes through it far more efficiently than the modulating technologies used today in optical telecommunications networks.

“It was fabricated according to current industrial processes, so any group in the world could reproduce it,” he said.

Cadence Design Systems, Inc. (NASDAQ:  CDNS) today announced the release of the new Virtuoso Advanced-Node Platform supporting advanced 7nm designs. Through collaboration with early 7nm FinFET customers, Cadence has expanded the Virtuoso custom design platform with innovative new capabilities to manage design complexity and process effects introduced with this advanced-node process. The Virtuoso Advanced-Node Platform update supports all major advanced FinFET technologies with proven results, while improving designer productivity at 7nm.

To address the many technical challenges of 7nm design, the Virtuoso Advanced-Node Platform offers a variety of layout capabilities, including advanced editing with multi-pattern color awareness, FinFET grids, and module generator (ModGen) device arrays. Additionally, customers can take advantage of variation analysis in their circuit design flows utilizing Monte Carlo analysis across corners to address variability with the Spectre® Accelerated Parallel Simulator, the Virtuoso ADE Product Suite and the Virtuoso Schematic Editor.

“As a leader in mobile computing, we require the highest performance, lowest power and highest density possible to deliver innovative, advanced-node designs,” said Ching San Wu, general manager of Analog Design and Circuit Technology at MediaTek. “Through our strong collaboration and continued partnership with Cadence, we have been able to develop and deploy a custom design methodology based on the Virtuoso Advanced-Node Platform. With our recent successful tapeout, we took advantage of its many unique capabilities designed to manage the challenges presented at 7nm.”

Key features in the updated Virtuoso Advanded-Node Platform include:

  • Multi-patterning and color-aware layout: Provides essential new support of a variety of fully colored “multi-patterned” custom design flows, which are a baseline requirement for the 7nm process and enable users to be more productive in their designs.
  • ModGen device arrays: Offers designers a set of modules that have been co-developed in close collaboration with key partners to improve designer productivity and mitigate layout complexities at the 7nm process node.
  • Automated FinFET placement: Provides automatic FinFET grid placement that simplifies the overall FinFET-based coloring design methodologies needed at 7nm. By adhering to 7nm process constraints, the Virtuoso Advanced-Node Platform greatly simplifies layout creation and minimizes errors that can be pervasive when designing at 7nm, while decreasing layout design time by up to 50 percent on custom digital and analog blocks.
  • Variation analysis: Enables high-performance Monte Carlo analysis targeting FinFET technology and high-sigma analysis, which can reduce the overall time to run simulations by a factor of 10.

“Through constant innovation and strategic partnerships with industry leaders, Cadence has solidified its leading role in providing advanced-node custom design tools,” said Tom Beckley, senior vice president and general manager, Custom IC & PCB Group at Cadence. “Through our extensive work with customers such as MediaTek, we’ve been able to validate that our approaches greatly reduce the overhead inherent in designing at 7nm in order to help deliver the best possible silicon. We currently have many customers that have completed successful tapeouts and delivered production designs using the Virtuoso Advanced-Node Platform.”

A coalition of leaders from the global tech, defense, and aerospace industries, led by the Semiconductor Industry Association (SIA) and Semiconductor Research Corporation (SRC), today released a report identifying the key areas of scientific research needed to advance innovation in semiconductor technology and fulfill the promise of emerging technologies such as artificial intelligence (AI), the Internet of Things (IoT), and supercomputing. The report, titled Semiconductor Research Opportunities: An Industry Vision and Guide, also calls for robust government and industry investments in research to unlock new technologies beyond conventional, silicon-based semiconductors and to advance next-generation semiconductor manufacturing methods.

“Semiconductor technology is foundational to America’s innovation infrastructure and global technology leadership,” said John Neuffer, president and CEO of SIA, which represents U.S. leadership in semiconductor manufacturing, design, and research. “Our industry has pushed Moore’s Law to levels once unfathomable, enabling technologies that have driven economic growth and transformed society. Now, as it becomes increasingly challenging and costly to maintain the breakneck pace of putting more transistors on the same size of silicon real estate, industry, academia, and government must intensify research partnerships to explore new frontiers of semiconductor innovation and to foster the continued growth of emerging technologies. Taking swift action to implement the recommendations from the Vision report will help usher in a new era of semiconductor technology and keep America at the head of the class in technological advancement.”

Neuffer also noted concern in the tech, research, and academic communities about proposed cuts to basic scientific research outlined in the Trump Administration’s fiscal year 2018 budget blueprint. Basic scientific research funded through agencies such as the National Science Foundation (NSF), the National Institute of Standards and Technology (NIST), the Defense Advanced Research Projects Agency (DARPA), and the Department of Energy (DOE) Office of Science has yielded tremendous dividends, helping launch technologies that underpin America’s economic strength and global competiveness. The U.S. semiconductor industry invests about one-fifth of revenue each year in R&D – the highest share of any industry. Neuffer expressed the semiconductor industry’s readiness to work with the Administration and Congress to enact a budget that embraces the strategic importance of research investments to America’s continued economic and technological strength.

“Continued and predictable advancements in semiconductor technology have fueled the growth of many industries, including those historically based on mechanics such as automotive,” said Ken Hansen, president & CEO of SRC. “As the rate of dimensional scaling has slowed, the need to reinvigorate the investment in semiconductor research has become increasingly clear. Now is the time for industry, government, and academia to double down their resources and efforts to ensure the pace of renewal continues. Alternative strategies and techniques to the traditional scaling for performance are now being explored by SRC. Furthermore, with the support of SIA, SRC is building research programs that align with the Vision report, including complimentary technologies such as advanced packaging and communications. An infusion of funding is vital to expand the research breadth beyond the historical focus areas, enabling the industry to keep its promise of a continuous stream of products with improved performance at reduced cost. As industries look to future areas of growth and innovation, SIA and SRC are laying the groundwork for new discoveries through fundamental research.”

The Vision report is the culmination of work by a diverse group of industry experts and leaders, including chief technology officers at numerous leading semiconductor companies, who came together over a nine-month period in 2016-2017 to identify areas in which research is essential to progress. The report, which will be updated periodically moving forward, has active participation from the industry’s leading chip makers, fabless companies, IP providers, equipment and material suppliers, and research organizations. It will serve as a foundational guide for defining the semiconductor industry’s future research paths in 14 distinct but complimentary research areas. These areas, outlined in the Vision report, are as follows:

1. Advanced Devices, Materials, and Packaging2. Interconnect Technology and Architecture

3. Intelligent Memory and Storage

4. Power Management

5. Sensor and Communication Systems

6. Distributed Computing and Networking

7. Cognitive Computing

 8. Bio-Influenced Computing and Storage9. Advanced Architectures and Algorithms

10. Security and Privacy

11. Design Tools, Methodologies, and Test

12. Next-Generation Manufacturing Paradigm

13. Environmental Health and Safety: Materials and Processes

14. Innovative Metrology and Characterization

 

Ultratech, Inc. (Nasdaq: UTEK), a supplier of lithography, laser­ processing and inspection systems used to manufacture semiconductor devices and high-brightness LEDs (HBLEDs), as well as atomic layer deposition (ALD) systems, today announced that it has received follow-on, multiple system orders from several outsourced semiconductor assembly and test (OSAT) companies in Taiwan, Korea and China. The AP300E lithography stepper will be used for leading-edge copper pillar and wafer-level packaging (WLP) in high-volume manufacturing (HVM). Ultratech plans to begin shipping the systems in Q2 and Q3 of this year.

Ultratech General Manager and Vice President of Lithography Products Rezwan Lateef stated, “OSATs are rapidly expanding their advanced packaging capabilities to capture the strong demand for copper pillar and fan-out package solutions. These customers look to their equipment suppliers to provide highly reliable, flexible, extendible and cost-effective solutions coupled with excellent application-specific knowledge. The AP300E lithography stepper delivers on all these aspects coupled with outstanding regional support. Ultratech believes that success in the OSAT market requires local, on-site support and has greatly expanded its presence (both in personnel and infrastructure) in the Asia Pacific region with a focus on Taiwan, China and Korea. These repeat, multiple system orders across the broad OSAT spectrum are a clear validation of our market leadership position and a strong statement of continued partnership from our customers.  We look forward to working with these valued customers to meet their current production needs and to develop the applications of tomorrow.”

The AP300 family of lithography systems is built on Ultratech’s customizable Unity Platform, delivering superior overlay, resolution and side wall profile performance and enabling highly-automated and cost- effective manufacturing. These systems are particularly well suited for copper pillar, fan-out, through-silicon via (TSV) and silicon interposer applications. In addition, the platform has numerous application-specific product features to enable next-generation packaging techniques, such as Ultratech’s award winning dual-side alignment (DSA) system, utilized around the world in volume production.