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SEMI announced today that over 43,000 visitors are expected to attend SEMICON Taiwan September 7-9 at the TWTC Nangang Exhibition Hall in Taipei. Over 550 exhibitors, 16 themed pavilions, and more than 20 international forums are being readied to connect attendees with companies, people, products, and information forming the future of advanced electronics, including a major focus on advanced packaging.

Douglas Yu, senior director of Integrated Interconnect and Packaging Technology at TSMC, recently announced that TSMC needs to transition – from the world’s leading IC foundry – to the industry’s first System in Package (SiP) foundry (SEMICON West; July 2016).  Yu stated, “We are a wafer foundry, but we are doing some packaging business to survive and grow . . . Moore’s law is becoming more challenging, so we are preparing for those days.”  Sources say that TSMC’s chip packaging changes have led to improvements of 20 percent in both speed and packaging thickness and 10 percent in thermal performance.

SEMICON Taiwan is an exceptional event to learn about the latest advances in packaging. On September 7, the SEMI Advanced Packaging Technology Symposium‘s theme is “Fan Out Solutions – Cost-effective FO Solutions, 3D/SiP FO Solutions, and Fine Patterning.” Industry experts from a wide range of companies will present, including: Amkor, APIC Yamada, ASE, ASM, IEK, Kulicke & Soffa, Lam Research, Protec, Senju, SPTS, SUSS MicroTec Photonic Systems, and Ueno SEIKI.

On September 8, SEMICON Taiwan’s SiP Global Summit begins with a 2.5/3D-IC Technology Forum with presentations from TSMC, Amkor, ANSYS, ASE Group, EVG, Fraunhofer IZM, Hitachi Chemical, IBM, IMEC, NMC, and SPIL.  On September 9, the SiP Summit features an Embedded and Wafer Level Package Technology Forum, with moderators from ASM Pacific Technology, ITRI, and SPIL.

Beyond packaging, many other innovation areas such as Smart Manufacturing, Semiconductor Materials and Executive Summit –Grand Opening Keynote session which always draws the most attention will be presented in technical and business programs, as well as on the show floor at the TechXPOTs, including:

  • High-Tech Facility TechXPOT: AccuDevice, Forbo Flooring, Hantech Engineering, Lumax International, Organo Technology, Particle Measuring, Rockwell Automation, Supenergy, Techgo Industrial, Trusval Technology, VIVOTEK, Wholetech Systems Hitech, and many more
  • Materials TechXPOT: AI Technology, Atotech Taiwan, CohPros International, CSI Chemical, Nippon Pulse Motor Trading (Taiwan), Tatsuta Electric Wire & Cable, and Uniwave Enterprise
  • New Product Launch TechXPOT: AblePrint Technology, Chemleader, Creating Nano Technologies, EVG-Jointech, First Elite Enterprise, SEIPI, Sigmatek, Sil-More Industrial, and YXLON/Teltec Semiconductor Pacific
  • Smart Manufacturing TechXPOT: Balluff Taiwan, Cimetrix, Dah Hsing Electric, and Gallant Precision Machining

For more information and registration for SEMICON Taiwan, please visit: www.semicontaiwan.org/en

BY DR. ZHIHONG LIU, Chairman and CEO, ProPlus Design Solutions

Semiconductor processes have long been a mystery for many circuit designers. They didn’t need to worry about how chips were fabricated most of the time, thanks to the many EDA innovations that make their jobs easier and complex designs possible.

The success of the foundry-fabless business model over the past 20 years has been one of the main drivers of the booming of semiconductor industry. The cooperation between foundries and IC designs in fabless companies for process development worked so well that process engineers and circuit designers only needed to focus on their area of expertise. EDA flows simplified the interaction by using process design kits (PDKs) as the information carrier for circuit designs and sent tapeout databases (GDSII) back to the foundry for chip fabrication. Most designers didn’t need to dig into the process.

That was then. The designer now is forced to understand process and devices when moving to smaller nodes in order to achieve more competitive designs. Because process is the least understood, the loose link between process and design should be enhanced to improve design and tapeout confidence.

Knowing processes and devices would help designers make better use of the process platform and improve designs. Device geometries are getting smaller and new structures such as FinFET and FD-SOI are becoming mainstream leading to complicated device characteristics and SPICE models, the most critical components in the PDK. They represent a process platform’s performance and device characteristics, fundamental to good circuit design. A solid understanding of SPICE models becomes necessary to make full use of the process. This is true not only for designs at advanced nodes at 28nm beyond, such as 16nm, 14nm and10nm, but critical for some refreshed older technologies for IoT/Wearable applications.

Running a full evaluation of process and device performance would provide guidance to better select device types, optimize device sizes and bias conditions, trade-off circuit speed and power. The same logic can be applied to generic circuit designs at any technology node, such as analog
designs at 180nm or above.

This practice is used mostly within IDMs where process and design teams have fairly direct channels to work cooperatively. Recently, fabless companies strengthened links with foundries to under- stand the process and devices to improve design output or for process-circuit co-design for high-end chip designs with more aggressive speed, power and performance specifications.

These efforts are significant. Most companies don’t have the resources and time to build a dedicated team and flow and there have been no available EDA tools dedicated to helping designers understand process and facilitate process development interactions. Increasing time-to-market pressures and tough competition drive the need to a higher priority.

Without an EDA tool, current practices can easily take weeks or months to build, maintain and run a flow by creating scripts or SPICE netlists for different evaluation items. It’s practically impossible to run through the cases to generate a full picture of process platform for designers within a short turnaround time.

As a result, it’s hard to come up with a set standard for process evaluation before using it in design, as efforts can vary for different projects. For a big corporation with many design projects, dealing with multiple foundries, using multiple technology nodes and different process platforms, this type of work is critical to its success however becomes overloaded.

Furthermore, the complexity of SPICE models is exploding. Thousands of parameters in each model and a huge model library file with more than 100K lines of code are quite common. Macro models with complicated layout- dependent effects and random variations add more dimensions of complexity.

Complexity and time pressures are huge. An EDA tool to manage both would be indispensable.

One tool could use the PDK library as the input to explore, compare and verify models. It could help designers under- stand and explore the process-design space to guide process platform selection and enable quick adoption of the process and assist designs. It would help designers dig into the process from different angles, including a high-level summary of the process and device performance, device characteristics, statistical behavior and circuit performance related to the application. This should enable designers quickly adopt and make full use of a process platform that suits their needs.

In addition to the monthly Updates, IC Insights’ subscription to The McClean Report includes three “subscriber only” webcasts.  The first of these webcasts was presented on August 3, 2016 and discussed semiconductor industry capital spending trends, the worldwide economic outlook, the semiconductor industry forecast through 2020, as well as China’s failures and successes on its path to increasing its presence in the IC industry.

In total, IC Insights forecasts that semiconductor industry capital spending will increase by only 3% this year after declining by 2% in 2015.  However, driven by the top three spenders—Samsung, TSMC, and Intel—capital spending in 2016 is expected to be heavily skewed toward the second half of this year. Figure 1 shows that the combined 2016 outlays for the top three semiconductor industry spenders are forecast to be 90% higher in the second half of this year as compared to the first half.

Figure 1

Figure 1

Combined, the “Big 3” spenders are forecast to represent 45% of the total semiconductor industry outlays this year.  An overview of each company’s actual 1H16 spending and their 2H16 spending outlook is shown below.

Samsung — The company spent only about $3.4 billion in capital expenditures in 1H16, just 31% of its forecasted $11.0 billion full-year 2016 budget.

TSMC — Its outlays in the first half of 2016 were only $3.4 billion, leaving $6.6 billion to be spent in the second half of this year in order to reach its full-year $10.0 billion budget.  This would represent a 2H16/1H16 spending increase of 92%.

Intel — Spent just $3.6 billion in 1H16.  The company needs to spend $5.9 billion in the second half of this year to reach its current $9.5 billion spending budget, which would be a 2H16/1H16 increase of 61%.

In contrast to the “Big 3” spenders, capital outlays by the rest of the semiconductor suppliers are forecast to shrink by 16% in the second half of this year as compared to the first half.  In total, 2H16 semiconductor industry capital spending is expected to be up 20% over 1H16 outlays, setting up a busy period for the semiconductor equipment suppliers through the end of this year.

Further trends and analysis relating to semiconductor capital spending through 2020 are covered in the 250-plus-page Mid-Year Update to the 2016 edition of The McClean Report.

Ultratech, Inc. (Nasdaq: UTEK), a supplier of lithography, laser­ processing and inspection systems used to manufacture semiconductor devices and high-brightness LEDs (HBLEDs), as well as atomic layer deposition (ALD) systems, today announced that it has received an ‘Outstanding Supplier Award’ from SJ Semiconductor Corp. Based in China, SJ Semiconductor is a pure play Middle-End-Of-Line (MEOL) semiconductor foundry house specializing in advanced wafer-level packaging. The award was presented to Ultratech by SJ Semiconductor CEO Cui Dong on July 27, at the company’s ‘Phase-I Mass Production, Outstanding Supplier Event’ at their facility in China. This award is further validation of Ultratech’s market leadership position in the advanced packaging lithography segment.

Rezwan Lateef, Ultratech’s General Manager and Vice President of Lithography Products, stated, “Ultratech has maintained its market leadership in the advanced packaging lithography segment by offering superior on-wafer results with industry leading cost-of-ownership and reliability in high-volume manufacturing environments. In recent years, Ultratech has expanded its presence in China, both in personnel and infrastructure, to support the burgeoning Chinese OSAT market. Ultratech believes that the SJ Semiconductor ‘Outstanding Supplier Award’ is a validation of our efforts in this region. We look forward to our continued partnership and to working closely with this valued customer to meet their future production and technology requirements.”

Ultratech is a supplier of lithography steppers for advanced packaging applications that include traditional copper pillar and wafer-level packaging (WLP), as well as the more advanced fan-out WLP and 3D ICs. The AP300 family of lithography systems is built on Ultratech’s customizable Unity Platform, delivering superior overlay, resolution and side wall profile performance while enabling cost-effective manufacturing. These systems are particularly well suited for copper pillar, fan-out, through-silicon via (TSV) and silicon interposer applications. In addition, the platform has numerous application-specific product features to enable next-generation packaging techniques, such as Ultratech’s award winning dual-side alignment (DSA) system, utilized around the world in volume production.

Silicon manufacturing appears to have diminished in its luster and seems to be on the verge of extinction in Silicon Valley. The buzz today in the high tech capital of the world seems to be driven primarily by software companies; the likes of Facebook, Google, Intuit, Oracle, and LinkedIn. The traditional silicon chips seem to have stepped aside to give way for Big Data, Data Security, Mobile Apps, and Cloud Storage. The Valley which was traditionally recognized largely for its dominance in Semiconductors still boasts the highest concentration of companies involved in the design and development of silicon Integrated Circuits (ICs). However, much of the silicon wafer fabrication facilities have moved offshore, primarily to the Asia Pacific region. This has led to a score of serious risks such as loss of IP (intellectual property), lack of control over the production process, and the danger of finding these components in the gray market.

There are literally just a hand full of companies that have found a way to continue both innovating as well as “manufacturing” silicon products in Silicon Valley.  OnChip Devices, Inc. is one such company that has successfully found a way to produce a wide range of silicon components in Santa Clara, CA. The company has announced that it is now offering wafer foundry services to fabless semiconductor companies.

OnChip’s wafer foundry offers Thin Film, CMOS, and BiPolar processes and has produced more than 250 different high-volume products under the OnChip brand as well as for other companies globally. With installed capacity of over 10,000 wafers per month and current utilization of less than 30%, this fab offers high quality wafers with competitive pricing and very short turnaround time. The fab produces 4”, 5”, and 6” wafers at 2µ to 5µ BiCMOS process technology focusing primarily on Analog products.

OnChip’s wafer manufacturing facility has been granted the ISO 9001:2008 certification and strives to continuously improve its quality as well as the cycle time. The processing time for raw wafers is typically 6 to 8 weeks. With a workforce led by a very successful and long-tenured management team, the facility conducts frequent on-site trained maintenance for increased equipment uptime. In addition to silicon wafer fabrication, OnChip also offers various other services such as testing, dicing, and IC packaging.

OnChip Devices is headquartered in Santa Clara, CA and develops Integrated Passive Devices. With its own silicon fabrication facility and strong partnerships with full turn-keys assembly and test houses in Asia, OnChip is offering silicon and ceramic solutions for High-brightness LED, Computing, and Consumer Electronics.

SJ Semiconductor Corp. (SJSemi) and Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated (NASDAQ:  QCOM), jointly announced that SJSemi has begun mass production of 14nm wafer bumping for Qualcomm Technologies. In the wake of 28nm wafer bumping mass production, and with further improvement of its processing techniques and capabilities, SJSemi has become China’s first semiconductor company to enter the industrial chain with 14nm advanced process node mass production. Mass production of the 14nm wafer bumping in China is part of Qualcomm Technologies’ efforts to continuously drive the development of the Chinese integrated circuit industry, and it further reinforces Qualcomm Technologies’ commitment to China through industrial chain optimization, localized services, and superior offers to Chinese customers.

Founded in August 2014, SJSemi is a joint venture between Semiconductor Manufacturing International Corp. (SMIC) and Jiangsu Changjiang Electronics Technology Co., Ltd (JCET). In December 2015, Qualcomm Global Trading Pte Ltd., a subsidiary of Qualcomm Incorporated, participated in an additional investment in SJSemi. SJSemi realized mass production of the 28nm wafer bumping in early 2016, within two years of its inception, and it now ships 12-inch wafers in high volume every month. SJSemi has sharpened its unique competitive edge in 28nm bumping technology by achieving not only a first-class yield rate but also industry-leading key technical indicators such as contact resistance control over high-density copper pillar bumping. SJSemi will continue to expand the capacity of its 12-inch wafer bumping line, securing the supply chain for its customers. Currently, SJSemi has reached the production capacity of bumping 20,000 12-inch wafers per month.

“We are grateful to Qualcomm Technologies for its consistent support. With its assistance, we have managed to set up an advanced 12-inch bumping line with stable and efficient production to offer mass production services to our customers,” said Mr. Dong Cui, Chief Executive Officer of SJSemi. “The mass production of our 14nm wafer bumping technology is in recognition of our capabilities and strengths, and indicates our ability to offer comprehensive services to first-class global customers like Qualcomm Technologies. We expect to continuously keep pace with customer demand, further improve our technical capability, enrich our process methods, and boost our added value to the industrial chain.”

“The 14nm bumping production from SJSemi is very important to Qualcomm Technologies and has begun mass production, which demonstrates SJSemi’s world-class manufacturing capabilities in leading-edge bumping process technology,” said Dr. Roawen Chen, Senior Vice President, QCT global operations, Qualcomm Technologies, Inc. “We are pleased to work with SJSemi to expand our semiconductor supply chain footprint in China, which further shows our commitment to support China’s local IC manufacturing and better serve our Chinese customers.”

A*STAR’s Institute of Microelectronics (IME) has launched two consortia on advanced packaging, the Silicon Photonics Packaging consortium (Phase II) and the MEMS Wafer Level Chip Scale Packaging (WLCSP) consortium. They will develop novel solutions in the heterogeneous integration of micro-electromechanical systems (MEMS) and silicon photonics devices, which will boost overall performance and drive down production costs. The new consortia will leverage on IME’s expertise in MEMS design, fabrication, wafer level packaging process, as well as silicon photonics packaging modules and processes.

The proliferation of the Internet of Things (IoT) is driving the rapid growth of diversified technologies which are key enablers in major application domains such as smart phones, tablets, wearable technology; and network infrastructures that support wireless communications.

However, this trend requires the complex integration of non-digital functions of “More-than-Moore” technologies such as MEMS with digital components into compact systems that have a smaller form factor, higher power efficiency and cost less. The onset of big data, cloud computing and high speed broadband wireless communications also calls for novel use of silicon photonics. Silicon photonics are a critical enabler of high density interconnects and high bandwidth, to meet high optical network requirements cost-effectively.

In the previous Silicon Photonics Packaging Consortium (Phase I), IME and its industry partners developed new capabilities in necessary device library and associated tool boxes to enable the integration of low profile lateral fiber assembly, laser diode and photonics devices. By employing a laser welding technique, the consortium demonstrated a fiber-chip-fiber loss of less than 8 decibel (dB) with less than 1.5dB excess packaging loss. These capabilities enabled integrated silicon photonic circuits to provide higher data rates at lower cost and power consumption. For details, please refer to Annex A.

Building on these achievements, the Silicon Photonics Packaging Consortium (Phase II) will develop a broad spectrum of silicon photonics packaging methodology. The consortium will further develop low loss silicon coupling modules, and provide a series of packaging solutions for laser diode integration. It will also focus on developing accurate thermal models, as well as improve overall module thermal management, reliability and radio-frequency (RF) performance to meet very high data bandwidth demand. All these new developments will lead to a more integrated packaging solution which promises better assembly margins and lower module costs.

IME’s MEMS WLCSP Consortium has also been established to develop a cost- effective integration packaging platform for capped MEMS and complementary metal-oxide semiconductor (CMOS) devices. This platform could be used for any MEMS devices with cavity-capping such as timing devices, inertial sensors, and RF MEMS packaging.

Conventional chip stacking that relies on a through-silicon via (TSV) and wire bonding on substrate method will usually result in high costs and large form factor. The consortium aims to lower production costs and achieve smaller footprint by developing a TSV-free over-mold wafer level packaging solution for MEMS-capped wafer using a novel metal deposited silicon pillar and wire bonding as a through mold interconnects.

The consortium aims to reduce form factor of integrated MEMS and CMOS devices by approximately 20 per cent, and lower manufacturing costs by approximately 15 per cent. These cost-effective packaging solutions are also expected to produce better electrical and reliability performance.

“These consortia partnerships play a critical role in developing innovative solutions to meet emerging market demands. Through these collaborations, we will elevate our capabilities from developing MEMS and silicon photonics devices to developing advanced solutions in heterogeneous integration. The capabilities developed will enable our industry partners to capture new growth opportunities in the IoT space and accelerate market adoption of cost-effective technologies,” said Prof. Dim-Lee Kwong, Executive Director of IME.

“Silicon photonics packaging is a crucial technology for the commercialisation of silicon photonic devices. The partnership generated remarkable results in the Silicon Photonics Packaging Consortium Phase I, and we are pleased to continue with the second phase, which will expand the application of silicon photonics with innovative approaches in terms of LD integration and RF performance. Through this consortium, Fujikura will accelerate the development of compact and cost-effective optical communications for diverse markets,” said Mr. Kenji Nishide, Executive Officer, General Manager, Advanced Technology Laboratory, Fujikura Ltd.

“Currently, it is anticipated that the demand for sensors will grow from billions to trillions by 2050. This demand is being driven by the emergence of sensor based smart systems fusing computing, connectivity and sensing in the context of the Internet of Things. IME’s packaging consortia partnership will allow us to identify and develop MEMS packaging innovative solutions in order to scale up for the Internet of Things,” said Mr. Mo Maghsoudnia, Vice President of Technology and Worldwide Manufacturing of InvenSense.

Mr. Shim Il Kwon, Chief Technology Officer, STATS ChipPAC said, “As the number of MEMS devices in emerging IoT applications continues to grow, semiconductor packaging will have a significant impact on the performance, size and cost targets that can be achieved. By collaborating with partners in the consortia, we will be able to help drive the cost effective integration of MEMS and ASICs in high performance, high yield WLCSP solutions for IoT products.”

New levels of performance of electronics technology have been enabled by flip-chip technology, fueling the growth of global markets for semiconductors, electronic devices, and a host of industrial and consumer products. BCC Research reveals in its new report that increasing complexity of the architecture of chip design and fabrication is spurring this market’s exponential growth rate.

Semiconductor devices like integrated circuits (ICs) are connected to external circuitry using flip-chip technology by means of solder bumps deposited onto chip pads. Traditionally, devices are connected from substrates or other active components using wire bonds. More specifically, flip chip is directly attached to a board, substrate, or carrier by various conductive methods called bumping. The chip is “bumped” by laying it on a substrate and thus uses a “face down” process. Wire bonding, the older methodology gradually being replaced by flip chip, used a “face up” process.

The global market for flip-chip technology, which totaled $24.9 billion in 2015, should reach $27.2 billion and $41.4 billion in 2016 and 2021, respectively, increasing at a five-year compound annual growth rate (CAGR) of 8.8%. As a segment, copper (Cu) pillar bumping process owned the largest market share in 2015, and should retain its position during the forecast period. The Cu pillar bumping process is expected to reach $21.2 billion by 2021, reflecting a five-year CAGR of 16.7%.

The flip-chip market is a technology-driven market. Manufacturers are focusing on developing new technologies for the bumping process, which in turn is increasing the demand for raw materials required for manufacturing. This leads to aggressive growth in this industry among raw material suppliers. The many advantages over other packaging methods such as reliability, size, flexibility, performance, and cost are the prime factors driving the growth of the flip-chip market. The market is also driven by availability of flip-chip raw materials, equipment, and services.

Demand for flip chips with controlled collapse chip connection (C4) technology has grown significantly due to the shrinking size of chips and demand for more sophisticated structures. Improved thermal heat transfer and performance at higher frequencies also drive the market for flip chips.

Flip-chip bumping extensively uses various wafer bumping technologies, such as lead-free solder, gold stud bumping, and so forth. Copper bumping accounts for the major share of the market. Tin-lead (Sn-Pb) solder is expected to show a highly negative growth rate. Government initiatives to ban toxic substances have impacted its market heavily.

“The Cu pillar bumping process provides better performance, low cost, and is a nontoxic process,” says BCC Research analyst Sinha Guarav. “In addition, increasing demand for communication devices and other computing devices is also expected to have a positive impact on the Cu pillar bumping market.”

Flip-Chip Technologies and Global Markets (SMC089B) analyzes the evolution, architecture, and value chain of flip-chip technologies. Global market drivers and trends, with data from 2015, 2016, and projections of CAGRs through 2021 also are provided.

BCC Research is a publisher of market research reports that provide organizations with intelligence to drive smart business decisions.

Applied Materials, Inc. today announced the appointment of Judy Bruner to serve on its Board of Directors. Ms. Bruner has also been appointed to serve as a member of the Audit Committee of the Board.

“As a well-respected chief financial officer with deep experience in the global high-tech industry, Judy will be an asset to Applied Materials’ Board of Directors,” said Wim Roelandts, chairman of the board of Applied Materials. “Having built her career in increasingly sophisticated finance roles across some of Silicon Valley’s top hardware companies, she is a welcome addition to our team of directors and will be a valued member of our Audit Committee.”

Judy Bruner served as Executive Vice President, Administration and Chief Financial Officer of SanDisk Corporation, a supplier of flash storage products, from June 2004 until its acquisition by Western Digital in May 2016. Previously, she was Senior Vice President and Chief Financial Officer of Palm, Inc., a provider of handheld computing and communications solutions, from September 1999 until June 2004. Prior to Palm, Inc., Ms. Bruner held financial management positions at 3Com Corporation, Ridge Computers and Hewlett-Packard Company. She currently serves as a member of the board of directors of Brocade Communications Systems, Inc. and a member of the board of trustees of the Computer History Museum.

North America-based manufacturers of semiconductor equipment posted $1.71 billion in orders worldwide in June 2016 (three-month average basis) and a book-to-bill ratio of 1.00, according to the June Equipment Market Data Subscription (EMDS) Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.00 means that $100 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in June 2016 was $1.71 billion. The bookings figure is 2.1 percent lower than the final May 2016 level of $1.75 billion, and is 12.9 percent higher than the June 2015 order level of $1.52 billion.

The three-month average of worldwide billings in June 2016 was $1.71 billion. The billings figure is 7.0 percent higher than the final May 2016 level of $1.60 billion, and is 10.2 percent higher than the June 2015 billings level of $1.55 billion.

“Although order activity slowed for the most recent month,” said Denny McGuirk, president and CEO of SEMI. “Billings activity for equipment companies based in North America are at their highest level since February 2011.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
January 2016

$1,221.2

$1,310.9

1.07
February 2016

$1,204.4

$1,262.0

1.05
March 2016

$1,197.6

$1,379.2

1.15
April 2016

$1,460.2

$1,595.4

1.09
May 2016 (final)

$1,601.5

$1,750.5

1.09
June 2016 (prelim)

$1,714.0

$1,713.2

1.00

Source: SEMI (www.semi.org), July 2016