Tag Archives: letter-ap-business

Solid State Technology Contributing Editor receives “Lifetime Achievement Award” for “Excellence in 3D Packaging Technologies”

July 21, 2016

Contributing editor and blogger Phil Garrou received the 3D InCites “Device of the Year” award during the 2016 SEMICON West conference for “Excellence in 3D Packaging Technologies.” The awards were a result of industry voting for individuals, companies and products exhibiting excellence in 3D packaging expertise and contributing to the commercialization of game-changing technologies such as: fan-out wafer level packaging (FOWLP), interposer-based packages, 3D stacks and 3D System-in-Package (SiP).

Since his retirement from Dow Chemical in 2004, Dr. Garrou has provided information as a consultant, expert witness and reporter on high end packaging with a focus on 2.5 / 3D Integration.
His weekly Solid State Technology packaging blog “Insights From the Leading Edge” (IFTLE) is now approaching its 300th post.
He has written 130 articles for Yole Developpement’s iMicronews that took “A Closer Look” at advanced packaging technologies focusing on 3DIC.
He co-edited Vol. 1-3 of the Wiley VCH series “Handbook of 3D Integration” in 2008 and 2014 and co-edited the first MRS Proceedings on 3DIC (2006 & 2008).
Garrou helped create and chaired the 1^st and 4^th “IEEE 3D System Integration Conference” that is now entering its 7^th year and has been Technical Chair of the RTI “3D Architectures for Semiconductor Integration & Packaging” Conference (3D ASIP) for the past 9 years.

Phil Garrou accepts the award for “Excellence in 3D Packaging Technologies” from 3D InCites Francoise von Trapp.

Amkor Technology receives “Device of the Year” for SWIFT semiconductor package

July 20, 2016

Amkor Technology, Inc. recently received the 3D InCites “Device of the Year” award during SEMICON West for its’ SWIFT semiconductor package. The awards were a result of industry voting for individuals, companies and products exhibiting excellence in 3D packaging expertise and contributing to the commercialization of game-changing technologies such as: fan-out wafer level packaging (FOWLP), interposer-based packages, 3D stacks and 3D System-in-Package (SiP).

Amkor’s SWIFT product was uniquely developed to deliver a high yielding, high-performance package with the thinnest profile in the industry. This package can deliver 2 µm line/space lithography with up to 4 layers of RDL and a very dense network of memory interface vias from bottom package to the top package at a very cost competitive price.

Jon Woodyard, Amkor’s VP of Technical Programs accepts the 3D InCites award for “Device of the Year” from Francoise von Trapp and Stephen Hiebert, KLA-Tencor.

AppliedMicro adopting TSMC 7nm finFET process technology

July 11, 2016

Applied Micro Circuits Corporation (NASDAQ:AMCC) today announced that it has adopted 7nm process technology from TSMC, a world-leading foundry, to enable AppliedMicro’s silicon products for cloud computing and networking applications.

“We are excited to extend our relationship with TSMC to ultimately bring cutting-edge technology to the cloud computing market,” said Paramesh Gopi, President and CEO of AppliedMicro. “We will work closely with TSMC to ensure our flagship silicon products benefit from their manufacturing excellence that is renowned throughout the industry. Together we will introduce technology to revolutionize the rapidly growing data-center market to deliver an unprecedented bundle of compute and connectivity performance, energy efficiency and bandwidth utilization at a low total cost of ownership.”

“We are pleased to be a part of AppliedMicro’s success,” said Dr. B.J. Woo, TSMC Vice President of Business Development. “TSMC’s advanced 7nm technology will empower AppliedMicro to deliver the critical performance needed in computing and connectivity applications.”

Recently introduced innovations from AppliedMicro include X-Gene 3 at ARM TechCon in November 2015, and single lambda, mixed signal 100G X-Weave PAM4 at the Optical Fiber Communications Conference in March 2016. Both product functions were validated with TSMC 16FF+ shuttle and are expected to sample to customers by early 2017.

TECHCET 2016 forecast: $1.39B in photoresists, $680M in extensions

July 8, 2016

Photoresist manufacturers had reason to smile as fiscal 2015 closed, with sales growing nicely to $1.37B, a 6.2% increase over 2014. That bump has to sustain them through 2020, according to a new report from Techcet Group, “Critical Materials Report: Photoresists and Extensions and Ancillaries 2016.” Total volumes for photoresist and extension materials continue to grow with wafer starts, although revenues are expected to hover around $1.4B for the next 4 years. Growth from wafer starts in partially offset by reductions in photoresist thicknesses for critical layers in leading edge devices.

Virtually all of the growth in lithography materials can be attributed to volume growth in advanced nodes. While the 5 year CAGR outlook for silicon wafer starts is -2% for the 45nm node and larger, that same outlook is +10% for the 28nm node and smaller. ArF (193nm wavelength) resists already comprise over 40% of the total market. Extreme ultra-violent lithography (EUVL @ ~13nm wavelength) remains in the forecast for 2020, but it will be limited to mix-and-match implementation at the 10nm node due to its premium cost and low throughput. Nano-Imprint Lithography (NIL) is in limited use by one Asian memory fab. Multi-patterning with 193nm immersion will remain the workhorse for all leading edge IC fabs.

The category of resolution “extension” materials to enable finer feature patterning grows out of the segment for bottom anti-reflection coatings (BARC) and spin-on hard-masks (HM), which can be combined with a top layer of photoresist in a so-called “Tri-Layer Resist” (TLR) approach. Extensions also include specialty chemical formations to “trim” lines by removing photoresist material, or to “shrink” holes by adding material to sidewalls. The extension materials market is now the fastest growing segment, already at $650M in 2015 it is forecast to reach $790M by 2020, as detailed in TECHCET’s Report.

The photoresist ancillary segment that includes strippers/removers, developers, edge-bead removers (EBR) and specialty solvents is expected to suffer a slow decline from today’s $600M to $575M by 2020, primarily due to volume reductions associated with thinner photoresists. Also, ancillaries are generally sourced in large quantities from local suppliers, and regional pricing pressures further depress revenues in this sub-market.

There are six major suppliers controlling 90% of the global resist market, with a total of eleven key manufacturers offering standard and advanced photoresist products and critical ancillaries. JSR and TOK share 53% of the market, with others at 12% or less. In addition to market analysis, critical supply chain issues and technical trends, the report includes profiles and updates for major suppliers of photoresist and related materials to the global semiconductor industry.

IC Insights lowersÂ 2016 semiconductor market forecast to -1%

July 8, 2016

The health of the semiconductor industry is increasingly tied to the health of the worldwide economy. Rarely can there be strong semiconductor market growth without at least “good” worldwide economic growth to support it. Consequently, IC Insights expects annual global semiconductor market growth rates to continue to closely track the performance of worldwide GDP growth (Figure 1). In its upcoming Mid-Year Update to The McClean Report 2016 (to be released at the end of July), IC Insights forecasts 2016 global GDP growth of only 2.3%, which is below the 2.5% level that is considered to be the global recession threshold.

Figure 1

In many areas of the world, local economies have slowed. China, which is the leading market for personal computers, digital TVs, smartphones, new commercial aircraft, and automobiles, is forecast to continue to lose economic momentum in 2016. Its GDP is forecast to increase 6.6% this year, which continues a slide in that country’s annual GDP growth rate that started in 2010 when growth rates exceeded 10%.

IC Insights believes that the worldwide economy will be negatively impacted, at least over the next year or two, by the Brexit vote this past June. At this point, since the U.K. is unlikely to officially be able to leave the European Union (EU) for a couple of years, the biggest negative effect on economic growth is the uncertainty of the entire situation. Some of the uncertainty created by the vote includes:

• Whether the U.K. will actually leave the EU. Since the Brexit vote is not legally binding, and still needs to be approved by the U.K. government, there is uncertainty if its departure from the EU will actually happen.

• Whether the U.K. will come apart itself. There are rumblings about Scotland breaking away from being a part of the U.K. in order for it to remain as part of the EU.

• What trade deals will be made by the U.K. if it does leave the EU? As part of its exit from the EU, the U.K. will need to establish numerous new trade deals with the EU. There is tremendous uncertainty regarding whether these deals would have a positive or negative effect on the U.K. economy.

• Will other countries follow the U.K. and depart from the EU? Anxiety persists over whether the EU will fall apart as other countries attempt their own exit. Some countries mentioned as possibly following the U.K. out of the EU include the Netherlands (Nexit), France (Frexit), Italy, Austria, and Sweden (Swexit).

The other major “culprit” dragging down semiconductor industry growth this year is the very weak DRAM market. At $45.0 billion, the DRAM market was the largest single product category in the semiconductor industry in 2015. IC Insights forecasts that the DRAM market will register a 19% drop of $8.5 billion this year to $36.5 billion. The DRAM market alone is forecast to shave three percentage points off of total semiconductor market growth this year. Semiconductor market growth excluding DRAM is forecast to be +2%.

Most of the DRAM market decline expected for this year is due to a rapid decline in DRAM pricing over the past 18 months. For 2016, the average price for a DRAM device is forecast to drop to $2.55, a steep 16% decline as compared to 2015’s DRAM ASP of $3.03. Further trends and analysis relating to semiconductor market forecasts through 2020 will be covered in the 250-plus-page Mid-Year Update to the 2016 edition of The McClean Report.

Dr. Cheryl L. Shavers elected to Mentor Graphics Board of Directors

July 7, 2016

Mentor Graphics Corp. (NASDAQ: MENT) today announced that on June 15, 2016, the company’s shareholders elected Dr. Cheryl L. Shavers to the company’s board of directors.

Dr. Shavers currently serves as chief executive officer of Global Smarts, Inc., an advisory services and strategy firm, which she founded in 2001 to assist companies and government agencies to manage growth opportunities and the innovative process. Additionally, she is a Distinguished Dean’s Professor at the Leavey School of Business at Santa Clara University. Dr. Shavers is also a director on the board of Rockwell Collins, Inc. serving on the company’s Nominating and Governance Committee, and chairing its Technology/Cybersecurity Committee.

“We welcome Dr. Shavers to the Mentor board,” said Walden C. Rhines, chairman and CEO of Mentor Graphics. “Her extensive experience in the semiconductor industry, U.S. government technology policy and direction of a major military/avionics corporation will provide helpful perspectives and direction for our company.”

Dr. Shavers was Under Secretary of Commerce for Technology for the U.S. Department of Commerce from November 1999 to February 2001 after having previously served as its Under Secretary designate. Prior to that, she held a variety of roles at Intel Corporation, including director of Emerging Technologies and sector manager of the Microprocessor Products Group for Intel Capital. She has served on the board of ATMI, a semiconductor materials company acquired by Entegris, and of E.W. Scripps Company. She served as non-executive chairman of BitArts Ltd., a digital security company, from 2001 to 2003.

Dr. Shavers holds a B.S. degree in Chemistry and a Ph.D. in Solid State Chemistry from Arizona State University and was awarded an honorary Master’s degree in Engineering Management from California Polytechnic State University. She is also a registered patent agent with the Patent and Trademark Office of the Department of Commerce.

Global semiconductor sales up slightly in May

July 5, 2016

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $26.0 billion for the month of May 2016, an increase of 0.4 percent compared to the previous month’s total of $25.9 billion, but a decrease of 7.7 percent compared to the May 2015 total of $28.1 billion. Month-to-month sales into all regional markets held relatively steady, with China leading the way with 3.1 percent market growth. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The small uptick in global semiconductor sales in May marked the market’s largest month-to-month growth in six months, but the overall landscape remains somewhat stagnant due to soft demand and unfavorable macroeconomic conditions,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Most regional markets have struggled to gain traction in 2016, with the Americas falling well behind sales posted through the same point last year. Sales of analog products were a bright spot in May, notching both month-to-month and year-to-year increases.”

Regionally, month-to-month sales increased in China (3.1 percent), but slipped slightly in the Americas (-0.1 percent), Europe(-0.8 percent), Asia Pacific/All Other (-0.8 percent), and Japan (-1.8 percent). Year-to-year sales increased marginally in Japan(0.4 percent), but dropped in China (-0.5 percent), Europe (-8.8 percent), Asia Pacific/All Other (-11.5 percent), and the Americas (-15.0 percent).

May 2016
Billions
Month-to-Month Sales
Market	Last Month	Current Month	% Change
Americas	4.78	4.78	-0.1%
Europe	2.64	2.62	-0.8%
Japan	2.60	2.55	-1.8%
China	7.80	8.04	3.1%
Asia Pacific/All Other	8.03	7.96	-0.8%
Total	25.85	25.95	0.4%

Year-to-Year Sales
Market	Last Year	Current Month	% Change
Americas	5.62	4.78	-15.0%
Europe	2.87	2.62	-8.8%
Japan	2.54	2.55	0.4%
China	8.08	8.04	-0.5%
Asia Pacific/All Other	9.00	7.96	-11.5%
Total	28.11	25.95	-7.7%

Three-Month-Moving Average Sales
Market	Dec/Jan/Feb	Mar/Apr/May	% Change
Americas	5.03	4.78	-5.0%
Europe	2.66	2.62	-1.5%
Japan	2.47	2.55	3.0%
China	8.03	8.04	0.2%
Asia Pacific/All Other	7.83	7.96	1.6%
Total	26.03	25.95	-0.3%

A*STAR’s Institute of Microelectronics (IME) has partnered semiconductor companies to develop cost-effective solutions in 2.5D and 3D wafer-level integrated circuit (IC) packaging. The newly formed Chip-on- Wafer Consortium II and the Cost-Effective Interposer Consortium will leverage IME’s expertise in 3D and 2.5D IC integration; bonding technologies; as well as the design and packaging of semiconductor dies to develop advanced chip packaging solutions. All these capabilities will lead to cost savings and high- volume manufacturing.

In today’s mobile and connected world, consumers demand next-generation devices that are multi-functional, more compact, offer better performance, and consume less power. As the industry moves towards more innovative technologies to keep pace with market trends, it must also keep manufacturing costs low to remain competitive.

The Chip-on-Wafer (CoW) Consortium II will build on the success of the first CoW consortium to further reduce production time and costs for 3D and 2.5D packaging. In the CoW Consortium I, IME and its partners successfully demonstrated Chip-on-Wafer bonding with Copper-Copper (Cu-Cu) diffusion bonding technology. The two-step process involves temporary flip-chip bonding and permanent gang bonding at a temperature of 200 degree celsius. This enables the scaling of the interconnect pitch of the integrated circuit from the average of 40 (micrometers) μm to 6μm.

The consortium achieved the highest throughput bonding – five times faster than the conventional solder-assisted thermo-compression bonding technique – making the flip-chip bonding of thin (20μm) through-silicon via (TSV) dies possible without damaging the chip.

These technological breakthroughs will allow device manufacturers to better integrate 3D chipsets such as complementary metal-oxide semiconductor (CMOS) image sensors, signal processors, logic and memory, and memory stacks. They will also increase the overall throughput by 400 to 500 per cent and lower the manufacturing cost by approximately 40 per cent.

The CoW Consortium II (please refer to Annex A for list of consortium members) will further develop the Cu-Cu diffusion bonding technology for energy-efficient and highly reliable devices. This technology will be applied in the development of 3D memory stack and 2.5D integration of a field-programmable gate array (FPGA) and memory on TSV-less interposer. It aims to achieve these by demonstrating a low-temperature Cu-Cu bonding with narrow-gap (3 to 5μm) flip- chip bonding, where the narrow gap is filled with optimised pre-applied under-fill.

Prior to the Cost-Effective Interposer Consortium, IME’s 2.5D Through-Silicon Interposer (TSI) Consortium successfully demonstrated an end-to-end design- process-assembly-packaging flow for large area (39 mm by 27 mm) TSI with dense multi-level Cu interconnects. FPGA and Dynamic Random Access Memory (DRAM) ICs were integrated for high-performance and power-efficient systems. The consortium also developed a 2.5D TSI process design kit (PDK) and electronic design automation (EDA) flow for fabless companies to design TSI, and subsequently perform wafer fabrication, assembly and packaging at IME’s 300mm wafer fabrication facility. These achievements afford companies across the value chain a lower cost of entry, and seamless design-to-manufacturing flow for 2.5D TSI technology. IME worked closely with Foundry, OSAT, Materials, Equipment, EDA, Fabless partners to capture their design and manufacturing requirements, and overcome challenges associated with the volume production of 2.5D TSI.

The Cost-Effective Interposer Consortium (please refer to Annex B for list of consortium members) will address the high manufacturing costs of interposers. It will address the capability limitations in silicon interposers for FPGA and graphic processing unit (GPU) IC designs for 2.5D and 3D IC packaging. IME and its partners will integrate value-added analog and power management unit (PMU) to the silicon interposer and develop an interposer which will not require TSV processing; hence reducing the cost of silicon interposers by up to 50 per cent.

Prof. Dim-Lee Kwong, Executive Director of IME said, “The outstanding results of phase 1 of our past consortia bring us to a new milestone in advanced chip packaging. They will play a foundational role in meeting challenging requirements for highly integrated mobile applications and connected devices. Moving forward, I am confident that IME’s close collaboration with our partners will continue to take our advanced packaging technologies and solutions to greater heights, and spur the mass adoption of cost-effective high performance systems.”