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By Ira Feldman, general chair, BiTS 

What’s the single area that is being most disrupted by emergent technologies like the Internet of Things (or the Internet of Vehicles) and Silicon Photonics? We think it’s packaging. The cost and size constraints of these pervasive devices is driving ever more “shrink” – and innovation in the area of packaging – in order to deliver their benefits to every aspect of our daily lives. From fancy pedometers that are auditing our every step to all the data centers that are required to host the big data that is being created … ICs are at the core of the transformation and the test and packaging of these devices is incrementally more challenging.

“Silicon Photonics manufacturing has evolved to the point where it is now possible to manufacture a silicon photonics die using a standard CMOS manufacturing line. But, one challenge remained unsolved: how to test these applications at wafer level in a volume production environment,” said Jose Moreira, senior staff engineer at Advantest. “Working in conjunction with Tokyo Electron Labs and STMicroelectronics, a test cell implementation for testing mixed digital and silicon photonics ICs has been devised. In our Burn-In and Test Strategies (BiTS) Workshop presentation, we will review a solution for a high volume test cell for an OSAT environment.”

bits 2 bits

Now in its 17th year, BiTS offers a full technical program that spans four days including sessions on MEMS test, WLCSP test, Test Cell Integration, simulation & modeling, materials, and more. This year’s Tutorial is a practicum on the theory and statistics that underlie Adaptive Test to include test time reduction and outlier detection. The BiTS EXPO showcases the latest in test cell hardware, services, and consumables including sockets, load boards, contactors, materials, and more. BiTS has plenty of time for networking, great food, and warm weather! Attend the Burn-In and Test Strategies (BiTS) Workshop (March 6-9) in Mesa, Arizona. SEMI has arranged a special discount of $50 off registration when using the code of 50SEM.

The worldwide electronics industry is greatly influenced by consumer purchases of smartphones, PCs, automobiles, and many other devices and systems. The better the worldwide economy performs, the more money consumers will spend on electronic systems, which in turn creates a positive environment conducive to good IC market growth.  For 2016, IC Insights is taking a conservative approach to worldwide GDP with forecast growth of 2.7%, which is only slightly better than the 2.5% global GDP growth in 2015. Some observations regarding worldwide GDP include the following.

– Average annual worldwide GDP figures have declined every decade since the 1960s with a slight rebound registered in the first six years of the current decade (Figure 1). Worldwide annual GDP growth has averaged 2.8% since 1980.

– Worldwide annual GDP growth rarely goes negative (the last negative worldwide GDP year before 2009 was in 1946) and rarely goes above 5.0% (with the usual associated surge in oil prices acting as a strong limiting factor).

– A worldwide GDP growth rate of 2.5% or less is considered by most economists to be indicative of a global recession, which puts 2015’s growth right at the threshold.  Prior to the late 1990s, when emerging markets like China and India represented a much smaller share of the worldwide economy, a global recession was typically defined as 2.0% or less growth.  The global recession threshold has never been a “hard and fast” rule, but the guidelines discussed here are useful for this analysis.

IC Insights depicts the increasingly close correlation between worldwide GDP growth and IC market growth in Figure 2.

Figure 1

Figure 1

Figure 2

Figure 2

As seen in Figure 2, the 2010-2015 correlation coefficient between worldwide GDP growth and IC market growth was 0.92, a very strong figure given that a perfect correlation is 1.0.  In the three decades previous to this time period, the correlation coefficient ranged from a relatively weak 0.63 in the early 2000s to a negative correlation of -0.10 in the 1990s.

IC Insights believes that the growing number of mergers and acquisitions in the IC industry (discussed in detail in Section 3 of the new 2016 McClean Report) has resulted in fewer major IC manufacturers and suppliers and is just one of the major changes in the supply base that illustrates the maturing of the industry.  Other factors such as few, if any, new entry points for startup IC manufacturers, a strong movement to the fab-lite business model, and declining capex as a percent of sales ratios, are also indicative of dramatic changes to the semiconductor industry that are likely to lead to less volatile pricing and less volatile market cycles.

With forecasted annual worldwide GDP growth rates that range from 2.7% to 3.1% over the next five years, IC Insights’ IC market growth rate expectations mirror the narrow range of worldwide GDP growth.

According to the latest market study released by Technavio, the global wafer-level manufacturing equipment market is set to post a CAGR of over 4 percent by 2020.

In its release, the company said this research report titled ‘Global Wafer-level Manufacturing Equipment Market 2016-2020’ provides an in-depth analysis of the market in terms of revenue and emerging market trends. This market research report also includes up to date analysis and forecasts for various market segments and all geographical regions.

The report also segments the global wafer-level manufacturing equipment market into three key regions, including APAC, North America, and Europe. Of these three regions, APAC has been the largest contributor to the market, accounting for close to 72 percent market share in 2015. The significant presence of semiconductor IC manufacturers in APAC is one of the major reasons for the high revenue contribution from this region. One of Technavio’s lead analysts from the semiconductor equipment sector, Asif Gani, says, “The increasing adoption of semiconductor devices in IoT applications is driving the semiconductormarket, which will create demand for wafer-level manufacturing equipment. Similarly, with the increasing demand for semiconductor ICs in both the consumer electronics and automobile segments, and also with the growing complexities of semiconductor ICs, the demand for wafer-level manufacturing equipment will see a rise during the forecast period.”

As of 2015, the foundry segment was the largest revenue contributor to the global wafer-level manufacturing equipment market and accounted for a revenue share of almost 63 percent. The primary reason for the market dominance of the foundry segment is the increasing number of fabless semiconductor manufacturers. Technavio predicts the foundry segment to achieve a revenue of over USD 27 billion by 2020, at a CAGR of more than 4 percent.

“The foundry segment is likely to progress significantly over the next five years due to increasing demand for semiconductor ICs, such as logic, analog, discrete, optic, and sensor ICs, which are used in devices such as smartphones, tablet PCs, notebooks, digital cameras, gaming consoles, set-top box, and network switches,” affirms Asif.

Memory segment anticipated to generate over USD 10 billion by 2020The memory segment is expected to generate over USD 10 billion by 2020, posting a CAGR of more than 4 percent during the forecast period. Technology traction and oversupply of DRAM by memory device manufacturers will slow down the expansion of production facilities globally in 2016. Therefore, the market share of this segment will decline in the same year. However, the market is expected to recover post 2016, due to the increasing demand for DRAM and NAND used in smartphones and tablet PCs and a high adoption of 3D NAND. This will indirectly trigger the demand for wafer-level manufacturing equipment during 2017-2020.

High adoption of the fabless business model to hinder growth of the IDM segmentThe IDM segment contributed more than USD 4 billion in 2015 to the global market and this figure is expected to increase to USD 5 billion by 2020, growing at a CAGR of over 2 percent, during the forecast period. However, the market share of this segment will decline as a result of the high adoption of the fabless business model.

EV Group (EVG), a supplier of wafer-bonding, lithography/nanoimprint lithography (NIL), metrology, photoresist coating, cleaning and inspection equipment, today announced its participation in the 3D integration consortium of IRT Nanoelec, which is headed by CEA-Leti. EVG joins Leti, STMicroelectronics and Mentor Graphics to develop advanced 3D wafer-to-wafer bonding technologies. SET also joined recently the consortium.

Based in Grenoble, France, IRT Nanoelec is an R&D center focused on information and communication technologies (ICT) using micro- and nanoelectronics. 3D integration is one of its core programs.

The 3D integration program was launched in 2012. It brings together, under a single roof, expertise and equipment addressing the entire 3D integration value chain: technology, circuit architecture, EDA tools, packaging and test. Mentor Graphics (EDA), ST (foundry) and Leti are the founding members of the consortium.

“The development of permanent bonding equipment and processes geared towards high-volume manufacturing of 3D stacked devices has been a focus area for EVG for more than 15 years. We are excited about the opportunities that result from joining forces with CEA-Leti, STMicroelectronics and Mentor Graphics to further develop and prove our solutions for advanced 3D technologies, such as 3D partitioning and advanced 3D imaging sensors,” said Markus Wimplinger, corporate technology development and IP director. “Being able to verify and further optimize bonding technologies with the most advanced product designs and in a leading-edge fab environment is critical for further progressing our technology development.”

Séverine Chéramy, director of the 3D integration program of IRT Nanoelec, said the consortium expects to achieve an interconnection pitch of about 1µm.

“The work with EVG, in the frame of IRT Nanoelec, will undoubtedly add value to the current program, because wafer-to-wafer stacking using direct Cu-to-Cu bonding is key for advanced 3D technologies, specifically for imaging application and 3D partitioning,” she said. “EVG’s knowledge on bonding will leverage the process expertise of the original members. The participation of EVG in the consortium will create new opportunities and optimized and cost-effective solutions for 3D IC devices.”

IRT Nanoelec previously announced that SET, Smart Equipment Technology, joined a consortium project to help develop advanced 3D die-to-wafer stacking technologies, using direct copper-to-copper bonding.

IRT-Nanoelec Research Technological Institute (IRT), headed by CEA-Leti, conducts research and development in the field of information and communication technologies (ICT) and, specifically, micro- and nanoelectronics. Based in Grenoble, France, IRT Nanoelec leverages the area’s proven innovation ecosystem to create the technologies that will power the nanoelectronics of tomorrow, drive new product development and inspire new applications – like the Internet of Things – for existing technologies. The R&D conducted at IRT Nanoelec provides early insight into how emerging technologies such as 3D integration and silicon photonics will affect integrated circuits.

SEMI announced today the launch of the European Semiconductor integrated Packaging and Test (ESiPAT) Special Interest Group.  The Special Interest Group (SIG) represents SEMI members who have semiconductor packaging, assembly, test manufacturing, or design activities in Europe. The purpose of the SIG is to foster collaboration among companies and to collectively raise the profile and reinforce the semiconductor back-end industry in Europe. Activities will include:

  • Maintaining a strong back-end network in Europe
  • Increasing awareness between European suppliers and device/packaging manufacturers
  • Mapping and reporting capabilities and capacities of European SiPAT members
  • Identifying gaps in the European back-end supply chain relative to other regions
  • Advocating for the  Packaging, Assembly, and Test industry in Europe
  • Building project consortia and bidding for European funding

The newly formed executive committee of the SIG includes representatives from AEMTec, First Sensor, NANIUM, RoodMicrotec, Sencio, STMicroelectronics, and Swissbit. More than 20 additional companies from the European back-end supply chain have already expressed interest to join.

Companies meeting the requirements can apply to join the ESiPAT group. SEMI membership and ESiPAT SIG membership dues are required. Additional information, including the charter and by-laws, is available online.  Within SEMI, Europe is pioneering the SiPAT SIG. Additional chapters in North America and Japan are currently under development.

Orbotech Ltd. today announced that, Nippon Mektron Mektec, a maker of flexible printed circuit boards (FPCBs), is deploying Orbotech direct imaging (DI) and automated optical inspection (AOI) systems in multiple factories. These systems will significantly improve current and future smartphone manufacturing by facilitating the creation of flex inspections and high-throughput production capability.

“Flex” PCB manufacturing, which is required to accommodate the rapidly expanding mobile phone market, will be supported by Orbotech’s Nuvogo DI systems, with DI for patterning and solder mask applications, as well as Orbotech’s AOI systems for inspection. Nippon Mektron has worked closely with Orbotech’s local support teams to ensure consistent product performance and quick production ramp up throughout their factories in Japan, Thailand, China and Taiwan.

“From mobile phones and tablets to wearables and sophisticated automotive electronics, today’s electronics manufacturers are constantly being challenged to simplify designs, provide flexible packaging solutions and support ever-smaller devices,” said Yair Alcobi, President, Orbotech Asia East. “Through this very close collaboration, we are pleased to support Nippon Mektron’s current and future product performance requirements for flex PCB manufacturing processes and enable them to offer innovative and market-ready solutions.”

According to industry analyst firm Prismark Partners’ January 2016 Printed Circuit Report, the 2015/2014 year-on-year value growth estimate for flex PCBs increased by 6.2 percent in dollar value worldwide, which can be attributed to demand for smart and connected electronics and the need for high-speed communications in small and lightweight packages.

IC Insights recently released its new Global Wafer Capacity 2016-2020 report that provides in-depth detail, analyses, and forecasts for IC industry capacity by wafer size, by process geometry, by region, and by product type through 2020.

Researchers estimate that there are about 80,000 earthquakes globally each year, but most are too minor to notice. The Great East Japan Earthquake (a.k.a., 2011 Tohoku Earthquake) and subsequent tsunami that struck east of Sendai on March 11, 2011 caused substantial loss of life and destruction to infrastructure. It was the most powerful earthquake ever to hit Japan and the fifth most powerful in the world since records started being kept in 1900. Many semiconductor fabs, as well as other facilities that support the industry, were significantly damaged by the quake (some were shut down permanently as a result).

Since the earliest days of IC production in Silicon Valley, the IC industry has always had much of its fabrication facilities located in seismically active regions. Moreover, as of December 2015, roughly half of the world’s total IC wafer production capacity was located in seismically active areas (defined as areas having moderate to high risk of being significantly impacted by earthquake tremors).

  • Taiwan and Japan accounted for 39% of global IC capacity in December of 2015. Both countries are considered entirely seismically active, and have large amounts of IC capacity exposed to potential earthquake damage.
  • Even though Southeast Asia is generally considered very active seismically, Singapore and Malaysia are actually considered relatively safe from earthquake damage. In China, Beijing is considered to have moderate-to-high seismic risk, but other cities such as Shanghai, Shenzhen, and Wuxi are considered to be “on solid ground.” Similarly, while the Southern part of France has moderate seismic risk, the Central and Northern areas do not.

As shown in Figure 1, 64% of pure-play IC foundry capacity is located in seismically active regions. Since two of the largest pure-play IC foundries in the world (TSMC and UMC) have such a significant presence in Taiwan, a disastrous earthquake or typhoon in that country would have serious ramifications for the entire electronics supply chain. In fact, because IC foundries have so many different customers and are sole-source producers for such a wide variety of part types, the ramifications of damage to IC foundry fabrication facilities would be much greater than damage done to individual IDM IC fabs.

Figure 1

Figure 1

A few years ago, IC Insights was contracted to perform a proprietary market research report for a large insurance company.  This company wanted to develop a model that showed how much in electronic system sales would be lost if the fabs in Taiwan were shut down for one, two, or three months due to damage caused by an earthquake or typhoon.  When considering only the Hsinchu Science Park, which is home to about 45% of the island nation’s total wafer capacity, it was determined that, for each month of net loss resulting from the Hsinchu fabs being out of operation, a $9.3 billion net negative effect would be exerted on worldwide electronic system sales!

Although the IC industry has always had the majority of its fabrication capacity located in “dangerous” areas, most buyers of ICs don’t give this a second thought.  Ultimately, all that really can be said about the ability to predict devastating natural disasters is that everything is just “fine” until one day it isn’t. However, while these tragic events are impossible to predict, they are not impossible to plan for.  The Great East Japan Earthquake should have been a wake-up call to spur the entire electronics supply chain to create new contingency plans, just in case.

“At Yole, we’ve identified five key packaging platforms that can be processed on a larger surface (rectangular/square),” said Amandine Pizzagalli, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing at Yole Développement. There are FOWLP panel, organic interposer, glass panel interposer, hybrid interposer and embedded die. Some of these advanced packaging platforms, embedded die and organic interposer are already available on panel, while others like FOWLP and glass interposer have yet to be confirmed. Over the past few years, it becomes clear that some panel package choices will be more suitable than others for successful commercial development.

So, when will the panel industry take off? How will it evolve?

Yole Développement (Yole) presents the panel packaging technologies landscape. Yole’s analysts detail the commercialization status, market adoption and the business opportunities for each available and in-development packaging technology. Under this new report, they analyze related drivers and challenges for technology adoption; they also describe the competitive landscape with a detailed supply chain and a market adoption roadmap.

Within the panel level packaging industry, embedded die-in-substrate is a promising packaging technology whose key benefits are small form factor and size, high integration capability, and good thermal/electrical performance. However, despite these benefits and the multiple players working on this technology, it hasn’t really taken off in terms of high-volume manufacturing. Presently, only a few players including TDK, AT&S, and Taiyo-Yuden are in volume production.

“At Yole, we believe that things are starting to happen which will propel this technology onto a high growth path,” commented Santosh Kumar, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing at Yole.

With TDK and ASE establishing their “ASE Embedding Electronics” joint venture in 2015 (in which products based on TDK’s SESUB technology will be manufactured), Yole expects more licensing/multi-sourcing activities in the future that will bode well for embedded die packaging. Also, substrate suppliers like AT&S are working with industrial bodies like IPC to create standards. OSATs are less interested in embedded die technology, but they can collaborate with their substrate partners to leverage their experience and technology to develop the supply chain and create a value-added product that will be a win-win scenario for both. One example is the collaboration between Nanium and AT&S for E2CP (Embedded Embedded Component Package).

FOWLP panel level could enable a lower cost per chip. The industry’s general consensus is that FO WLP-on-panel will bring huge cost benefits. Many OSATs and equipment/materials providers are involved in FOWLP-on-panel’s process development, but at present only J-Devices has the established infrastructure for FOWLP-on-panel, while ASE is using their flip-chip infrastructure for low-cost FOWLP-on-panel production.

Certain criteria must be fulfilled and certain challenges overcome for FOWLP-on-panel’s broad adoption linked to large capex investment, equipment readiness, standardization, multisource availability, and most important, market availability to keep the panel line running. There are technical challenges too, such as warpage control, die placement accuracy, and fabrication of sub 10/10um line, etc. on large panels.

Glass panel interposer is another attractive platform for RF applications due to its considerable upside, which includes electrical performance, CTE match, and cost reduction opportunities. However, commercialization of glass panel interposer has limits linked to Through Glass Via (TGV) formation and metallization. Substrate makers and glass suppliers are pushing to validate glass panel interposer’s value, but OSATS, which have zero control over glass material’s cost structure and possess limited experience, are not likely to invest in glass panel technology’s development.

By Deborah Geiger, SEMI

The application that world’s largest contract chipmaker TSMC submitted to set up a 12-inch wafer plant in China will likely be green-lighted before Chinese New Year’s rolls around on February 8, according to the China Post on January 26.

The recent Solid State Technology article  “China Semiconductor Acquisitions Surge, SEMICON China Brings the New Market into Focus“ (SEMI) on January 26 discusses semiconductor equipment spending in 2016 ─  expected to be $5.3 billion, 9 percent above 2015 spending. In 2016, total spending on semiconductor materials in China will be $6.2 billion. Programs such as “Build China’s IC Manufacturing Ecosystem” and “Tech Investment Forum-China 2016” will be offered at the upcoming SEMICON China.

The Shanghai Integrated Circuit Investment Fund (SICIF) announced a plan to invest 20 billion yuan (about $3 billion) in foundry SMIC and two other China chip manufacturers, according to Peter Clarke from the EE Times.

The Taiwan minister of economic affairs, John Deng, says Taiwan’s chip designers “are keen to accept investment from China, but the higher reaches of the semiconductor industry remain off limits.”  In the article “Minister Deng says Chip Designers Need China” by Cheng Ting-Fang and Debby Wu of the Nikkei Asian Review, Deng says that he intends to lobby the new parliament to get the ban lifted.

The article in the Economist “Chips on their Shoulders: China Wants to become a Superpower in Semiconductors” on January 23 discusses how China wants to become a superpower in semiconductors and is planning on spending “colossal sums” to achieve this.

Solid State Technology‘s Ed Korczynski writes about “Imagining China’s IC Fab Industry in 2035“ on January 22, noting that China has been investing in technology to reach global competitiveness for many decades. Intel’s Fab68 in Dalian began production of logic chips in 2010, Samsung’s Fab in Xian began production of V-NAND chips in 2014, and TSMC announced it is seeking approval to build a wholly-owned 300mm foundry in Nanjing.  How and why is the pace escalating?

The Nikkei Asian Review article on “U.S. Opposition Scuppers Philips’ $3.3B Sale of Lumileds to Chinese Buyers” by Jennifer Lo on January 22 talks about how Royal Philips had to scrap a $3.3 billion deal to sell its lighting components units to a consortium of Chinese buyers due to opposition by U.S. regulators over national security concerns.

EE Times Silicon Valley Bureau chief Rick Merritt reports from the SEMI Industry Strategy Symposium (ISS) in an article primarily on SMIC on January 20. Merritt postulates that China’s Big Fund is like the Powerball lottery, “A lot of money is at stake so everybody wants to play, but no one knows how to win.” Some say that $100 billion in government and private funds are available.

For a more comprehensive list of articles related to the China market and the semiconductor industry, visit China Market Central which helps you navigate the unfolding China market dynamics — China policy and market developments.

Presto Engineering Inc. announced this week that it has significantly expanded its turnkey capabilities with the opening of two new manufacturing hubs and a world-wide logistics center in Asia.

As an outcome of its partnership with Inside Secure, announced April 2015, Presto Engineering is taking on the facilities in Asia, adding footprint; significant expertise; and a new, enhanced suite of services for Presto’s customers. Presto Engineering now offers a complete and comprehensive turn-key product engineering and production management solution for integrated circuits (IC), from GDSII hand-off (design output) to finished ICs shipped directly to end customers, targeted at the latest in high-speed communication, Internet of Things (IoT) and secured elements markets.

“This expansion provides the local production capacity and hands-on expertise that we need in Asia to offer our customers a fast, secure, cost-effective, and comprehensive production solution,” states Michel Villemain, CEO, Presto Engineering. “We now have fully-trained staff and substantial local capacity with our own test equipment in place in Asia. This both strengthens and complements our capabilities in the U.S. and Europe, enabling us to provide responsive, on-site and in-region technical support for optimum visibility on customer projects, where and when it counts.”

Jon Lanson, Presto’s Vice President of WW Sales & Marketing adds, “There is no doubt that security is a major concern in the IoT market. Building a hardware-based secure solution, like what’s done in the payment world, is one of the leading IoT security approaches. With Presto’s new secure capabilities in Europe and Asia, we are ready to address this manufacturing issue now, by either assisting clients with developing their own specific solution, or executing an existing turnkey process.”

The new operations are located in Bangkok, Thailand; Kaohsiung, Taiwan; and Hong-Kong, SAR. To Presto’s existing capacity in the US and Europe, they add 20+ probe test cells, advanced die prep capabilities, and payment module manufacturing in secured (EAL5+/EAL6) floors, ready to support large projects with unit volumes of 10 million or more.