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Brewer Science, Inc., and Arkema announced a partnership to produce high-quality directed self-assembly (DSA) materials for use in semiconductor manufacturing. DSA will be one of the key technologies that enable high-volume, cost-effective nanoscale manufacturing.

This partnership leverages Brewer Science’s strength based on more than 30 years of experience in advanced semiconductor materials and process solutions with Arkema’s experience of more than 20 years in block copolymer (BCP) technology and manufacturing. This combination of manufacturing and support expertise will accelerate the introduction of DSA material technology for next-generation lithography applications.

“We are excited to work with Arkema to bring this technology to market,” said Dr. Daniel Sullivan, Director of Brewer Science’s Semiconductor R&D. “Brewer Science has earned the reputation for bringing value to customers and moving the industry forward. Our goal is to provide a turnkey DSA process so customers can obtain all the materials and process knowledge needed to implement DSA quickly and cost-effectively. Combining each company’s expertise in materials and manufacturing will allow us to deliver a robust solution to the industry.”

“Arkema is committed to deliver high-quality DSA materials to the Semiconductor Market. This unique partnership will accelerate the introduction of a commercial solution in the market and provide a unique support to our future customers built on the strength of both companies,” said Ian Cayrefourcq, Scientific Director of Arkema.

Both companies plan to bring process stability to DSA by providing BCP in volume to support an entire node life with a single batch while also offering a wide range of process flexibility through a full suite of DSA materials and Arkema’s proven BCP blending process.

We are in a historic era for consolidation among semiconductor manufacturers. Included in the announced mergers and acquisitions this year alone are:

Semiconductor Market Consolidation. (Slide from: Dr. Rutger Wijburg, Sr. Vice President and General Manager, GLOBALFOUNDRIES; keynote at Semicon Europa

Semiconductor Market Consolidation. (Slide from: Dr. Rutger Wijburg, Sr. Vice President and General Manager, GLOBALFOUNDRIES; keynote at Semicon Europa)

According to a recent article in the Wall Street Journal by Don Clark, the reasons for this market consolidation are relatively new to the industry: slowing growth and rising costs.

In the past, chip makers used acquisitions to obtain new technology. But, Clark writes that a different reason is becoming more prominent: “Many recent deals resemble consolidation waves in older industries, motivated mainly by trimming costs in areas like manufacturing, sales and engineering.”

For example, Avago projects that it can gain $750 million in annual savings starting in 2017 after it integrates Broadcom, according to Clark.

The article cites figures from Dealogic stating that the industry has seen $100.6 Billion in mergers and acquisitions in 2015 so far, compared to $37.7 Billion for all of 2014.

And that total is poised to go higher.

“Bloomberg reported last week that four chip companies — Analog Devices Inc., Maxim Integrated Products Inc., SanDisk Corp. and Fairchild Semiconductor International Inc. — were in talks concerning different deal options… ‘It’s buy or be sold,’ summed up Alex Lidow, chief executive of Efficient Power Conversion Corp., a startup he co-founded in 2007 after 30 years leading chip maker International Rectifier Corp,” Clark writes.

In the early 90s Siborg Systems Inc. released MicroTec: a semiconductor device and process simulator that has become used by more than 140 Universities and more than 40 semiconductor companies for computationally extensive simulations. Siborg has recently made a new version available particularly targeting educational use of the software. Examples are created for a few popular semiconductor process and device text books including “Solid State Electronic Devices” by Ben Streetman, Sanjay Banerjee, Pearson Education, March 9, 2014; “Modern Semiconductor Devices for Integrated Circuits” by Chenming C. Hu, Pearson Education, March 22, 2009; and “Fabrication Engineering at the Micro- and Nanoscale” by Stephen A. Campbell, Oxford University Press, September 5, 2007.

Microtec is a significantly simplified semiconductor TCAD tool while still being a powerful modeling tool for industrial semiconductor process/device design. It is an efficient tool for computationally extensive simulations arising in modeling of power semiconductor devices with large dimensions, and is particularly useful for devices made of SiC, GaN and other materials with a wide bandgap.

The program was widely used in education, including Universities such as UC Berkeley, Waseda University, Tokyo Institute of Technology, and the University of Waterloo; it allows students to learn basic ideas about the modern semiconductor device design in a realistic model environment and create their own virtual devices using realistic process flow and test their performance. MicroTec is an easy-to-use simplified TCAD tool that can be learned Microtec within a few hours while still offering robustness and realistic semiconductor process and device simulation. The program also is an asset to those who need to understand the physics of semiconductor devices without knowing much about computers or numerical methods and who do not have much time for learning new process/device simulation tools.

A simplified limited version of MicroTec semiconductor device simulator was also published by John Wiley and Sons, 2000-02-08, in “Semiconductor Devices Explained: Using Active Simulation”, by Ton Mouthaan, Professor of the Twente University in the Netherlands.

MicroTec is able to simulate 2D silicon process modeling including epitaxy, oxidation, diffusion and implantation and 2D steady-state semiconductor device simulation including SOI-MOSFET, MOSFET, BJT, JFT,IGBT, DMOS, Schottky devices, Solar Cells, etc.

Based on the diffusion-drift model, Microtec employs finite difference technique on a rectangular, automatically generated mesh.

One of the features of MicroTec is the ability to run on virtually any PC. Being a true 32-bit application for Windows, MicroTec needs very little RAM allocation. With no memory threshold, the program can be even be run on computers with only a few Mbytes of memory if a modest number of mesh nodes is used. Typical simulation only take minutes of CPU time on a regular PC.

Microtec includes three main software tools:

  • SiDif for 2D semiconductor process simulation including implantation, diffusion, oxidation and epitaxy
  • SemSim for steady-state 2D semiconductor device simulation
  • SiBGraf for 2D and 1D graphics

German chemical company Evonik Industries AG and Japanese FPD production equipment manufacturer SCREEN Finetech Solutions Co., Ltd. have signed a contract for a strategic partnership in order to offer best performance of perfectly matched iXsenic (R) semiconductor material, equipment, and process.

iXsenic is a solution-processable inorganic metal oxide semiconductor which is applied under ambient conditions. No vacuum environment is needed which results in process simplifications, high yield and cost advantages. iXsenic is best applied via slot-die coating.

The Japanese company SCREEN Finetech Solutions Co., Ltd. provides a wide range of equipment and services for the FPD industry including high-quality coating machines like slot-die/slit coater (Linearcoater*). In the FPD industry SCREEN FT is the global technology and market leader for such equipment. Evonik and SCREEN FT have been running application tests with iXsenic on Linearcoater for years. Now they have signed a contract for a strategic partnership to jointly promote the iXsenic technology. “With SCREEN FT we have found the perfect partner”, says Prof. Ralf Anselmann, Vice President at Evonik. “The advantages are obvious: Evonik offers the semiconductor iXsenic, SCREEN FT provides the production equipment. Thus, material, equipment and process can be perfectly matched to the customer’s needs. With this setup we will offer optimal service and performance to our customers.”

Material layers like photo resists are already coated today in the Electronics industry but semiconductive layers are normally applied via vapor deposition (CVD or PVD). With the solution-processable iXsenic material it is now possible to coat the semiconductor. “With our partnership we expect faster and easier integration of the iXsenic technology at the customer’s site including higher reliability for mass production” comments Mitsumasa Kodama, Deputy General Manager at SCREEN Holdings. “And not to forget: with perfectly matched material and equipment mobilities above 10 cm²/Vs are not just a champion’s value but reality.”

The strategic partnership of Evonik and SCREEN FT is the consequent next step to strengthen the commercialization of the iXsenic technology.

New S$150 million joint investment is expected to create 60 jobs for highly skilled scientists, engineers and researchers.

SINGAPORE, October 19, 2015 – Applied Materials, Inc. today announced it plans to establish a new R&D laboratory in Singapore in collaboration with the Agency for Science, Technology and Research (A*STAR). The S$150 million joint investment will focus on developing advanced semiconductor technology to fabricate future generations of logic and memory chips.

The S$150 million joint lab will be housed within A*STAR’s new R&D cluster at Fusionopolis Two and will feature a 400 square meter Class 1 cleanroom with state-of-the-art semiconductor process equipment that has been custom designed and built by Applied Materials. The facility will be staffed by 60 highly skilled researchers and scientists, working together with extended research teams at A*STAR’s other research institutes.

The joint lab combines Applied Materials’ leading expertise in materials engineering with A*STAR’s multi-disciplinary R&D capabilities. A*STAR’s Institute of Microelectronics (IME), Institute of Materials Research and Engineering (IMRE), and Institute of High Performance Computing (IHPC) will contribute to research in low-defect processing, ultra-thin film materials, materials analysis and characterization, and modelling and simulation in many areas. The joint lab is also supported by The Singapore Economic Development Board, and is in line with its efforts to promote leading-edge R&D and advanced manufacturing activities. The intention is for products developed by the joint lab to be manufactured by Applied Materials in Singapore. In addition, Applied Materials plans to conduct experiments on the synchrotron at the Singapore Synchrotron Light Source (SSLS) and work with the National University of Singapore where a new beamline for semiconductor applications is to be developed. Funding for the construction of the new beamline is supported by the National Research Foundation.

Mr. Gary Dickerson, President and Chief Executive Officer of Applied Materials, Inc., said, “A*STAR and the government of Singapore have been great R&D partners for Applied Materials. We are excited to expand our collaboration to develop advanced semiconductor technology for extending Moore’s Law. Applied Materials’ leading expertise in materials engineering can help solve the challenges of producing future generations of logic and memory chips.”    

Mr. Lim Chuan Poh, Chairman, A*STAR, said, “This collaboration will catalyse the development of emerging technologies for the global electronics market and advance Singapore’s position as a key R&D hub for the industry. The joint lab reaffirms A*STAR’s multi-disciplinary R&D capabilities to drive innovation in the electronics sector, a key growth area for Singapore’s economy, and will generate further economic value through the creation of good jobs.”

“The joint lab will strengthen capabilities for Applied Materials in Singapore, as we expand from advanced manufacturing to early stage R&D and designing global products,” said Mr. Russell Tham, Corporate Vice President & Regional President South East Asia, Applied Materials, Inc. “Successful public-private partnerships, leveraging complementary strengths, help create new forms of value from Singapore and keep the local industry competitive.”

Prof. Raj Thampuran, Managing Director, A*STAR, said, “The new joint lab takes the longstanding collaboration between Applied Materials and A*STAR to the next level, and will marshal our combined strengths in research, development, innovation and industrial applications. This technology will pioneer new processes and techniques to advance the fabrication of semiconductor devices.”

The new joint lab marks Applied Materials’ second collaboration with A*STAR. In 2012, Applied and A*STAR’s IME formed a Center of Excellence in Advanced Packaging in Singapore to develop advanced 3D chip packaging technology.

CEA-Leti today announced that it has joined the GLOBALSOLUTIONS ecosystem as an ASIC provider, specifically to support GLOBALFOUNDRIES’ 22FDX (TM) technology platform.

Launched this summer, GLOBALFOUNDRIES’ 22FDX technology platform is the industry’s first 22nm FD-SOI semiconductor technology developed specifically to meet the ultra-low-power requirements of the next generation of connected devices. The versatility of the 22FDX platform is a result of unmatched design flexibility and intelligence, including software-controlled transistor body-biasing that provides real-time trade-offs between power and performance. Delivering FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies, the platform enables a new level of innovations on next-generation chips and sets new standards in-terms of user experience for Internet of Things (IoT), mainstream mobile, RF, and networking applications.

GLOBALSOLUTIONS was created more than five years ago to spur innovation in the semiconductor industry and assure chip designers receive world-class service from design conception to production. The ecosystem combines GLOBALSOLUTIONS’ internal resources with a broad spectrum of partners to efficiently enable the fastest time-to-volume for foundry customers.

“Together with our design services partners, we are able to offer a full suite of services and comprehensive turnkey solutions that confirms GLOBALFOUNDRIES’ leadership in providing high-performance customized products in the FD-SOI and ASIC markets,” said Gary Patton, chief technology officer and head of worldwide R&D at GLOBALFOUNDRIES. “Our expanded partnership with Leti further reflects our commitment to find design implementations that will accelerate time-to-volume and deliver ultra-low-power solutions to our customers.”

Earlier this year, Leti assigned a team of experts to GLOBALFOUNDRIES’ Dresden, Germany, Fab 1 to support ramp up of the platform. As an ecosystem partner, Leti will provide GLOBALFOUNDRIES’ customers circuit-design IP, including for its back-bias feature for FD-SOI, which enables exceptional performance at very low voltages with low leakage.

“This strategic partnership with GLOBALFOUNDRIES positions Leti to help a broad range of designers utilize FD-SOI technology’s significant strengths in ultra-low-power and high performance in their IoT and mobile devices with 22nm technology,” said Marie Semeria, Leti CEO. “In addition, it gives both sides’ customers increased access to our respective technologies. This kind of partnership is a key part of Leti’s global strategy.”

Rudolph Technologies, Inc. announced today that it has purchased Stella Alliance, LLC, a Massachusetts-based semiconductor inspection technology intellectual property (IP) portfolio company. Stella Alliance’s patented illumination, auto-focus, and image acquisition technology significantly enhances the ability to identify certain critical defects not visible with current techniques. With this acquisition, Rudolph expects to add a next-generation, high-resolution inspection system to its portfolio of solutions in the second quarter of 2016. Additionally, the acquired technology is able to handle large rectangular substrates, extending Rudolph’s inspection portfolio footprint into growing unserved segments of microelectronic device manufacturing.

Paul McLaughlin, Rudolph’s chairman and chief executive officer, stated, “We expect the addition of this patented technology to bring a competitive advantage to our customers by addressing current inspection limitations, while helping Rudolph maintain the dominant market share in the back-end inspection arena.”

The technology was developed to overcome the challenges of detecting residue-related defects that traditional technologies can miss. These defects can have a significant impact on the interconnect quality, such as incomplete etch of bond or bump pads, faint copper bridging and stringers at the bottom of vias and high aspect ratio trenches in fan-out wafer level packaging (FOWLP), wafer-level chip scale packaging (WLCSP) and embedded die applications.

In addition, the technology provides the high resolution needed to inspect highly warped rectangular panels (larger than 500mm). This complements Rudolph’s JetStep (R) S line of steppers, which are panel-ready today. With this technology, Rudolph will offer a more comprehensive panel solution, which involves printing, inspecting and yield analysis, to quickly ramp lines and maintain high productivity.

“This new technology helps Rudolph provide configurable systems to meet current and future challenges faced by our customers,” said Mike Goodrich, vice president and general manager of Rudolph’s Inspection Business Unit. “As interconnect technology becomes increasingly important in back-end 3D and 2.5D applications, we anticipate this inspection technique to be a key component for our customers’ process control strategies.”

The company does not expect the transaction to have an impact on the results of operations for the 2015 third quarter. Terms of the transaction were not disclosed.

 

The official Call for Papers has been issued for the 2016 Symposia on VLSI Technology and Circuits, to be held at the Hilton Hawaiian Village June 13-16, 2016 (Technology) and June 15-17, 2016 (Circuits). The deadline for paper submissions to both conferences is January 25, 2016. The late-news paper submissions deadline for the Symposia on VLSI Technology is March 24, 2016; there is no late-news submission for the Symposium on VLSI Circuits. Complete details for paper submission can be found online at: http://www.vlsisymposium.org/authors/

For the past 28 years, the combined annual Symposia on VLSI Technology and Circuits has provided an opportunity for the world’s top device technologists, circuit and system designers to engage in an open exchange of leading edge ideas at the world’s premier mid-year conference for microelectronics technology. Held together since 1987, the Symposia on VLSI Technology and Circuits have alternated each year between sites in the US and Japan, enabling attendees to learn about new directions in the development of VLSI technology & circuit design through the industry’s leading research and development presentations.

The comprehensive technical programs at the two Symposia are augmented with short courses, invited speakers and several evening panel sessions. Since 2012, the Symposia have presented joint focus sessions that include invited and contributed papers on topics of mutual interest to both technology and circuit attendees.

The Symposium on VLSI Technology seeks technical innovation and advances in all aspects of IC technology, as well as the emerging IoT (Internet of Things) field, including:

  • IoT systems & technologies, including ultra-low power, heterogeneous integration, sensors, connectivity, power management, digital/analog, microcontrollers and application processors
  • Stand-alone & embedded memories, including DRAM, SRAM, non-volatile and emerging memory technologies
  • CMOS Technology, microprocessors & SoCs, including scaling, VLSI manufacturing concepts and yield optimization
  • RF / analog  /digital technologies for mixed-signal SoC, RF front end; analog, mixed-signal I/O, high voltage, imaging, MEMS, integrated sensors
  • Process & material technologies, including advanced transistor process and architecture, modeling and reliability; alternate channel; advanced lithography, high-density patterning; SOI and III-V technologies, photonics, local interconnects and Cu/optical interconnect scaling
  • Packaging technologies & System-in-Package (SiP)
  • Photonics Technology & “Beyond CMOS” devices 

The Symposium on VLSI Circuits seeks original papers showcasing technical innovations and advances in the following areas:

  • Digital circuits and processor techniques for standalone and embedded processors
  • Memory circuits, architectures & interfaces for volatile and non-volatile memories, including emerging memory technologies
  • Clock generation and distribution for high-frequency digital and mixed-signal applications
  • Analog and mixed-signal circuits, including amplifiers, filters and data converters
  • Wireline receivers & transmitters, including circuits for inter-chip and long-reach applications
  • Wireless receivers & transmitters, including circuits for WAN, LAN, PAN, BAN, inter-chip and mm-wave applications
  • Power management circuits, including battery management circuits, voltage regulators, energy harvesting circuits
  • Application-oriented circuits & VLSI systems, imagers, displays, and sensors for biomedical and healthcare applications

Joint technology and circuits focus sessions feature invited and contributed papers highlighting innovations and advances in materials, processes, devices, integration, reliability and modeling in the areas of advanced memories, 3D integration, and the impact of technology scaling on advanced circuit design. Submissions are strongly encouraged in the following areas of joint interest:

  • Design in scaled technologies: scaling of digital, memory, analog and mixed-signal circuits in advanced CMOS processes
  • Design enablement: design for manufacturing, process/design co-optimization, on-die monitoring of variability and reliability
  • Embedded memory technology & design: SRAM, DRAM, Flash, PCRAM, RRAM, MRAM and NVRAM memory technologies
  • 3D & heterogeneous integration: power and thermal management; inter-chip communications, SIP architectures and systems

Papers sought for “big integration”

Authors are encouraged to submit papers that showcase innovations that extend beyond single ICs and into the module, including focus areas in the Internet of Things (IoT), industrial electronics, “big data” management, biomedical applications, robotics and smart cars. These topics will be featured in focus sessions as part of the program.

Best Student Paper Award

Awards for best student paper at each Symposia will be chosen, based on the quality of the papers and presentations. The recipients will receive a financial award, travel cost support and a certificate at the opening session of the 2017 Symposium. For a paper to be reviewed for this award, the author must be enrolled as a full-time student at the time of submission, must be the lead author and presenter of the paper, and must indicate on the web submission form that the paper is a student paper.

The Full Service Foundry division of ams AG, a leading provider of high performance analog ICs and sensors, today announced a further expansion of its industry-leading 0.35µm High-Voltage CMOS specialty process platform. The advanced “H35” process provided by the High-Voltage process expert ams now includes a set of truly voltage scalable transistors offering significant area and performance improvements.

The new voltage scalable High-Voltage NMOS and PMOS transistor devices are optimized for various drain-source voltage levels (VDS) from 20V to 100V and provide significant lower on-resistance thus resulting in area savings. Using an optimized 30V NMOS transistor in power management applications instead of a fixed 50V transistor results in an area saving of approximately 50%. A 60V optimized NMOS device results in 22% less area when compared to a standard 120V NMOS transistor. Foundry customers developing complex High-Voltage analog/mixed-signal applications such as large driver and switching ICs instantly benefit from more dies per wafer.

The area optimized devices are ideally suited for a wide range of applications such as MEMS drivers, motor drivers, switches and power management ICs used in automotive, medical and industrial products. ams’ Full Service Foundry division is among first foundries worldwide offering true voltage scalable transistors to its foundry customers. Being fully automotive (ISO/TS 16949) and medical (ISO 13485) certified, ams supports highest quality requirements from its customers.

“Being among first foundries worldwide offering true voltage scalable devices, proofs ams’ expertise in developing specialty High-Voltage CMOS processes and providing excellent manufacturing services. ams’ foundry team is looking forward to teaming up with product developers who are creating advanced High-Voltage products”, said Markus Wuchse, general manager of ams’ Full Service Foundry division. “Our hitkit, the ams benchmark Process Design Kit as well as our High-Voltage process expertise enable our partners to optimize their HV integrated circuits towards area and on-resistance, which immediately results in more dies per wafer.”

This latest High-Voltage process extension is an add-on to the company’s ”More Than Silicon” portfolio, under which ams provides a package of technology modules, intellectual property, cell libraries, engineering consultancy and services to help customers successfully develop advanced analog and mixed-signal circuit designs based on its specialty technologies.

By Peter Connock, chairman of memsstar and co-chair of the European SEMI Secondary Equipment and Applications Special Interest Group

The dramatic shift from the trend for increasingly advanced technology to a vast array and volume of application-based devices presents Europe with a huge opportunity. Europe is a world leader in several major market segments – think automotive and healthcare as two examples – and many more are developing and growing at a rapid rate. Europe has the technology and manufacturing skills to satisfy these new markets but they must be addressed cost effectively – and that’s where the use of secondary equipment and related services comes in.

Secondary Equipment & Applications ─ Enabling the Internet of “Everything”

While Moore’s Law continues to drive the production of advanced devices, the broadening of the “More than Moore” market is poised to explode. All indicators are pointing to a major expansion in applications to support a massive increase in data interchange through sensors and related devices. The devices used to support these applications will range from simple sensors to complex packages but most can, and will, be built by “lower” technology level manufacturing equipment.

This equipment will, in many cases, be required to be “remanufactured” and “repurposed” but will allow semiconductor suppliers to extend the use of their depreciated equipment and/or bring in additional equipment, matched to their process needs, at reduced cost. In many cases this older equipment will need to be supported by advanced manufacturing control techniques and new test and packaging capabilities.

SEMI market research shows that investment in “legacy” fabs is important in manufacturing semiconductor products, including the emerging Internet of Things (IoT) class of devices and sensors, and remains a sizeable portion of the industries manufacturing base:

  • 150mm and 200mm fab capacity represent approximately 40 percent of the total installed fab capacity
  • 200mm fab capacity is on the rise, led by foundries that are increasing 200mm capacity by about 7 percent through to 2016 compared to 2012 levels
  • New applications related to mobility, sensing, and IoT are expected to provide opportunities for manufacturers with 200mm fabs

SEMI_Europe1

Out of the total US$ 27 billion spent in 2013 on fab equipment and US$ 31 billion spent on fab equipment in 2014, secondary fab equipment represents approximately 5 percent of the total, or US$ 1.5 billion, annually, according to SEMI’s 2015 secondary fab equipment market report. For 2014, 200mm fab investments by leading foundries and IDMs resulted in a 45 percent increase in spending for secondary 200mm equipment.

SEMI_Europe2

Establishing a Vibrant and Professional Secondary Equipment Industry in Europe

Secondary equipment will form at least part of the strategy of almost anyone manufacturing or developing semiconductors in Europe. In many cases, it is an essential capability for competitive production. As the secondary equipment industry increases its strategic importance to semiconductor manufacturers and researchers it is critical that the corresponding supply chain ensures a supply of quality equipment, support and services to meet rapidly developing consumer needs. Common challenges across the supply chain include:

  • How to generate cooperation across Europe between secondary equipment users and suppliers and what sort of cooperation is needed?
  • How to ensure the availability of sufficient engineering resource to support the European secondary installed base?
  • Are there shortages of donor systems or critical components that are restricting the use of secondary equipment and, if so, how might this be resolved

Join us at SEMICON Europa to find out more about Europe’s Secondary Industry

Europe’s secondary industry will be in the spotlight during two sessions at SEMICON Europa 2015:

The sessions are organized by the SEMI SEA Europe Group and are open to everyone associated with the secondary industry, be they device manufacturer or supplier, interested in the development of a vibrant industry providing critical support to cost effective manufacturing in Europe.

About the Secondary Equipment and Applications (SEA) Group

The SEA group in Europe is working on activities to:

  • Increase market knowledge
  • Create a European network of relevant customers, suppliers and representative organizations
  • Establish quality and standards in secondary equipment
  • Catalyze Engineering resource development
  • Understand key issues facing the European Secondary industry and any required project activity (e.g., impact of EU laws such as RoHS2, parts supply, etc.)