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Worldwide silicon wafer area shipments increased during the first quarter 2015 when compared to fourth quarter 2014 area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

Total silicon wafer area shipments were 2,637 million square inches during the most recent quarter, a 3.4 percent increase from the 2,550 million square inches shipped during the previous quarter, resulting in a new quarterly volume shipment record. New quarterly total area shipments are 11.6 percent higher than first quarter 2014 shipments.

“Total silicon shipment volumes for the first quarter of this year surpassed the record high reached in the third quarter of last year,” said Ginji Yada, chairman of SEMI SMG and general manager, International Sales & Marketing Department of SUMCO Corporation. “Silicon shipments for the most recent quarter benefited from the strong market momentum the semiconductor market enjoyed last year.”

Quarterly Silicon Area Shipment Trends

Millions of Square Inches

Q1 2014

Q3 2014

Q4 2014

Q1 2015
Total

2,363

2,597

2,550

2,637

*Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers, epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

The Silicon Manufacturers Group acts as an independent special interest group within the SEMI structure and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.

SEMI is the global industry association serving the nano- and micro-electronic manufacturing supply chains. SEMI maintains offices in Bangalore, Beijing, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C.   For more information, visit www.semi.org.

SEMI today announced the SEMICON West 2015 technical and business program agenda tackling the most important issues facing the future of semiconductor manufacturing. In addition to the exposition with over 650 exhibitors planned, SEMICON West will feature over 180 total hours of programs —  including free technical, applications and business programs as well as an extensive lineup of exclusive programs. Discounted registration for SEMICON West ends June 5.

Exclusive programs include the three-day Semiconductor Technology Symposium (STS) conference, a comprehensive technology and business conference addressing the key issues driving the future of semiconductor manufacturing and markets. STS is offered as an intensive professional conference, with paid guaranteed classroom-style seating, lunch, and networking breaks. Aligned with the latest inputs from technology roadmaps, sessions at the STS will focus on the significant trends shaping near-term semiconductor technology and market developments in key areas including:

  • Semiconductor Manufacturing: Current Challenges and Future Opportunities for the Supply Chain
  • Adjacent Spaces: Strategies for Executing Expansion into Adjacent Markets
  • Packaging: The Very Big Picture 
  • Packaging: Digital Health and Semiconductor Technology
    • Test Vision 2020 (Automated Test Equipment)
    • Interconnect Technology for High-Performance Computing
    • Making Sense of the Lithography Landscape: Cost and Productivity Issues below 14nm and Path(s) to 5nm
    • Scaling Transistors: HVM Solutions Below 14nm; Getting to 5nm
    • Flexible Hybrid Electronics for Wearable Applications – Challenges/Solutions
    • Interconnect Technology for High-Performance Computing

In addition to the STS conference, SEMICON West continues to feature a full set of complimentary programs, including keynote addresses, executive panels, technical and business sessions.

The Tuesday Keynote Panel includes Jo De Boeck, senior VP and CTO of imec; Mike Campbell, senior VP of Engineering at Qualcomm; and Subashish Mitra, associate professor at Stanford University who will tackle the issue of “Scaling the Walls of sub-14nm Manufacturing.” Doug Davis, senior VP and GM, IoT Group at Intel, will present the Wednesday Keynote.

SEMICON West TechXPOT conference sessions on the exhibition floor are also provided free to exposition attendees. Sessions at the TechXPOTs are developed for engineers, technologists, and business leaders seeking solutions to key technology challenges, exploring cutting-edge and future technology developments and assessing their impact on the semiconductor supply chain. Developed in conjunction with SEMI technical committees, partner organizations, and technologists, the TechXPOT agenda will provide a deeper view of key technology developments and their business impact:

  • What’s Next for MEMS?
  • Automating Semiconductor Test Productivity
  • Emerging Generation Memory Technology: Update on 3D NAND, MRAM and RRAM
  • Materials Session: Contamination Control in the Sub-20nm Era
  • Subsystem and Component Suppliers at Critical Cross Roads to Deliver on Yield and Productivity
  • Equipment and Materials Opportunities for Flexible Hybrid Electronics
  • Packaging Session: Auto Utopia — Gearing up Semiconductor to Turn Dreams to Reality
  • The Evolution of the New 200mm Fab for the Internet of Everything
  • Monetizing the IoT: Opportunities and Challenges for the Semiconductor Sector
  • CMP Technical and Market Trends
  • Factory of the (Near) Future: Using Industrial IoT in Semiconductor Manufacturing Sector
  • Update on Industry Status of 450mm

Other key programs include:

  • Silicon Innovation Forum Conference is a two-day innovation conference that includes a one-day startup/investor forum and a one-day research forum.
  • Sustainable Manufacturing Forum is a three-day event starting on July 13; it delves into issues of Regulatory Compliance, Sustainable Technologies, and Sustainable Supply Chains.
  • “Bulls and Bears,” a session where a panel of technical and financial thought leaders address provocative questions on the state of the microelectronics industry and the outlook for the future.

Discounted registration for SEMICON West 2015 (www.semiconwest.org) through June 5.  Early-bird pricing for the Semiconductor Technology Symposium (STS), Test Vision 2020, and Sustainable Manufacturing Forum (SMF) applies through June 5. Premier sponsors of SEMICON West 2015 include Applied Materials, KLA-Tencor, and Lam Research.

Semiconductor Research Corporation (SRC) announced today that Ken Hansen has been appointed SRC’s new President and Chief Executive Officer (CEO), effective June 1.

Hansen’s professional experience includes serving as Vice President and Chief Technology Officer (CTO) at Freescale Semiconductor since 2009. Hansen replaces retiring SRC President and CEO Larry Sumney who guided the organization for more than 30 years since its inception in 1982. SRC’s many accolades over the years include being the recipient of the National Medal of Technology in 2007.

“SRC under Larry Sumney’s leadership has made an indelible impact on the advancement of technology during the past three decades, and we congratulate Larry on his retirement and salute him for his contributions to the semiconductor industry,” said Mike Mayberry, Intel Corporate Vice President and Director of Components Research who is SRC Board Chairman. “We also welcome Ken Hansen to his new role guiding SRC, and we look forward to Ken’s leadership helping SRC reach new heights in an era where basic research and development is as critical as ever.”

Prior to his CTO role at Freescale, Hansen led research and development teams for more than 30 years in multiple senior technology and management positions at Freescale and Motorola. Hansen holds Bachelor and Master of Science degrees in Electrical Engineering from the University of Illinois where he has been recognized as an ECE (Department of Electrical and Computer Engineering) Distinguished Alumni.

In his new role at SRC, Hansen intends to build on the consortium’s mission of driving focused industry research to both advance state-of-the-art technology and continue to create a pipeline of qualified professionals who will serve as next-generation leaders for the industry.

“SRC also has an opportunity to strengthen its core by recruiting new members to gain more leverage to fund industry wide solutions for some of the challenging technology roadblocks that are ahead of us,” said Hansen.

“The model that SRC has developed is unmatched in the industry and has proven to be extremely significant. The industry would not be where it is today without the contributions of SRC under the leadership and vision of Larry Sumney,” Hansen continued.

Meanwhile, Sumney’s decorated career began in 1962 at the Naval Research Laboratory. He later directed various other research programs at Naval Electronics Systems Command and the Office of the Undersecretary of Defense — including the Department of Defense’s major technology initiative, Very High Speed ICs (VHSIC) —before agreeing to lead SRC following its formation by the Semiconductor Industry Association.

Under his leadership, SRC has also formed wholly owned subsidiaries managing the Nanoelectronics Research Initiative (NRI), the Semiconductor Technology Advanced Research network (STARnet) and the SRC Education Alliance, among other programs. Sumney received a Bachelor of Physics from Washington and Jefferson (W&J) College, which recognized him with the 2012 Alumni Achievement Award, and a Master of Engineering Administration from George Washington University.

“I have enjoyed a front row seat in the development of today’s technology-based economy and advancement of humanity through the semiconductor industry,” said Sumney. “I am completely confident that SRC is well positioned and will continue to flourish, to seed breakthrough innovation and help provide the people and ideas to keep the U.S. semiconductor industry competitive and prosperous in years to come.”

Additional industry leaders with strong ties to SRC commended Sumney for his service over the years while supporting Hansen’s appointment.

“Over more than 30 years, Larry Sumney’s visionary leadership of SRC has steered one of the world’s most transformative industries through times of tremendous growth and innovation,” said John Kelly, Senior Vice President, Solutions Portfolio and Research for IBM.  “I’ll personally miss working with Larry, but also have tremendous respect for and confidence in Ken Hansen, and we look forward to collaborating with him to drive the next generation of research in this vital industry.”

“Larry’s leadership and vision are key reasons why SRC’s research has played a fundamental role behind many of the most significant semiconductor innovations of the last three decades,” said Lisa Su, AMD president and CEO and a former SRC student. “Ken’s broad industry experience makes him ideally suited to lead the next phase of the SRC, as the organization continues to expand its capabilities and provide the basic research and development foundation needed to further accelerate innovation across the industry.”

The 61st annual IEEE International Electron Devices Meeting (IEDM) has issued a Call for Papers seeking the world’s best original work in all areas of microelectronics research and development. The paper submission deadline is Monday, June 22, 2015 at 23:59 p.m. Pacific Time.

Overall, the 2015 IEDM is seeking increased participation in the areas of ‘Beyond CMOS’ devices, flexible devices, neuromorphic computing, power devices, sensors for the Internet of Things (IoT) and variation/reliability.

In addition, Special Focus Sessions will be held on the following topics: neural-inspired architectures; 2D materials and applications; flexible electronics and applications; power devices and reliability on non-native substrates; and silicon-based nanodevices for detection of biomolecules.

The 2015 IEDM will take place at the Washington, DC Hilton Hotel from December 7-9, 2015, preceded by a collection of 90-minute afternoon Tutorial sessions on Saturday, Dec. 5, and a full day of Short Courses on Sunday, Dec. 6. On Wednesday the conference will continue the successful Entrepreneurs Luncheon sponsored by IEDM and EDS Women in Engineering.

At IEDM each year, the world’s best scientists and engineers in the field of microelectronics from industry, academia and government gather to participate in a technical program of more than 220 presentations, along with a special Luncheon Presentation on Tuesday, Dec. 8 and a variety of panels, special sessions, Short Courses, IEEE/EDS award presentations and other events spotlighting more leading work in more areas of the field than any other conference.

Papers in the following areas are encouraged:
– Circuit and Device Interaction
– Characterization, Reliability and Yield
– Display and Imaging Systems
– Memory Technology
– Modeling and Simulation
– Nano Device Technology
– Power and Compound Semiconductor Devices
– Process and Manufacturing Technology
– Sensors, MEMS and BioMEMS

Advanced Semiconductor Engineering, Inc. and TDK Corporation announced today that both companies will enter into an agreement to establish a joint venture company to manufacture IC embedded substrates using TDK’s SESUB (Semiconductor Embedded SUBstrate) technology. ASE and TDK plan to own 51 percent and 49 percent, respectively, of the newly created entity. The indicative name of the joint venture company will be ASE Embedded Electronics Incorporated, and its manufacturing facility is planned to be located in the Nantze Export Processing Zone, Kaohsiung City, Taiwan.

TDK developed its proprietary SESUB technology by harnessing its signature technologies in ultrafine processing and materials. The SESUB technology enables semiconductor chips to be thinned down to as low as 50 μm and embedded in a four-layer plastic substrate. TDK’s SESUB technology provides numerous advantages, such as enabling miniaturization by reducing the mounting area on substrates and a thinner profile by achieving a 300 μm thickness. Other advantages include excellent thermal dissipation characteristics, which offer greater design flexibility and inter-chip connection that enhances EMI performance.

ASE SiP solutions using SESUB technology will offer a robust embedded solution in enabling a wide number of applications such as PMIC, sensors and RF tuners etc. The planned joint venture business model aims to leverage on TDK’s success in delivering SESUB technology to the market with ASE’s capabilities in advanced packaging, test and module level solutions for semiconductor miniaturization.

“With the anticipated need for further miniaturization and weight reduction of smartphones and wearable devices in the future, demand for semiconductors embedded in substrates, such as SESUBs, is expected to increase globally,” says Mr. Takehiro Kamigama, CEO and President of TDK Corporation. “TDK has already been producing SESUBs at its Kofu Plant, but to meet the anticipated increase in demand, it will establish the joint company in Taiwan to add to its production capacity with ASE, which possesses technologies including assembly of IC packages and other items, and boasts a world-class performance record in product testing. The joint venture establishment will create a structure for full-scale mass production,” added Mr Takehiro Kamigama.

“ASE serves a diverse group of customers including several major players supplying to the portable and wearable consumer market and is a leader in SIP integration using its advanced packaging solutions and test expertise. TDK, on the other hand, has a proven proprietary embedded substrate technology addressing the market needs of integrating more chips and functions, higher performance, lower power consumption and better heat dissipation onto a smaller form factor,” says Dr Tien Wu, COO, ASE Group. “We see this powerful alliance as an added value to the ASE SIP ecosystem and together, catapulting TDK’s SESUB technology into the forefront as an industry standard,’’ added Dr. Tien Wu.

The proposed establishment of and capital injection into the joint venture company will be subject to various regulatory approvals or consents (including but not limited to the approvals of the Taiwan Fair Trade Commission and Export Processing Zone Administration).

Microchip Technology Incorporated, a provider of microcontroller, mixed-signal, analog and Flash-IP solutions, and Micrel, Incorporated today announced that Microchip has signed a definitive agreement to acquire Micrel for $14.00 per share.  Micrel shareholders may elect to receive the purchase price in either cash or shares of Microchip common stock.  The acquisition price represents a total equity value of about $839 million, and a total enterprise value of about $744 million, after excluding Micrel’s cash and investments on its balance sheet of approximately $95 million.

“We are pleased to have Micrel become part of the Microchip team. Micrel’s portfolio of Linear and Power Management products, LAN solutions and Timing and Communications products, as well as their strong position in the Industrial, Automotive and Communications markets, complement many of Microchip’s initiatives in these areas.”

“We believe that this acquisition provides the best vehicle for us to realize significant value for Micrel’s shareholders and is a fantastic outcome for our employees and customers, as well as the opportunity to scale up to the much stronger sales and manufacturing platforms of Microchip,” said Ray Zinn, President and CEO of Micrel.

Concurrent with this announcement, Microchip announced that its Board of Directors has authorized an increase in the existing share repurchase program to 20.0 million shares of common stock from the approximately 2.5 million shares remaining under the prior authorization.  Under this program, in the next several months, Microchip intends to repurchase the approximate number of shares it issues in the Micrel acquisition, which is expected to result in the transaction having the accretive effects of a cash transaction from a financial perspective.  The acquisition is expected to be mildly dilutive to Microchip’s non GAAP earnings per share immediately after the close, but is expected to be accretive in the first full quarter after completion of the repurchase of the number of shares issued in the transaction.

As previously announced by Micrel, the Micrel Board of Directors created a Transaction Committee entirely comprised of independent directors on January 20, 2015 to consider a range of strategic alternatives, including a potential sale of Micrel. The process leading up to the merger agreement with Microchip was overseen by the Transaction Committee which unanimously recommended the approval of the merger agreement to Micrel’s Board of Directors.

The acquisition has been unanimously approved by the Boards of Directors of each company and is expected to close early in the third quarter of calendar 2015.

All of Micrel’s directors and certain executive officers have signed voting agreements with Microchip under which they must vote in favor of the merger.

BY GREG SHUTTLEWORTH, Global Product Manager at LINDE ELECTRONICS

The market expectations of modern electronics technology are changing the landscape in terms of performance and, in particular, power consumption, and new innovations are putting unprecedented demands on semiconductor devices. Internet of Things devices, for example, largely depend on a range of different sensors, and will require new architectures to handle the unprecedented levels of data and operations running through their slight form factors.

The continued shrinkage of semiconductor dimensions and the matching decreases in microchip size have corresponded to the principles of Moore’s Law with an uncanny reliability since the idea’s coining in 1965. However, the curtain is now closing on the era of predictable / conventional size reduction due to physical and material limitations.

Thus, in order to continue to deliver increased performance at lower costs and with a smaller footprint, different approaches are being explored. Companies can already combine multiple functions on a single chip–memory and logic devices, for example–or an Internet of Things device running multiple types of sensor through a single chip.

We have always known that we’d reach a point where conventional shrinking of semiconductor dimensions would begin to lose its effect, but now we are starting to tackle it head on. A leading U.S. semiconductor manufacturer got the ball rolling with their FinFET (or tri–gate) design in 2012 with its 3D transistors allowing designs that minimize current leakage; other companies look set to bring their own 3D chips to market.

At the same time, there’s a great deal of experimentation with a range of other approaches to semiconductor redesign. Memory device manufacturers, for instance, are looking to stack memory cells vertically on top of each other in order to make the most of a microchip’s limited space. Others, meanwhile, are examining the materials in the hope of using new, more efficient silicon–like materials in their chips.

Regardless of the approach taken, however, this step change in microchip creation means new material demands from chip makers and new manufacturing techniques to go with them.

The semiconductor industry has traditionally had to add new materials and process techniques to enhance the performance of the basic silicon building blocks with tungsten plugs, copper wiring / CMP, high–k metal gates, for example. Now, however, it is beginning to become impossible to extend conventional materials to meet the performance requirements. Germanium is already added to Si to introduce strain, but its high electron mobility means Germanium is also likely to become the material of the Fin itself and will be complemented by a corresponding Fin made of III–V material, in effect integrating three semiconductor materials into a single device.

Further innovation is required in the areas of lithography and etch. This is due to the delay in production suitability of the EUV lithography system proposed to print the very fine structures required for future technology nodes. Complex multi-patterning schemes using conventional lithography are already underway to compensate for this technology delay, requiring the use of carbon hard masks and the introduction of gases such as acetylene, propylene and carbonyl sulphide to the semiconductor fab. Printing the features is only half of the challenge; the structures also need to be etched. The introduction of new materials always presents some etch challenges as all materials etch at slightly different rates and the move to 3D structures, where very deep and narrow features need to be defined through a stack of different materials, will be a particularly difficult challenge to meet.

The microchip industry has continuously evolved to deliver amazing technological advances, but we are now seeing the start of a revolution in microchip design and manufacturing. The revolution will be slow but steady. Such is the pattern of the microchip industry, but it will need a succession of new materials at the ready, and, at Linde, we’re prepared to make sure the innovators have everything they need.

Microchip Technology Inc., a provider of microcontroller, mixed-signal, analog and Flash-IP solutions, through its Silicon Storage Technology (SST) subsidiary, and GLOBALFOUNDRIES, a provider of advanced semiconductor manufacturing technology, today announced the full qualification and availability of SST’s 55nm embedded SuperFlash non-volatile memory (NVM) on GLOBALFOUNDRIES’ 55nm Low Power Extended (LPx)/ RF enabled platform. The qualification of GLOBALFOUNDRIES’ 55nm, split-gate-cell SuperFlash technology-based process was performed according to JEDEC standards. This process technology also met the requirements of AEC-Q100 Grade 1 qualification with an ambient temperature range of -40°C to 125°C, and demonstrated endurance of 100K program/erase cycles with more than 20 years of data retention at 150°C.

According to global information company IHS, the automotive semiconductor market is forecast to reach $31B in 2015, with a strong 7.5 percent improvement over 2014. Embedded Flash-based semiconductors are a key component of this market segment.

“Embedded SuperFlash memory is a de-facto standard at foundries for microcontrollers, smartcards, and various system-on-chip devices,” said Mark Reiten, vice president of Technology Licensing for SST, a wholly owned subsidiary of Microchip. “GLOBALFOUNDRIES has been a great partner for building a state-of-the-art 55nm embedded SuperFlash platform, and we are already engaged with several customers in various market segments. We are pleased to partner with GLOBALFOUNDRIES, to further strengthen our market leadership in embedded Flash-based devices.”

“GLOBALFOUNDRIES recognizes the need to provide a low-cost embedded Flash platform for secure ID, mixed-signal, NFC/RF and next-generation IoT applications,” said Gregg Bartlett, senior vice president of product management at GLOBALFOUNDRIES. “Our deep collaboration with SST has resulted in qualified, commercially available 55nm SuperFlash technology on GLOBALFOUNDRIES’ high-yielding 55nm low-power process platform, which will enable high-performance solutions for customers across key market segments.”

GLOBALFOUNDRIES’ 55nm LPx/RF platform, complete with eNVM technology, is available to customers now. This platform technology offers a fast path-to-product solution, with a custom library of off-the-shelf eNVM IP blocks that are optimized for specific MCU product applications.

MagnaChip Semiconductor Corporation, a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products, today announced that Tae Young Hwang has resigned as the Company’s Chief Operating Officer and President and from all other officer and director positions with the Company and its subsidiaries. Mr. Hwang’s resignation was effective as of April 30, 2015.

The Company also announced that Young-Joon Kim, the Company’s Interim Chief Executive Officer and General Manager, Display Solutions Division, will assume Mr. Hwang’s duties as the Company’s principal operating officer. In addition, the Company announced that Seung-Hoon Lee, the Company’s Senior Vice President of Manufacturing Operations, will oversee the company’s semiconductor manufacturing services operations on a day-to-day basis and will report to Mr. Kim. Mr. Lee, who has 28 years of manufacturing operations experience in the semiconductor industry, is the current head of the company’s fabrication facility in Gumi, South Korea, and previously served as the head of the company’s fabrication facility in Cheongju, South Korea.

A new study coauthored by Wellesley economist, Professor Daniel E. Sichel, reveals that innovation in an important technology sector is happening faster than experts had previously thought, creating a backdrop for better economic times ahead.

The Producer Price Index (PPI) of the United States suggests that the prices of semiconductors have barely fallen in recent years. The slow decline in semiconductor prices stands in sharp contrast to the rapidly falling prices reported from the mid-1980s to the early 2000s, and has been interpreted as a signal of sluggish innovation in this key sector.

The apparent slowdown puzzled Sichel and his coauthors, David M. Byrne of the Federal Reserve Board, and Stephen D. Oliner, of the American Enterprise Institute and UCLA–particularly in light of evidence that the performance of microprocessor units (MPUs), which account for about half of U.S. semiconductor shipments, has continued to improve at rapid pace. After closely examining historical pricing data, the economists found that Intel, the leading producer of MPUs, dramatically changed the way it priced these chips in the mid-2000s–roughly the same time when the slowdown reported by government data occurs. Prior to this period, Intel typically lowered the list prices of older chips to remain competitive with newly introduced chips. However, after 2006, Intel began to keep chip prices relatively unchanged over their life cycle, which affected official statistics.

To obtain a more accurate assessment of the pace of innovation in this important sector, Sichel, Byrne, and Oliner developed an alternative method of measurement that evaluates changes in actual MPU performance to gauge the rate of improvement in price-performance ratios. The economists’ preferred index shows that quality-adjusted MPU prices continued to fall rapidly after the mid-2000s, contrary to what the PPI indicates–meaning that worries about a slowdown in this sector are likely unwarranted.

According to Sichel, these results have important implications, not only for understanding the rate of technological progress in the semiconductor industry but also for the broader debate about the pace of innovation in the U.S. economy.

“These findings give us reason to be optimistic,” said Sichel. “If technical change in this part of the economy is still rapid, it provides hope for better times ahead.”

Sichel and his coauthors also acknowledge that their results raise a new puzzle. “In recent years,” they write, “the price index for computing equipment has fallen quite slowly by historical standards. If MPU prices have, in fact, continued to decline rapidly, why have prices for computers–which rely on MPUs for their performance–not followed suit?” The researchers believe it is possible that the official price indexes for computers may also suffer from measurement issues, and they are investigating this possibility in further work.

“How Fast Are Semiconductor Prices Falling,” coauthored by Daniel E. Sichel, Wellesley College and NBER; David M. Byrne, Federal Reserve Board; and Stephen D. Oliner, American Enterprise Institute and UCLA, is available as an NBER working paper and is online at http://www.nber.org/papers/w21074 and https://www.aei.org/publication/how-fast-are-semiconductor-prices-falling/.