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Cohu, Inc. (NASDAQ:COHU) and Xcerra Corporation (NASDAQ:XCRA) today announced they have entered into a definitive merger agreement pursuant to which Cohu will acquire Xcerra for a combination of cash and stock. The acquisition is expected to make Cohu a global leader in semiconductor test, with combined sales for Cohu and Xcerra in excess of $800 million for the last twelve months.

Upon the closing of the transaction, Xcerra shareholders will be entitled to receive $9.00 in cash and 0.2109 of a share of Cohu common stock, subject to the terms of the definitive agreement. Based on the closing price of Cohu common stock as of May 7, 2018, the transaction values Xcerra at $13.92 per share, or approximately $796 million in equity value, with a total enterprise value of approximately $627 million, after excluding Xcerra’s cash and marketable securities net of the debt on its balance sheet as of January 31, 2018. The transaction value represents a premium of 8.4% to Xcerra’s closing price on May 7, 2018, and a premium of 15.4% to Xcerra’s 30-day average closing price.

“This proposed acquisition is a powerful combination of two complementary companies that will accelerate our strategy to diversify our product offerings and strengthen Cohu’s position as a global leader in back-end semiconductor equipment. The depth and breadth of the combined product portfolios, engineering and product development resources, as well as the global customer support platforms will enable us to deliver comprehensive semiconductor back-end solutions that better meet the future needs of our customers,” commented Luis Müller, Cohu’s President and CEO.

Mr. Müller continued, “The acquisition of Xcerra increases our addressable market to approximately $5 billion across handlers, contactors, test and inspection, further strengthening our ability to fully capitalize on the secular growth opportunities in the automotive, IoT, industrial and mobility markets. We are excited to welcome the Xcerra team to Cohu and look forward to an efficient completion of the transaction, with a focus on delivering long-term value to our customers, employees and shareholders.”

Commenting on the proposed acquisition, David Tacelli, Xcerra’s President and CEO, stated, “We are very pleased to be joining forces with Cohu to create a global leader in back-end semiconductor test. Together, we will be an even stronger and more competitive company with far reaching long-term benefits to our customers and employees. I am extremely proud of what the Xcerra team has accomplished over the past several years and look forward to the exciting possibilities we can achieve together with Cohu.”

The transaction is expected to be immediately accretive to non-GAAP earnings per share and generate over $20 million of annual run-rate cost synergies within 2 years of closing, excluding stock-based compensation and other charges.

 

UnitySC, a developer of advanced inspection and metrology solutions, today announced the opening of its Asia subsidiary, Unity Semiconductor Limited Company (UnitySC Asia). The entity was established to deliver enhanced customer support for UnitySC’s growing installed base of inspection and metrology tools throughout the region. UnitySC Asia is headquartered at Tai-Yuan Hi-Tech Industrial Park, Jubei City, Hsinchu, Taiwan, and has field offices in Singapore, Korea, and Shanghai, as well as a presence in Japan.

“Asia is experiencing very strong growth in the semiconductor industry,” said Kamel Ait-Mahiout, CEO, UnitySC. “We’re seeing customers ramp up new advanced packaging technologies in their factories to meet the demands of multiple market drivers. It is evident that being local is quickly becoming a requirement, so that we can provide application development along with our existing customer support capabilities. UnitySC Asia is a key piece of our growth strategy, following the recent acquisition of HSEB GmbH, which broadened our process control portfolio.”

Seventy percent of UnitySC’s global customer installed base is located in Asia. The region’s rapid growth is driven by expanding markets: wireless and connectivity, as well as automotive, which includes electric vehicles and autonomous driving. These trends are fueling increased demand for advanced packaging, power devices and sensors.

“While UnitySC has long maintained a customer service presence in Asia, growth in the region calls for a local sales force as well as experienced application engineers who can respond to complex process questions quickly,” said Patrick Desjardins, general manager, UnitySC Asia. “Moreover, as our installed base of tools grows in the region, we will be able to provide the high-quality support our customers have come to expect directly from our local offices.”

UnitySC is growing in the Asia Pacific region and is staffed to support all areas of service. The local team includes engineers, experienced application engineers and customer service personnel, and also offers on-site customer support and assistance.

 

Semtech Corporation (Nasdaq:SMTC), a supplier of high performance analog, mixed-signal semiconductors and advanced algorithms, today announced it has acquired substantially all the assets of IC Interconnect, Inc. (“ICI”), a privately-held, U.S.-based company that provides contract wafer bumping and related services to the electronics industry. The acquisition is expected to add 42 employees located in Colorado Springs, Colo.

Under the terms of the purchase agreement, Semtech acquired ICI assets for a cash purchase price of approximately $7 million and assumed certain obligations going forward. Semtech funded the purchase price using its current cash assets. The Company does not expect the deal to have any material impact to its earnings.

Next-generation Protection platforms require advanced technological capabilities to deliver the right combination of the highest performance and smallest footprint. Semtech and ICI have demonstrated their ability to produce market leading solutions such as the Semtech Z-Pak™ platform with more than 25 billion Z-Pak-based devices shipped into high-end consumer applications such as smartphones, wearables and tablets.

“The addition of ICI is aimed at further enhancing our U.S. R&D capabilities by developing and ramping our next-generation Z-Pak platform – the Z-UltraTM platform,” stated Mark Costello, Vice President and General Manager of Semtech’s Protection Products Group. “The “Z-Ultra” platform will significantly enhance Semtech’s ability to address new challenges created by further shrinking of silicon geometries and will drive quantum improvements in system-level performance over our current platform.”

“ICI has combined manufacturing process innovation and operational excellence to deliver cost-effective wafer level packages to Semtech since 2001 and we are now excited to become part of the Company,” stated Curt Erickson, President of ICI.

To meet growing market demand for high-density 2.5D and 3D stacked semiconductor solutions, Silicon Valley-based ALLVIA, Inc. has expanded its in-house capabilities to include the formation of through-quartz vias (TQV) ranging from 15 microns in diameter and 100 microns deep to 50 microns in diameter and 250 microns deep. ALLVIA’s new TQV solution significantly improves the performance of 3D-ICs by creating IC interconnects with lower parasitic capacitance than can be achieved with the earlier generation of through-silicon via (TSV) technology.

he company had been outsourcing the production of via holes in the fused silica (quartz) that it uses, but its newly added capability brings all via-drilling operations in-house, expanding ALLVIA’s intellectual property and reducing the cost of production. The company will continue to apply its proprietary technology to fill the high-aspect-ratio via holes with copper plating to fabricate finished interposer products.

Sergey Savastiouk, CEO of ALLVIA, said, “Performing our own via drilling in fused silica allows us to improve turnaround times and production volumes for our customers while also delivering better quality using our state-of-the-art technology for copper plating, chemical mechanical polishing and deep via thin-film deposition.”

In addition to providing via foundry services, ALLVIA applies its technology in manufacturing and selling ultra-thin quartz interposers that form the electrical connections between a silicon chip and a printed circuit board.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has started construction work for the next expansion phase of its corporate headquarters. The new building will house EVG’s “Manufacturing III” facility, which will more than double the floor space for the final assembly of EVG’s systems.

“With our innovative manufacturing solutions for the high-tech industry as well as new biomedical applications, we operate in very dynamic markets with great future prospects,” stated Dr. Werner Thallner, executive operations and financial director at EV Group. “In light of the high capacity utilization in all areas of our existing facilities, as well as the positive market outlook, we decided to implement our plans for building our Manufacturing III facility this year. This will support our long-term growth targets at our corporate headquarters in St. Florian am Inn.”

EVG Manufacturing III Photo 1

The new Manufacturing III building, adjacent to the new test room site that was opened just a few months ago, will be built next to the river Inn. The ultramodern building will provide approximately 4,800 square meters of additional space in total, which will benefit not only manufacturing but other departments as well. In addition to an expansion of warehouse space, a new delivery area with a dedicated packaging site designed for cleanroom equipment will be created, along with an airfreight security zone and new truck loading docks for the shipment of the completed systems to EVG’s worldwide customers.

The construction of the new Manufacturing III building is set to be completed in early 2019.

Mentor, a Siemens business, has announced that several tools in its Calibre® nmPlatform and Analog FastSPICE (AFS™) Platform have been certified by TSMC for the latest versions of TSMC’s 5nm FinFET and 7nm FinFET Plus processes. Mentor also announced it has updated its Calibre nmPlatform tools in support of TSMC’s Wafer-on-Wafer (WoW) stacking technology. These Mentor tools and TSMC’s new processes will enable mutual customers to more quickly deliver silicon innovations in high-growth markets.

“Mentor continues to increase its value to the TSMC ecosystem by offering more features and solutions in support of our most advanced processes,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “By continuing to innovate leading-edge electronic design automation (EDA) technologies for our new processes, Mentor is again proving its commitment to TSMC and our mutual customers.”

Mentor’s enhanced tools for TSMC 5nm FinFET and 7nm FinFET Plus processes

Mentor worked closely with TSMC to certify various tools in Mentor’s Calibre nmPlatform – including Calibre nmDRC™, Calibre nmLVS™, Calibre PERC™, Calibre YieldEnhancer, and Calibre xACT™ – for TSMC’s 5nm FinFET and 7nm FinFET Plus processes. These Calibre solutions now have new measurements and checks including, but not limited to, supporting extreme ultraviolet (EUV) lithography requirements jointly defined with TSMC. Mentor’s Calibre nmPlatform team is also working with TSMC to address physical verification runtime performance by enhancing scalability of multi-CPU runs to improve productivity. Mentor’s AFS platform, including the AFS Mega circuit simulator, is also now certified for TSMC’s 5nm FinFET and 7nm FinFET Plus processes.

Mentor’s enhanced tools for TSMC’s WoW stacking technology

Mentor made enhancements to its Calibre nmPlatform tools in support of the WoW packaging. Enhancements include DRC and LVS signoff for dice with backside through-silicon vias (BTSV), interface alignment and connectivity checks for die-to-die as well as die-to-package stacking. Further enhancements include parasitic extraction on backside routing layers, interposers with through-silicon vias (TSVs), and interface coupling.

Calibre Pattern Matching for TSMC’s 7nm SRAM Array Examination Utility

Mentor worked closely with TSMC to integrate Calibre Pattern Matching into TSMC’s 7nm SRAM Array Examination Utility. This flow helps customers to ensure their SRAM implementations are constructed to meet process requirements. This automation enables customers to tape out successfully. The SRAM Array Examination Utility is available to TSMC’s customers for 7nm production.

“TSMC continues to develop innovative silicon processes that enable our mutual customers to bring to market many of the world’s most advanced ICs,” said Joe Sawicki, vice president and general manager of the Design-to-Silicon Division at Mentor, a Siemens business. “We, at Mentor, are proud to not only lead the way in certifying our platforms for TSMC’s latest processes, we are also proud of our close partnership with TSMC in developing new technologies that help customers achieve production silicon faster.”

To learn more, visit Mentor at booth #408 at TSMC’s Technology Symposium on May 1, 2018 at the Santa Clara Convention Center in Santa Clara, California.

 

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its continued collaboration with TSMC to further 5nm and 7nm+ FinFET design innovation for mobile and high-performance computing (HPC) platforms. The Cadence® digital, signoff and custom/analog tools have achieved the latest Design Rule Manual (DRM) and SPICE certification for the TSMC 5nm and 7nm+ processes. The corresponding process design kits (PDKs) are now available for download.

5nm and 7nm+ Digital and Signoff Tool Certification

Cadence provides a fully integrated digital flow from implementation to final signoff that has been certified by TSMC for the latest versions of the 5nm and 7nm+ processes. For the 7nm+ process, the Cadence full-flow includes the Innovus™ Implementation System, Quantus™ Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, Physical Verification System (PVS) and Layout-Dependent Effect (LDE) Electrical Analyzer. For the 5nm process, the Cadence certified tools include the Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, the layout vs. schematic (LVS) function in PVS and LDE Electrical Analyzer.

Cadence digital and signoff features available for the 7nm process are also available for the 5nm and 7nm+ process. Some of these features include cut-metal handling throughout the design flow, via-pillar support, clock mesh and bus-routing. These capabilities can enable customers to successfully design mobile and HPC systems with improved power, performance and area (PPA) while reducing iterations and achieving their cost and performance objectives.

In addition, Cadence has delivered new enhancements focused on EUV support at key layers and associated new design rules that specifically support the 5nm and 7nm+ processes. Some of the other newest enhancements for the 7nm+ process include cell pin support, Self-Heating Effect (SHE) and heatsink support.

Specifically for the 5nm process, Cadence digital and signoff tools offer high-resistance resistor support, router compliance for new rules and new extraction support including additional resistor layer modeling and other middle end-of-line (MEOL) features.

5nm and 7nm+ Custom/Analog Tool Certification

The certified custom/analog tools include the Spectre® Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre RF, and Spectre Circuit Simulation, as well as the Virtuoso® product suite, which consists of the Virtuoso Schematic Editor, Virtuoso Layout Suite and Virtuoso Analog Design Environment.

By using the latest capabilities and design methodologies included with the Virtuoso Advanced-Node Platform, customers can achieve an improvement in custom physical design throughput versus traditional non-structured design methodologies, while maintaining a similar effort and cycle time via the advanced capabilities in the Virtuoso and Spectre tools.

Cadence delivered several custom/analog enhancements specifically to support the TSMC 5nm and 7nm+ process technologies. For example, Cadence introduced an accelerated custom placement and routing methodology, which enables customers to improve productivity and meet their power, multiple patterning, density and EM requirements. In addition, Cadence introduced universal poly grid snapping, asymmetric coloring support and voltage-dependent rule support for power/ground rails specifically for the 5nm process.

5nm and 7nm+ Library Characterization Tool Flow

The Virtuoso Liberate™ Characterization Solution and the Virtuoso Variety™ Statistical Characterization Solution have been validated to deliver Liberty libraries including advanced timing, noise and power models. The solutions utilized innovative methods to characterize Liberty Variation Format (LVF) models, enabling accurate process variation signoff for low-voltage applications and the ability to create EM models enabling signal EM optimizations and signoff.

“Using the latest design rules and PDKs, our customers have started designing complex SoCs on our most advanced process technologies,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Through the continuation of our collaboration with Cadence, we’ve certified their tools and flows for 5nm and 7nm+ designs, which can enable our customers to achieve their design goals within a fast, predictable timeline.”

“Over the past few years, Cadence has taken on a broader role in facilitating advanced-node adoption due to the optimizations and performance improvements across our digital and signoff and custom/analog tool suites,” said Dr. Chin-Chi Teng, corporate vice president and general manager in the Digital & Signoff Group at Cadence. “We’ve expanded our collaboration with TSMC by developing tools and flows that support their 5nm and 7nm+ process technologies, and our latest TSMC certifications are enabling us to support customers using the most advanced process nodes.”

Synopsys, Inc. (Nasdaq: SNPS) today announced certification of the Synopsys Design Platform with TSMC’s latest Design Rule Manual (DRM) for advanced 7-nanometer (nm) FinFET Plus process technology. With several test chips taped out and production designs currently under development by multiple customers, this certification by TSMC enables a wide range of designs from high-performance computing and high-density to low-power mobile applications using the Synopsys Design Platform.

This certification is a milestone for TSMC’s extreme ultraviolet lithography (EUV) process that enables significant area savings while maintaining high performance when compared to non-EUV process nodes.

The Synopsys Design Platform, anchored by Design Compiler Graphical synthesis and IC Compiler™ II place-and-route tools, has been enhanced to take full advantage of TSMC’s 7-nm FinFET Plus for high-performance designs. Design Compiler Graphical is capable of automatically inserting via pillar structures to boost performance and prevent signal electromigration (EM) violations, and can pass the information to IC Compiler II for further optimization. It also automatically applies non-default rules (NDR) during synthesis and performs layer-aware optimization to improve design performance. These optimizations, including IC Compiler II bus routing, continue throughout the place-and-route flow to meet stringent delay-matching requirements of high-speed network.

PrimeTime® timing analysis advanced waveform propagation (AWP) and parametric on-chip variation (POCV) technologies have been optimized to address increased waveform distortion and non-Gaussian variation effects of higher performance and lower voltage operation. In addition, PrimeTime’s physically-aware signoff has been expanded to support via-pillars.

Synopsys has enhanced the Design Platform to perform physical implementation, parasitic extraction, physical verification, and timing analysis to support TSMC’s WoW technology. The physical implementation flow with IC Compiler II provides full support for wafer staking designs, from initial die floorplan preparation to placement and assignment of bumps to implementation of die routing. Verification is done by IC Validator for DRC/LVS checks, and Synopsys’ StarRC tool performs parasitic extraction.

“Ongoing collaboration with Synopsys and early customer engagements on TSMC’s 7-nanometer FinFET Plus process technology are delivering differentiated platform solutions that help our mutual customers bring innovative new products to market faster,” said Suk Lee, senior director of the Design Infrastructure Marketing Division at TSMC. “Certification of the Synopsys Design Platform enables our mutual customers’ designs in our first mass-production, EUV-enabled technology.”

“Our collaboration with TSMC on their mass-production 7-nanometer FinFET Plus process allows companies to confidently begin designing their increasingly large SoC and multi-die chips with the highly-differentiated Synopsys Design Platform,” said Michael Jackson, corporate vice president of marketing and business development for the Design Group at Synopsys. “Certification on TSMC’s 7-nanometer FinFET Plus process enables our customers to benefit from significant power, performance, and area improvements of an advanced EUV process, while accelerating time-to-market for their differentiated products.”

GLOBALFOUNDRIES today announced that Arbe Robotics has selected GF’s 22FDX® process for its groundbreaking patented imaging radar that will achieve fully automated system capabilities and enable safer driving experiences for autonomous vehicles.

Arbe Robotics’ radar is the first in the world to show real-time 1 degree resolution and provide the required enhancements for sensors and ADAS technologies. Arbe’s goal is to build a sensing system with high resolution and zero false alarms, so vehicles will be able to make decisions relying exclusively on the data provided by the radar. Leveraging GF’s 22FDX FD-SOI technology, the new chipset is increasing the amount of transmitting and receiving channels on a chip and allowing for better integration to Arbe’s proprietary processor.

The rise of autonomous driving is changing the automobile semiconductor market, which is expected to grow to an estimated $54 billion by 2023. This is driven by a need for new technologies that promise to enhance the driving experience, such as 360-degree surround view monitoring, which requires high resolution and long-range capabilities. GF’s 22FDX process provides the superior RF performance, power consumption, low noise, and high digital density to increase range and improve resolution for these applications.

As the first company to demonstrate ultra-high-resolution at a wide field of view, Arbe Robotics’ radar technology can detect pedestrians and obstacles at a range of 300 meters, in any weather and lighting conditions. The processor creates a full 3D shape of the objects and their velocity, and classifies targets using their radar signature.

“Arbe Robotics’ imaging radar is optimized for providing a real-time 4D picture of the environment at ultra high resolution,” said Kobi Marenko, CEO of Arbe Robotics. “The collaboration with GF is a significant step towards archiving the high-performance level required for autonomous driving safety. With over a decade of automotive industry experience, GF’s 22FDX delivers a performance on-demand, energy-efficient solution for our current and future radar technology needs.”

“The trend of autonomous driving is progressing rapidly, and with it is the need for high-resolution radar. The future will rely on a mix of real-time maps, advanced navigation software, and live data from vehicle sensors,” said Mark Granger, vice president of automotive at GF. “That’s why GF is pleased Arbe Robotics has chosen our 22FDX platform, together bringing valuable attributes that support the explosive growth of the autonomous driving industry.”

GF’s 22FDX platform is a part of the company’s AutoPro™ solutions, which provides customers with additional access to manufacturing services that support the full range of AEC-Q100 quality grades from Grade 2 to Grade 0 to minimize certification efforts and speed time-to-market.

SPTS Technologies, an Orbotech company and a supplier of advanced wafer processing solutions for the global semiconductor and related industries, announced today that it has been awarded the coveted Queen’s Award for Enterprise in Innovation 2018. The award recognizes SPTS’s development of novel physical vapor deposition (PVD) process solutions for Fan-Out Wafer Level Packaging (FOWLP) of semiconductor devices. Some of the advanced features and functionality developed for SPTS’s 300mm Sigma®fxP PVD system was made possible with funding assistance from a Welsh Government R&D grant. In addition to assessing the degree of innovation, the judging panel also evaluated SPTS on its corporate responsibility, which included employee affairs, customer and supplier relationships, and its impact on the environment and contribution to society.

“We are extremely proud to be recognized with the Queen’s Award for Enterprise in Innovation,” stated Kevin Crofton, Corporate Executive Vice President at Orbotech and President of SPTS Technologies. “We provide advanced wafer processing equipment to the world’s leading semiconductor and microelectronics manufacturers, and an ongoing program of research and development coupled with our ability to commercialize our innovation has been key to building and sustaining a profitable business. This award belongs to our entire global organization – from those directly involved in the development of our advanced PVD solutions for the fast growing FOWLP application sector, to those who sold, manufactured, installed and supported the many 300mm Sigma systems that we’ve shipped into our customer base.”

Mr Crofton added, “The success of our wafer processing solutions for advanced packaging is a testament to the quality and competitiveness of UK developed technologies and products in the global markets. We are also very pleased to share credit for this award with the Welsh Government who demonstrated their commitment with the R&D grant that helped fund this and other advanced packaging development programs here at SPTS.”

Economy Secretary, Ken Skates said: “Huge congratulations to SPTS on winning another Queens Award for Enterprise and Innovation. SPTS is a prominent global business in South East Wales and an increasingly successful exporter, and this prestigious award is a well-deserved recognition of the company’s hard work and innovation.”

“The Welsh Government is proud to work with dynamic and forward thinking companies such as SPTS and we are pleased to have supported the company’s project to design and develop advanced packaging processes for semiconductors. There is no doubt that companies like SPTS are increasingly vital to our economy which is why my Economic Action Plan, which was published in December, seeks to support businesses to innovate, introduce new products and services and rise to the challenges of the future.”

The Queen’s Awards for Enterprise are the UK’s most prestigious business awards, given only to companies or individuals who are outstanding in their field. Previously known as the Queen’s Awards to Industry, the Queen’s Awards for Enterprise were introduced in 1966 to acknowledge businesses with outstanding performance in three categories – International Trade, Innovation and Sustainable Development.  The awards are open to any company operating in the UK and are announced annually on 21 April, The Queen’s birthday.