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A lithographic method for TSV alignment to embedded targets was evaluated using in-line stepper self metrology, with TIS correction.

BY WARREN W. FLACK, Veeco Instruments, Plainview, NY and JOHN SLABBEKOORN, imec, Leuven, Belgium

Demand for consumer product related devices including backside illuminated image sensors, interposers and 3D memory is driving advanced packaging using through silicon via (TSV) [1]. The various process flows for TSV processing (via first, via middle and via last) affect the relative levels of integration required at the foundry and OSAT manufacturing locations. Via last provides distinct advantages for process integration, including minimizing the impact on back end of line (BEOL) processing, and does not require a TSV reveal for the wafer thinning process. Scaling the diameter of the TSV significantly improves the system performance and cost. Current via last diameters are approximately 30μm with advanced TSV designs at 5 μm [2].

Lithography is one of the critical factors affecting overall device performance and yield for via last TSV fabrication [2]. One of the unique lithography requirements for via last patterning is the need for back-to-front side wafer alignment. With smaller TSV diameters, the back-to- front overlay becomes a critical parameter because via landing pads on the first level metal must be large enough to include both TSV critical dimension (CD) and overlay variations, as shown in FIGURE 1. Reducing the size of via landing pads provide significant advantages for device design and final chip size. This study evaluates 5μm TSVs with overlay performance of ≤ 750nm.

Alignment, illumination and metrology

Lithography was performed using an advanced packaging 1X stepper with a 0.16 numerical aperture (NA) Wynne Dyson lens. This stepper has a dual side alignment (DSA) system which uses infrared (IR) illumination to view metal targets through a thinned silicon wafer [3]. For the purposes of this study and its results, the wafer device side is referred to as the “front side” and the silicon side is referred to as the “back side.” The side facing up on the lithography tool is the back side of the TSV wafer, as shown in FIGURE 2.

The top IR illumination method for viewing embedded alignment targets, shown in Fig. 2, provides practical advantages for integration with stepper lithography. Since the illumination and imaging are directed from the top, this method does not interfere with the design of the wafer chuck, and does not constrain alignment target positioning on the wafer. The top IR alignment method illuminates the alignment target from the back side using an IR wavelength capable of transmitting through silicon (shown as light green in FIGURE 2) and the process films (shown in blue). In this configuration the target (shown in orange) needs to be made from an IR reflective material such as metal for optimal contrast. The alignment sequence requires that the wafer move in the Z axis in order to shift alignment focus from the wafer surface to the embedded target.

Back-to-front side registration was measured using a metrology package on the lithography tool which uses the DSA alignment system. This stepper self metrology package (DSA-SSM) includes routines to diagnose and compensate for measurement error from having features at different heights. For each measurement site the optical metrology system needs to move the focus in Z between the resist feature and the embedded feature. Therefore angular differences between the Z axis of motion, the optical axis of the alignment camera, and the wafer normal will contribute to measurement error for the tool [3]. The quality of the wafer stage motion is also very important because a significant pitch and roll signature would result in a location dependent error for embedded feature measurement, which would complicate the analysis.

If the measurement operation is repeatable and consistent across the wafer, then a constant error coming from the measurement tool, commonly referred to as tool induced shift (TIS), can be characterized using the method of TIS calibration, which incorporates measurements at 0 and 180 degree orientations. The TIS error—or calibration—is calculated by dividing the sum of offsets for the two orientations by two [4]. While the TIS calibration is effective for many types of measurements for planar metrology, for embedded feature metrology, the quality of measurement and calibration also depend on the quality and repeatability of wafer positioning, including tilt. In previous studies, the registration data obtained from the current method were self consistent and proved to be an effective inspection method [3, 5]. However given the dependencies affecting TIS calibration for embedded feature metrology, it is desirable to confirm the registration result using an alternate metrology method [5]. In order to independently verify the DSA-SSM, overlay data dedicated electrical structures were designed and placed on the test chip.

Electrical verification of TSV alignment is performed after complete processing of the test chip and relies on the landing position of a TSV on a fork-to-fork test structure in the embedded metal 1 (damascene metal). When the TSV processing is complete the copper filled TSV will make contact with metal 1. The TSV creates a short between the two sets of metal forks, allowing measurement of two resistance values which can be translated into edge measurements. For the case of ideal TSV alignment, the two resistances are equal. The measurement resolution of the electrical structure is limited by the pitch of the fork branches. In this study resolution is enhanced by creating structures with four different fork pitches. A similar fork-to-fork structure rotated 90 degrees is used for the Y alignment. Using this approach both overlay error and size of the TSV in both X and Y can be electrically determined [6].

Experimental methods

This study scrutinizes image placement performance by examining DSA optical metrology repeatability after TSV lithography, and then comparing this optical registration data with final electrical registration data.

The TSV-last process begins with a 300mm device wafer with metal 1, temporarily bonded to a carrier for mechanical support as shown in FIGURE 3. The back side of the silicon device wafer (light green) is thinned by grinding and then polished smooth by chemical mechanical planarization (CMP). The TSV is imaged in photoresist (red) and etched through the thinned silicon layer. FIGURE 3 depicts the complete process flow including the TSV, STI and PMD etch, TSV fill, redis- tribution layer (RDL) and de-bonding from carrier. The aligned TSV structure must land completely on the metal 1 pad (dark blue).

TSV lithography is done with a stepper equipped with DSA. The photoresist is a gh-line novolac based positive- tone material requiring 1250mJ/cm2 exposure dose with a thickness of 7.5μm [5]. The TSV diameter is 5μm, and the silicon thickness is 50μm. TSV etching of the silicon is performed by Bosch etching [7]. Tight control of lithography and TSV etching is required to insure that vias land completely on metal 1 pads, as shown in FIGURE 1.

Acceptable features for DSA-SSM metrology need to fit the via process requirements for integration. Since the TSV etch process is very sensitive to pattern size and density, the TSV layer is restricted to one size of via, and the DSA-SSM measurement structure is constructed using this shape. The design of the DSA-SSM measurement structure uses a cluster of 5μm vias with unique grouping and clocked rotation to avoid confusion with adjacent TSV device patterns during alignment.

FIGURE 4 shows two different focus offsets of DSA camera images of the overlay structure. For this structure, the reference metal 1 feature (outlined by the blue ring) and the resist pattern feature (outlined by the red ring) are not in the same focal plane. For a silicon thickness of 50μm, focusing on one feature will render the other feature out of focus, requiring each feature to have its own focus offset, which is specified in the metrology measurement recipe.

Optical registration process control

This study leveraged a sampling plan of 23 lithography fields with 5 measurements per field, resulting in a total of 115 measurements per wafer. Since the full wafer layout contains 262 fields, this sampling plan provides a good statistical sample for monitoring linear grid and intrafield parameters.

In the initial run, the overlay settings were optimized using the DSA-SSM metrology feedback and then the parameters were fixed to investigate overlay stability over a nine-week period. Trend charts for mean and 3σ for seven TSV lots are shown in FIGURE 5. Each measurement lot consists of 8 wafers, with 115 measure- ments per wafer, and all data is corrected for TIS on a per lot basis using measurements of a single wafer at 0 and 180 degree orientations [3]. The lot 3σ is consistently less than 600nm over the nine-week period. There appears to be a consistent small Y mean error (blue diamond) that could be adjusted to improve subsequent overlay results. With a Y mean correction applied, the registration data shows mean plus 3σ ≤ 600nm.

Validating TSV alignment and in-line optical metrology

Two TSV last test chip wafers were completely processed to the stage that they can be electrically measured. TABLE 1 shows the registration numbers confirming a good match between the two metrology methods. It is important to note that an extra translation step is performed between the optical and the electrical measurement: the TSV etch.

In this analysis the TSV etch is assumed to be perfectly vertical. From the data we can conclude that the TSV etch is indeed vertical enough not to interfere with the overlay data. Otherwise this would show as translation or scaling effects between the two metrology methods.


The lithographic method for TSV alignment to embedded targets was evaluated using in-line stepper self metrology, with TIS correction. Registration data was collected over a nine-week period to characterize the stability of TSV alignment. With corrections applied, the registration data demonstrates mean plus 3σ ≤ 600nm. The in-line optical registration data was then correlated to detailed electrical measurements performed on the same wafers at the end of the process to provide independent assessment of the accuracy of the optical data. Good correlation between optical and electrical data confirms the accuracy of the in-line optical metrology method, and also confirms that the TSV etch through 50μm thick silicon is vertical.


1. Vardaman, J. et. al., TechSearch International: Advanced Packaging Update, July 2016.
2. Van Huylenbroeck, S. et. al., “Small Pitch High Aspect Ratio Via Last TSV Module”, The 66th Electronic Components and Technology Conference, Los Vegas, NV, May 2016.
3. Flack, W. et. al., “Optimization of Through Si Via Last Lithography for 3D Packaging”, Twelfth International Wafer- Level Packaging Conference, San Jose, CA, October 2015.
4. Preil, M. et. al, “Improving the Accuracy of Overlay Measurements through Reduction of Tool and Wafer Induced Shifts”, Metrology, Inspection, and Process Control for Microlithography Proceedings, SPIE 3050, 1997.
5. Flack, W. et. al., “Verification of Back-to-Front Side Alignment for Advanced Packaging”, Ninth Interna- tional Wafer-Level Packaging Conference, Santa Clara, CA, November. 2012.
6. Flack, W. et.al., “Overlay Performance of Through Si Via Last Lithography for 3D Packaging”, 18th Electronics Packaging Technology Conference, Singapore, December 2016
7. Slabbekoorn, J. et. al, “Bosch Process Characterization For Donut TSV’s” Eleventh International Wafer-Level Packaging Conference, Santa Clara, CA, November 2014.

Micron Technology, Inc. (Nasdaq: MU) today added a new cost-efficient solid-state drive (SSD) to its client computing portfolio. The Micron 1300 SSD makes flash storage accessible to more users, enabling its adoption in a broader set of personal computing devices for a better mobile computing experience. Consumers who are eager to move from rotating media to solid state drives value fast performance, quick startup, and reliability — whether for desktop, mobile or workstation PCs. SSDs address these needs better than power-hungry hard disk drives (HDDs), yet their higher prices have kept users from shifting to SSDs. Micron redesigned the 1300 SSD series to close the price gap.

“The deployment of advanced 3D NAND technologies has led the client SSD market to branch into value and higher-performance storage segments,” said Gregory Wong, president of Forward Insights. “Micron’s latest client SSD solutions provide a coherent migration path from HDD to value-oriented SSDs.”

The new Micron 1300 SATA SSD is one of the industry’s first 96-layer triple-level cell (TLC) 3D NAND-based SSDs, available in capacities up to 1TB (in M.2) and 2TB (in 2.5-inch). This product introduction extends Micron’s leadership in high-density SSD design and high-volume manufacturing of performance 3D NAND-based flash drives. The ability to build drives with very small footprints like the M.2 SSD form factor, which is as small as a stick of gum, also hinges on Micron’s leadership in 3D NAND technology.

“We are driving innovation to deliver on the personal computing needs of users who want thinner, lighter and less power-hungry devices,” said Roger Peene, vice president of product planning and strategy for Micron’s Storage Business Unit. “Expanding our broad SSD portfolio with high-density 96-layer NAND storage delivers greater performance, form factors and efficiency at lower cost to meet the demanding needs of today’s mobile workers.”

The Micron 1300 SSD enhances storage performance for mobile, desktop and workstation PCs with 2.7x higher read throughput over HDDs.* It delivers sequential reads/writes up to 530MB/520MB per second and random reads/writes up to 90,000/87,000 input/output operations per second (IOPS).

In addition, the Micron 1300 SSD, designed to be power efficient, extends battery life between charges for the mobile worker. It uses 75 milliwatts (mW) of power, which is only 45 percent of the active (read/write) power of an average HDD.** The Micron 1300 SSD also supports Microsoft® Windows® 10 Modern Standby requirements including adaptive thermal management and near-instant transmission to low-power mode for increased productivity. The SSD also offers important features to protect valuable data such as asynchronous power-loss protection for data at rest and optional Opal 2.0 self-encryption.

The Micron 1300 SSD is an extension of the popular Micron 1100 SATA client SSD. Continuing the widely adopted SATA connectivity, Micron’s 1300 SSD series offers compelling price-to-value ratios at a range of capacities.

GOWIN Semiconductor Corp., an innovator of programmable logic devices, announces the release of GOWIN’s new EDA tool, YunYuan 1.9. With the release of this new toolchain, GOWIN will enable enhanced features and performance capabilities on their current and future FPGA product families.

EDA toolchains are becoming increasingly complex as FPGA applications are integrating more functions for the cloud and endpoint markets. To enable this complexity change, the new toolchain will include Gowin Synthesis, an enhanced front end logic synthesis tool designed and developed by the GOWIN EDA software team. It’s a significant milestone for GOWIN as the total toolchain is now completely designed in-house, allowing for quick quality improvements as well as product updates for customers time to market requirements. While GOWIN’s FPGA’s will be more optimized for IP, performance, and utilization using the new Yun Yuan 1.9 toolchain, the toolchain will additionally support the current Synopsys Synplify Pro synthesis tool already integrated.

“The development of the new synthesis tool is a major step for GOWIN,” said Alan Liu, Director of Software Development, GOWIN Semiconductor. “We can now make tool adjustments in real-time, enhancing the user experience.”

GOWIN EDA (YunYuan®) is an easy-to-use integrated design environment, providing design engineers with a one-stop solution. The complete GUI based environment covers FPGA design entry, code synthesis, place & route, bitstream generation, download, and online debugging of GOWIN FPGA’s on customer’s boards. The new toolchain also incorporates the following updated IP blocks:


  • CAN2.0 & CAN-FD IP
  • High-Speed MIPI Interface (1:8 & 1:16 Gear Box)
  • Ethernet 10/100/1000Mhz MAC Controller & Interface to MII/RMII/GMII

Memory Controller:

  • pSRAM Controller IP


  • Configurable RISC-V (5-Stage-Pipeline) CPU & System IP


  • FIR
  • NLMS Filter
  • FDAF – Frequency Domain Adaptive Filter
  • Cross-Correlation

Synopsys, Inc. (Nasdaq:SNPS) and GLOBALFOUNDRIES (GF) today announced a collaboration to develop a portfolio of automotive Grade 1 temperature (-40C to +150C junction) DesignWare® Foundation, Analog, and Interface IP for the GF 22-nm Fully-Depleted Silicon-On-Insulator (22FDX®) process. By providing IP that is designed for high temperature operation on 22FDX, Synopsys enables designers to reduce their design effort and accelerate AEC-Q100 qualification of system-on-chips (SoCs) for automotive applications such as eMobility, 5G connectivity, advanced driver assistance systems (ADAS), and infotainment. The Synopsys DesignWare IP implements additional automotive design rules for the GF 22FDX process to meet stringent reliability and operation requirements. This latest collaboration complements Synopsys’ broad portfolio of automotive-grade IP that provides ISO 26262 ASIL B Ready or ASIL D Ready certification, AEC-Q100 testing, and quality management.

“Arbe’s ultra-high-resolution radar is leveraging this cutting edge technology that enabled us to create a unique radar solution and provide the missing link for autonomous vehicles and safe driver assistance,” said Avi Bauer, vice president of R&D at Arbe. “We need to work with leading companies who can support our technology innovation. GF’s 22FDX technology, with Synopsys automotive-grade DesignWare IP, will help us meet automotive reliability and operation requirements and is critical to our success.”

“GF’s close, collaborative relationships with leading automotive suppliers and ecosystem partners such as Synopsys have enabled advanced process technology solutions for a broad range of driving system applications,” said Mark Ireland, vice president of ecosystem partnerships at GF. “The combination of our 22FDX process with Synopsys’ DesignWare IP enables our mutual customers to speed the development and certification of their automotive SoCs, while meeting their performance, power, and area targets.”

“Synopsys’ extensive investment in developing automotive-qualified IP for advanced processes, such as GF’s 22FDX, helps designers accelerate their SoC-level qualifications for functional safety, reliability, and automotive quality,” said John Koeter, vice president of marketing for IP at Synopsys. “Our close collaboration with GF mitigates risks for designers integrating DesignWare Foundation, Analog, and Interface IP into low-power, high-performance automotive SoCs on the 22FDX process.”

GLOBALFOUNDRIES & Synopsys at Mobile World Congress 2019

On February 25, 2019, Synopsys will join the GLOBALFOUNDRIES NEXTech Lab Theater Session at MWC19. A panel discussion, with leading industry experts, ​​including Joachim Kunkel, general manager of the Solutions Group at Synopsys, and Mike Cadigan, senior vice president of global sales, business development, customer and design engineering at GF, will offer insights about the importance of intelligent connectivity, the growth, demands, and innovations it is poised to bring, and its impacts across the semiconductor value chain. For more information, visit: https://www.globalfoundries.com/join-gf-mwc19.


For more information on Synopsys DesignWare IP for automotive Grade 1 temperature operation on GF’s 22FDX process:

Researchers at CEA-Leti and Stanford University have developed the world’s first circuit integrating multiple-bit non-volatile memory (NVM) technology called Resistive RAM (RRAM) with silicon computing units, as well as new memory resiliency features that provide 2.3-times the capacity of existing RRAM. Target applications include energy-efficient, smart-sensor nodes to support artificial intelligence on the Internet of Things, or “edge AI”.

The proof-of-concept chip has been validated for a wide variety of applications (machine learning, control, security). Designed by a Stanford team led by Professors Subhasish Mitra and H.-S. Philip Wong and realized in CEA-Leti’s cleanroom in Grenoble, France, the chip monolithically integrates two heterogeneous technologies: 18 kilobytes (KB) of on-chip RRAM on top of commercial 130nm silicon CMOS with a 16-bit general-purpose microcontroller core with 8KB of SRAM.

The new chip delivers 10-times better energy efficiency (at similar speed) versus standard embedded FLASH, thanks to its low operation energy, as well as ultra-fast and energy-efficient transitions from on mode to off mode and vice versa. To save energy, smart-sensor nodes must turn themselves off. Non-volatility, which enables memories to retain data when power is off, is thus becoming an essential on-chip memory characteristic for edge nodes. The design of 2.3 bits/cell RRAM enables higher memory density (NVM dense integration) yielding better application results: 2.3x better neural network inference accuracy, for example, compared to a 1-bit/cell equivalent memory.

The technology was presented on Feb. 19, at the International Solid-State Circuits Conference (ISSCC) 2019 in San Francisco in a paper titled, “A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques”.

But NVM technologies (RRAM and others) suffer from write failures. Such write failures have catastrophic impact at the application level and significantly diminish the usefulness of NVM such as RRAM. The CEA-Leti and Stanford team created a new technique called ENDURER that overcomes this major challenge. This gives the chip a 10-year functional lifetime when continuously running inference with the Modified National Institute of Standards and Technology (MNIST) database, for example.

“The Stanford/CEA-Leti team demonstrated a complete chip that stores multiple bits per on-chip RRAM cell. Stored information is correctly processed when compared with previous demonstrations using standalone RRAM or a few cells in a RAM array,” said Thomas Ernst, Leti’s chief scientist for silicon components and technologies. “This multi-bit storage improves the accuracy of neural network inference, a vital component of AI.”

Mitra said the chip demonstrates several industry firsts for RRAM technology. These include new algorithms that achieve multiple bits-per-cell RRAM at the full memory level, new techniques that exploit RRAM features as well as application characteristics to demonstrate the effectiveness of multiple bits-per-cell RRAM at the computing system level, and new resilience techniques that achieve a useful lifetime for RRAM-based computing systems.

“This is only possible with a unique team with end-to-end expertise across technology, circuits, architecture, and applications,” he said. “The Stanford SystemX Alliance and the Carnot Chair of Excellence in NanoSystems at CEA-Leti enabled such a unique collaboration.”

GLOBALFOUNDRIES (GF) and Dolphin Integration, a provider of semiconductor IP, today announced a collaboration to develop a series of adaptive body bias (ABB) solutions to improve the energy efficiency and reliability of system-on-chip (SoC) on GF’s 22nm FD-SOI (22FDX) process technology for a wide range of high-growth applications such as 5G, IoT and automotive.

As part of the collaboration, Dolphin Integration and GF are working together to develop a series of off-the-shelf ABB solutions for accelerating and easing body bias implementation on SoC designs. ABB is a unique 22FDX feature that enables designers to leverage forward and reverse body bias techniques to dynamically compensate for process, supply voltage, temperature (PVT) variations and aging effects to achieve additional performance, power, area and cost improvements beyond those from scaling alone.

The ABB solutions in development consist of self-contained IPs embedding the body bias voltage regulation, PVT and aging monitors and control loop as well as complete design methodologies to fully leverage the benefits of corner tightening. GF’s 22FDX technology offers the industry’s lowest static and dynamic power consumption. With automated transistor body biasing adjustment, Dolphin Integration can achieve up to 7x energy efficiency with power supply as low as 0.4V on 22FDX designs.

“We have been working with GF for more than two years on advanced and configurable power management IPs for low power and energy efficient applications,” said Philippe Berger, CEO at Dolphin Integration. “Through our ongoing collaboration with GF, we are focused on creating turnkey IP solutions that allow designers to realize the full benefit of FD-SOI for any SoC design in 22FDX.”

“In order to simplify our client designs and shorten their time-to-market, GF and our ecosystem partners are helping to pave the way to future performance standards in 5G, IoT and automotive,” said Mark Ireland, vice president of Ecosystem at GF. “With the support of silicon IP providers like Dolphin Integration, new power, performance and reliability design infrastructures will be available to customers to fully leverage the benefits of GF’s 22FDX technology.”

Design kits with turnkey adaptive body bias solutions on GF’s 22FDX will be available starting in Q2 2019.

The inaugural SEMI 3D & Systems Summit opens today as the industry gathers for the latest insights and trends in 3D integration and systems for semiconductor manufacturing and applications. The 28-30 January summit in Dresden, Germany, highlights the future of intelligent systems powered by artificial intelligence (AI). To register, click here.

SEMI 3D & Systems Summit features a broad scope of topics aimed at driving business opportunities and innovation in areas including:

  • 3DIC Through-Silicon-Via (TSV) technology
  • 2.5D, 3D FO-WLP/e-WLB
  • Active and passive interposers
  • Stacked dies or stacked wafers
  • 3D alternative technologies
  • 5G Integration


Professor Hubert Lakner, director, Fraunhofer-Institute for Photonic Microsystems IPMS, will kick off the summit with his keynote Heterointegration – The Path to Future Complex Intelligent Systems. Lakner will explore connected intelligence opportunities arising from the transition to autonomous driving, the digitalization and electrification of cars, and the digitalization of industry and electrical power grids. These capabilities will be enabled by AI, improved cybersecurity, reinforced connectivity through 5G, edge computing, low-power components, sensors and power management.

Steffen Kroehnert, senior director, Technology Development, Amkor Technology Inc. will discuss advances in heterogeneous integration. The current wave of technology innovation in the semiconductor industry is largely driven by AI, deep learning, cloud computing and Internet of Things (IoT), with each of these leading-edge technologies sharing a common need: high-speed signaling with ultra-low latency/power and real time computational formulations. These capabilities require fully integrated functionality at the source, better known as the edge.

3D & System Summit Speakers

3D & Systems Summit speakers include experts from industry leaders such as Orbotech, GLOBALFOUNDRIES, Fraunhofer-Institute for Photonic Microsystems IPMS, EPIC – European Photonics Industry Consortium, McKinsey, System Plus Consulting, ASE Group, imec, DISCO HI-TEC EUROPE, STMicroelectronics, G-ray, Amkor, TU Dresden, Huawei, Fraunhofer IZM, AT&S AG, Deca Technologies and Miland.

Exhibitors Include Leaders in 3D Integration Microelectronics

The exhibition will showcase the most prominent names in 3D integration microelectronics manufacturing including ASE Group, Amkor Technology, Canon, Confovis, DISCO, FineTech, Fraunhofer IZM, FRT Metrology, Imec, LPKF, Optim Wafer Services, SPTS andXPERI. See the floorplan here.

3D & Systems Summit attendees are also invited to join the Symposium Panel Level Packaging 2019, organized by Fraunhofer IZM, 30 January, 14:00-18:00. Registration for the event is open. More details on the symposium are available here.

By Serena Brischetto

SEMI met with Martin Schrems, director of Strategy and Business Development at AT&S AG, to discuss Fan-Out technology trends ahead of SEMI 3D & Systems Summitin Dresden, Germany.

SEMI: What are the AT&S AG mission and vision and your role within the company?

Schrems: AT&S AG is evolving from a pure PCB manufacturer towards an interconnect solution provider. We can clearly see a continued trend towards miniaturization and modularization by (3D) integration of components such as integrated circuits and passives. Module sizes tend to increase by integrating more functions and system-level requirements. As a PCB maker, we have served such system-level requirements for a long time. Further integration offers opportunities to embed components in PCBs or substrates, offer layout and simulation services, as well as provide assembly and test services depending on specific customer requirements. As director of Strategy and Business Development, I work with my colleagues in AT&S, customers, and partners across the industry towards understanding and leveraging this major transformation in the electronics industry.

SEMI: What project are you currently working on that you think will make a difference in 2019?

Schrems: There are number of very exciting projects, many of them already involving AT&S contributions to module integration. Some of these projects involve key customers directly. We see exciting opportunities for integration of larger multi-function modules by combining PCB, substrate, and embedding core competences.

SEMI: The focus of your presentation at the 3D & Systems Summit will be on “Fan-Out System-in-Board technology enabling module and system-level integration.” What do you see as the key trend in this area?

Schrems: Fan-Out technologies are used to distribute I/O pad connections of nanoCMOS ICs over a larger area. This relaxes bump pitch and feature size requirements for subsequent system-level PCB interconnects. In some cases, Fan-Out layers already provide a substitute to currently used Flip-Chip substrates. Well-known examples are Fan-Out packages for application processors for smartphones. There is definitely a trend in the market towards Fan-Out for high-end processor applications. Advantages of such Fan-Out packages are shorter electrical connections and a reduced thickness.

However, one weakness of current Fan-Out packages is that only a limited number of components can be integrated due to mechanical stability challenges – a barrier to further component integration in larger modules. Currently, the only way to integrate more components is to use laminate-based PCBs and substrates with conventional Surface Mount Technology. Recent proposals like our “Fan-Out System-in-Board” (FO-SiBTM) technology are expected to provide an alternative Fan-Out packaging option at the board-level in the future.

SEMI: Please elaborate.

Schrems: Fan-Out capability and integration of more components – typically up to the 100 and more needed for electronics integration at system level – can be achieved simultaneously by combining technologies from the PCB and the packaging world. PCB laminates such as glass particles and organic materials provide mechanical stability for large boards. The recent introduction of substrate-like PCBs (mSAP) has already paved the way to cover applications that were reserved for substrates and classical packaging in the past.

With FO-SiBTM technology, we have taken it a step further and offer the option to integrate SAP substrate layers onto the PCB with lines/spaces below 10µm. FO-SiBTM makes it possible to directly contact nanoCMOS chips on PCBs without any intermediate substrates. Further adding Cu pillar technology at panel level will enable Fan-Out structures even for surface-mounted components, making recent R&D on panel-level Cu pillar technology very important. Through joint R&D, we can drive progress in the industry to further enable cost-effective heterogeneous 3D integration.

SEMI: What are your expectations for the 3D & Systems Summit in Dresden, and why do you recommend your members and other industry leaders to attend?

Schrems: The 3D summit is the high-level conference where key electronics industry players discuss major heterogeneous integration trends. Therefore, we very much appreciate the opportunities to exchange ideas across the supply chain including users, developers of integrated electronics hardware and tool manufacturers.

Serena Brischetto is a marketing and communications manager at SEMI Europe.

Laser systems specialist LPKF Laser & Electronics, based in Hannover, Germany has added a foundry service for thin glass substrates to its product portfolio. The company recently introduced the Laser-Induced Deep Etching technology, or LIDE for short, a process for the precise and highly efficient manufacturing of through-glass vias (TGV) and other deep micro features in thin glass substrates. The LIDE process is able to overcome past limitations in glass drilling and micro machining as it combines very high productivity and low manufacturing cost with the superior quality of a direct data process, forgoing masks or photo processing.

With the introduction of its new independent foundry service, LPKF is hoping to make the LIDE technology available on a much wider scale, covering both prototyping and experimental applications as well as scalable mass production capacity. The service is aimed at the manufacturing of glass substrates for advanced IC and MEMS packaging as well as micro-machining of spacer wafers,microfluidics and other specialty glass applications. LPKF’s new foundry service is located at its corporate headquarters and will operate under the company’s Vitrion brand name.

Established in 1976, LPKF Laser & Electronics manufactures laser systems used in circuit board prototyping, microelectronics fabrication, solar panel scribers, laser plastic welding systems and recently added a foundry service for thin glass substrates used in electronics packaging. LPKF’sworldwide headquarters is located in Hannover, Germany and its North American headquarters resides in Portland, OR.

ZEISS today unveiled a new suite of high-resolution 3D X-ray imaging solutions for failure analysis (FA) of advanced semiconductor packages, including 2.5/3D and fan-out wafer-level packages. The new ZEISS systems include the Xradia 600-series Versa and Xradia 800 Ultra X-ray microscopes (XRM) for submicron and nanoscale package FA, respectively, as well as the new Xradia Context microCT. With the addition of these new systems to its existing family of products, ZEISS now provides the broadest portfolio of 3D X-ray imaging technologies serving the semiconductor industry.

“Throughout its 170-year history, ZEISS has pushed the frontiers of scientific research and advanced the start-of-the-art in imaging technologies to enable new industrial applications and technological innovations,” stated Dr. Raj Jammy, president, ZEISS Process Control Solutions (PCS) and Carl Zeiss SMT, Inc. “Now more than ever in the semiconductor industry, where package as well as device features are shrinking in all three dimensions, new imaging solutions are needed to quickly isolate failures in order to enable higher package yields. We are extremely pleased to announce this trio of new 3D X-ray imaging solutions for advanced semiconductor packaging, which provides our customers with a powerful high-resolution toolset to improve their failure analysis success rates.”

Advanced Packaging Requires New Defect Detection and Failure Analysis Methods
As the semiconductor industry approaches the limits of CMOS scaling, semiconductor packaging needs to help bridge the performance gap. To continue producing ever-smaller and faster devices with lower power requirements, the semiconductor industry is turning to package innovation through 3D stacking of chips and other novel packaging formats. This drives increasingly complex package architectures and new manufacturing challenges, along with increased risk of package failures. Furthermore, since the physical location of failures is often buried within these complex 3D structures, conventional methods for visualizing failure locations are becoming less effective. New techniques are required to efficiently isolate and determine the root cause of failures in these advanced packages.

To address these needs, ZEISS has developed a new suite of 3D X-ray imaging solutions that provides submicron and nanoscale 3D images of features and defects buried within intact structures in advanced package 3D architectures. This is enabled by rotating a sample and capturing a series of 2D X-ray images from different perspectives, followed by reconstruction of 3D volumes using sophisticated mathematical models and algorithms. An unlimited number of virtual cross-sections of the 3D volume may be viewed from any angle – providing valuable insight of failure locations prior to physical failure analysis (PFA). The combination of submicron and nanoscale XRM solutions from ZEISS provides a unique FA workflow that can significantly enhance FA success rates. ZEISS’s new Xradia Context microCT offers high contrast and resolution in a large field of view, using projection-based geometric magnification, and is fully upgradable to Xradia Versa.

New Imaging Solutions in Detail
Xradia 600-series Versa is the next generation of 3D XRM for non-destructive imaging of localized defects within intact advanced semiconductor packages. It excels in structural and FA applications for process development, yield improvement and construction analysis. Based on the award-winning Versa platform with Resolution at a Distance (RaaD) capability, Xradia 600-series Versa offers unsurpassed performance for high-resolution imaging of larger samples at long working distances to determine root causes of defects and failures in packages, circuit boards and 300 mm wafers. It can easily visualize defects associated with package-level failures, such as cracks in bumps or microbumps, solder wetting problems or through silicon via (TSV) voids. The 3D visualization of defects prior to PFA reduces artifacts and guides cross-section orientations, leading to improved FA success rates. Features include:

  • 0.5 micron spatial resolution, 40 nm min voxel size
  • Up to 2x higher throughput than Xradia 500-series Versa, achieved while maintaining high resolution with excellent source spot-size stability and thermal management control across the full kV and power range
  • Improved ease of use, including fast-activation source control
  • Ability to observe submicron structural changes within a package successively imaged at multiple reliability test read points

Xradia 800 Ultra brings 3D XRM to the nanoscale realm, producing images of buried features with nanoscale spatial resolution while preserving the volume integrity of the region of interest. Applications include process analysis, construction analysis and defect analysis of ultra-fine-pitch flip chip and bump connections – enabling process improvement for ultra-fine-pitch package and back-end-of-line (BEOL) interconnects. Xradia 800 Ultra enables visualization of the texture and volume of solder consumed by intermetallic compounds in fine-pitch copper pillar microbumps. Defect sites are preserved during imaging, enabling targeted follow-up analysis by a variety of techniques. The construction quality of blind assemblies, such as wafer-to-wafer bonded interconnect and direct hybrid bonding, can be characterized in 3D. Features include:

  • 150 nm and 50 nm spatial resolution (sample preparation is required)
  • Optional pico-second laser sample prep tool, enabling extraction of an intact volume sample (typically 100 microns in diameter) in under one hour
  • Compatibility with a wide range of options for follow-on analysis, including transmission electronic microscopy (TEM), energy dispersive X-ray spectroscopy (EDS), atomic force microscopy (AFM), secondary ion mass spectroscopy (SIMS) and nanoprobing