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Micron Technology, Inc. (Nasdaq:MU) today launched the Micron 5200 series of SATA solid state drives (SSDs), maintaining performance, consistency, capacity, reliability, and overall infrastructure value. Built on Micron’s new 64-layer 3D NAND technology, the Micron 5200 series of SSDs offers a cost-optimized SATA platform for business-critical virtualized workloads that cripple on a hard drive, such as OLTP, BI/DSS, VDI, block/object and media streaming.

Leveraging the proven architecture, performance and capacity of the well-regarded 5100 SATA SSDs, the Micron 5200 series is engineered to deliver a fast, easy and cost-effective enterprise storage solution to replace existing hard drives and legacy SSDs. Micron 5200 SSDs immediately deliver better total cost of ownership and improve data center efficiency through server and storage platform consolidation, reducing IT costs and simplifying infrastructure and maintenance. Now it is easier than ever before for enterprises to add more flash into the data center and get more out of server deployments.

As the first SATA enterprise SSD available with 64-layer 3D NAND technology, the Micron 5200 SSDs deliver improved densities, throughput, consistency, and power efficiency — all at a better value. The quality of an SSD depends on the NAND it’s built on, and the Micron 5200 series of SSDs is engineered to deliver improved reliability with the industry’s lowest annualized drive failure rate for SATA enterprise SSDs according to data sheet specifications, offering better value with Micron’s known silicon-to-system quality advantage.

“Micron 5200 SSDs unleash market-leading performance, capacity and reliability, paired with a rich feature set and unprecedented flexibility, adding up to the ideal storage solution for business-critical workloads,” said Micron Storage Business Unite Vice President and General Derek Dicker. “We simplified the server qualification process by leveraging the same foundational architecture that’s currently available on Micron SATA SSDs. Customers can trust the same proven controller and firmware design while taking advantage of advanced flash media for better performance, quality of service, and value.”

“Today’s business-critical, virtualized workloads simply cannot run at peak, consistent performance on yesterday’s technology,” said Dedicated Computing Senior Vice President Sales and Marketing Dave Guzzi. “Customers need advanced storage technology to achieve better performance and reliability — and a lower total cost of ownership. Fortunately, Micron offers all this along with the ease of a common platform that leverages the same proven controller and firmware design as previous SSD generations.”

“It says a lot that Micron chose to release its next-generation SSD based on the architecture of its prior generation while only changing the NAND from 32-layer to 64-layer technology,” said Jim Handy of Objective Analysis. “This shows that the company and its customers are pleased with the performance and reliability of the earlier 5100 series and are open to migrating to a new flash technology in a way that minimizes requalification costs.”

Join the SOLID Storage Revolution

Built on Micron’s industry-leading 64-layer 3D NAND technology for enterprise SATA SSDs, the Micron 5200 series of SSDs accelerates applications that need faster, more consistent performance, while offering overall infrastructure value and quality of service (QoS) at an improved total cost of ownership. Optimized for latency-sensitive, read-intensive workloads, these new SATA SSDs minimize storage bottlenecks with faster, predictable performance, making the move from hard drives to SSDs easier than ever before. Key features include:

  • Quality of Service — The Micron 5200 SSDs deliver extremely efficient QoS, offering up to 99.7 percent better QoS when compared to a mission-critical hard disk drive.1
  • Unmatched Capacity — Micron 5200 SSDs offer the industry’s broadest SATA portfolio with capacities up to 7.68TB, twice the capacity of other SSDs on the market.
  • Leading Performance — Engineered for fast random IO performance that fuels virtualized applications, Micron 5200 SSDs deliver up to 95k IOPS random reads and best-in-class 33,000 random writes, delivering strong performance in both areas. The drive is also highly flexible, as data center managers can use the innovative Flex Capacity feature to adjust the drive’s endurance, performance, and capacity to meet ever-changing workload demands.
  • Leader in MTTF Offering — Micron 5200 SSD data sheet specifications offer a mean time to failure (MTTF) of 3 million device hours, compared to the industry average for SATA enterprise SSD specifications of 2 million hours MTTF.
  • Easy to Manage — A fast, easy, affordable way to extend the life of existing server deployments, Micron 5200 SSDs are hot-swappable, easy to install, and only take minutes to configure, saving both time and money on setup and maintenance.

The Micron 5200 series of SSDs offers varying levels of performance and endurance to meet the diverse needs of low-latency, read-intensive workloads. Visit the Micron 5200 series SSD product flyer for additional information on the feature and function advantages. Micron 5200 SSDs are designed to replace 10K RPM hard drives and help IT managers deliver better performance and capacity – all while using less power. As an example, in an OLTP workload environment, a single Micron SSD allows you to get 3X more IOPS performance than an entire rack of 24 10K RPM hard drives.

  • 5200 ECO SATA SSD — Scale storage with fast, vast, built-to-last SSDs. Scale data center capabilities easily and efficiently. With capacities up to 7.68TB in a 2.5″ form factor, the Micron 5200 ECO SSD meets and surpasses the capacity per unit of rack space and cost advantages that had been previously owned by HDDs. Specially designed for read-intensive workloads, the Micron 5200 ECO SSD provides cloud services and content sharing companies a reliable, easy-to-deploy SATA storage solution that works within existing infrastructure deployment models to deliver radically faster performance than an HDD − and a significantly better value.
  • 5200 PRO SATA SSD — An all-purpose drive to power read-intensive workload demands. Micron 5200 PRO SSDs are an all-purpose drive to power read-intensive workloads that require higher random write performance and endurance. The Micron 5200 PRO is quick to respond and deliver on the unforecasted demand of today’s application workloads, including burst-driven transaction waves or sudden high volume web traffic. For IT administrators needing to ensure fast data throughput to keep their business running smoothly at all times, the Micron 5200 PRO SSD is a known storage workhorse and is engineered to deliver consistently fast, leading performance.

Micron 5200 SSDs are available now for OEM qualification and for purchase through distributors, such as ASI, Avnet, CDW, Ingram, Microland, WPG-Americas, Synnex and others.

Everspin Technologies, Inc. (NASDAQ:MRAM), a developer and manufacturer of discrete and embedded MRAM, today announced the Company recorded revenue for its first 40nm 256Mb STT-MRAM products in the fourth quarter of 2017 and is in the process of ramping its volume production in 2018. This achievement represents an important milestone for STT-MRAM as it is the enabling step for bringing the persistent memory to market.

STT-MRAM is a significant advancement in magnetoresistive random access memory (MRAM) as the densities of this persistent memory technology open up new market opportunities beyond where MRAM has been deployed previously. While there are several companies committed to the MRAM market today, Everspin has the advantage of being the first to reach a volume production for STT-MRAM as well as the only company that is executing on both discrete and embedded MRAM (eMRAM) solutions. The 256Mb STT-MRAM also employs an innovative ST-DDR3 interface, unlocking performance previously unattainable in legacy MRAM components.

“Our 256Mb STT-MRAM is the first ever perpendicular MTJ STT-MRAM entering mass production. This is both a testament to the technical strength of Everspin’s team in design and technology as well as the joint productization strength provided by the collaboration with GLOBALFOUNDRIES,” said Kevin Conley, President and CEO of Everspin Technologies. “This is a bellwether milestone in the evolution of this disruptive technology and we are very excited about the advantages that the capacity and performance of this product brings to our customers.”

“GLOBALFOUNDRIES is excited to see the first STT-MRAM from the Everspin partnership reaching production. The movement of discrete STT-MRAM to volume production is an important milestone on the way to enabling our risk production release of 22FDX eMRAM for GLOBALFOUNDRIES’ customers later this year,” said Dave Eggleston, Vice President of Embedded Memory, GLOBALFOUNDRIES.

Kevin Conley, President and CEO, and Jeff Winzeler, CFO, will present tomorrow at Needham & Company’s 20th Annual Growth Conference from 12:50 – 1:30PM EST at the Lotte New York Palace Hotel. Management will be available to meet with investors at the conference. Copies of any presentation materials will be made available on www.Everspin.com.

Intel today announced the availability of the Intel Stratix 10 MX FPGA, the industry’s first field programmable gate array (FPGA) with integrated High Bandwidth Memory DRAM (HBM2). By integrating the FPGA and the HBM2, Intel Stratix 10 MX FPGAs offer up to 10 times the memory bandwidth when compared with standalone DDR memory solutions. These bandwidth capabilities make Intel Stratix 10 MX FPGAs the essential multi-function accelerators for high-performance computing (HPC), data centers, network functions virtualization (NFV), and broadcast applications that require hardware accelerators to speed-up mass data movements and stream data pipeline frameworks.

In HPC environments, the ability to compress and decompress data before or after mass data movements is paramount. HBM2-based FPGAs can compress and accelerate larger data movements compared with stand-alone FPGAs. With High Performance Data Analytics (HPDA) environments, streaming data pipeline frameworks like Apache Kafka and Apache Spark Streaming require real-time hardware acceleration. Intel Stratix 10 MX FPGAs can simultaneously read/write data and encrypt/decrypt data in real-time without burdening the host CPU resources.

“To efficiently accelerate these workloads, memory bandwidth needs to keep pace with the explosion in data,” said Reynette Au, vice president of marketing, Intel Programmable Solutions Group. “We designed the Intel Stratix 10 MX family to provide a new class of FPGA-based multi-function data accelerators for HPC and HPDA markets.”

The Intel Stratix 10 MX FPGA family provides a maximum memory bandwidth of 512 gigabytes per second with the integrated HBM2. HBM2 vertically stacks DRAM layers using silicon via (TSV) technology. These DRAM layers sit on a base layer that connects to the FPGA using high density micro bumps. The Intel Stratix 10 MX FPGA family utilizes Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) that speeds communication between FPGA fabric and the DRAM. EMIB works to efficiently integrate HBM2 with a high-performance monolithic FPGA fabric, solving the memory bandwidth bottleneck in a power-efficient manner.

Intel is shipping several Intel Stratix 10 FPGA family variants, including the Intel Stratix 10 GX FPGAs (with 28G transceivers) and the Intel Stratix 10 SX FPGAs (with embedded quad-core ARM processor). The Intel Stratix 10 FPGA family utilizes Intel’s 14 nm FinFET manufacturing process and incorporates packaging technology, including EMIB.

 

IXYS Corporation (NASDAQ:IXYS), a global manufacturer of power semiconductors and integrated circuits (ICs) for energy efficiency, power management, transportation, medical, and motor control applications, today announced a new power semiconductor product line: 200V Ultra-Junction X3-Class HiPerFET Power MOSFETs. The current ratings range from 36A to 300A; a broad selection of devices are available in a number of international standard packages.

Fabricated using a charge compensation principle and IXYS’ own process technology, these new MOSFETs exhibit the lowest on-state resistances in the industry (3.5 milliohms in the SOT-227 package and 4 milliohms in the TO-264, for example). Along with gate charges as low as 21 nanocoulombs, these devices enable highest power densities and energy efficiencies in a wide variety of high-speed power conversion applications.

The fast body diodes of the devices are optimized and have low reverse recovery charge and time, thereby suppressing transients and enabling low-noise, high-efficiency power switching. Their low reverse recovery charge and time also boost efficiencies. In addition, these new MOSFETs are avalanche capable and exhibit a superior dv/dt performance (up to 20V/ns).

Targeted applications include synchronous rectification, battery chargers for light electric vehicles (LEVs), motor control (48V-110V systems), DC-DC converters, uninterruptible power supplies, electric forklifts, inverters, power solid state relays, and Class-D audio amplifiers.

The new 200V X3-Class Power MOSFETs with HiPerFET body diodes are available in the following international standard size packages: TO-3P, TO-220 (overmolded or standard), TO-247, PLUS247, TO-252, TO-263, TO-264, TO-268HV, SOT-227. Some example part numbers include IXFP36N20X3, IXFA72N20X3, IXFH90N20X3 and IXFN300N20X3, with current ratings of 36A, 72A, 90A and 300A, respectively.

Additional product information can be obtained by visiting the IXYS website at http://www.ixys.com or by contacting the company directly.

SUNY Polytechnic Institute (SUNY Poly) Professor of Nanoengineering Bin Yu has been named a Fellow of the National Academy of Inventors (NAI), the organization announced Tuesday. Election to NAI Fellow status is one of the highest professional accolades bestowed solely to academic inventors who have demonstrated a prolific spirit of innovation in creating or facilitating outstanding inventions that have made a tangible impact on quality of life, economic development, and the welfare of society.

“I am proud to congratulate Dr. Yu on his selection as Fellow of the NAI, which is a strong reflection of his research that has helped to advance cutting-edge nanotechnologies,” said SUNY Poly Interim President Dr. Bahgat Sammakia. “Dr. Yu’s numerous patents and continued SUNY Poly-based research in exciting areas such as nanomaterials and advanced nano-devices continues to hold promise for further developments that can enhance energy efficiency and boost computing speeds to improve the technologies that our society relies on each day.”

Those elected to the rank of NAI Fellow are named inventors on U.S. patents and were nominated by their peers for outstanding contributions to innovation, as well as for patents and licensing, innovative discovery and technology, and providing significant impact on society.

Dr. Yu has a number of significant accomplishments in the areas of nano electronic devices, nano-based sensors, nano-based energy harvesting, emerging data storage devices, next-generation interconnects, and smart nano-manufacturing, including work as the lead researcher for the world’s first 10 nm gate-length 3D transistor FinFET (IEEE-IEDM’2002), and for the world’s first THz silicon logic switch (IEEE-IEDM’2001).

Dr. Yu is the recipient of multiple awards and honors, including the NASA Innovation Award and IBM Faculty Award, and was ranked #3 by the National Science Foundation for Supported Investigators with Most Patents in 2011; as an inventor, he holds more than 300 awarded U.S. patents.

“I am honored that I have been selected to become a National Academy of Inventors Fellow, a powerful recognition of the work undertaken at SUNY Poly which can help to advance technology based on a wide variety of applied nanostrucutures,” said Dr. Yu. “I congratulate my fellow inductees and appreciate the acknowledgement of the importance of these research contributions that have led to more than 300 U.S. patents. I look forward to continuing to pursue efforts utilizing SUNY Poly’s state-of-the-art resources and capabilities for research related to nano-inspired technologies targeted for the next-generation of computing, sensing, and energy generation, as well as research related to emerging nanomaterials for smart nanomanufacturing.”

Dr. Yu has published books and book chapters on topics ranging from graphene-based electronics to 2D layered semiconductor-based emerging solar photovoltaics. He has also served as Editor of IEEE Electron Device Letters from 2001-2007, Associate Editor of IEEE Transactions on Nanotechnology from 2007-2010, and is currently an Editorial Board Member for Nano-Micro Letters and an Editorial Advisory Board Member for Nanoelectronics and Spintronics, among other leadership positions. Dr. Yu has been invited as a speaker to more than 100 highlight/invited talks, seminars, and tutorials to international conferences, universities, industry national labs, and professional societies. He is also an Institute of Electrical and Electronics Engineers (IEEE) Fellow and IEEE Electronic Device Society Distinguished Lecturer. More information about Dr. Yu’s background can be found here.

With the election of the 2017 class there are now 912 NAI Fellows, representing over 250 research universities and governmental and non-profit research institutes. The 2017 Fellows are named inventors on nearly 6,000 issued U.S. patents, bringing the collective patents held by all NAI Fellows to more than 32,000 issued U.S. patents.

Included among all NAI Fellows are more than 100 presidents and senior leaders of research universities and non-profit research institutes; 439 members of the National Academies of Sciences, Engineering, and Medicine; 36 inductees of the National Inventors Hall of Fame; 52 recipients of the U.S. National Medal of Technology and Innovation and U.S. National Medal of Science; 29 Nobel Laureates; 261 AAAS Fellows; 168 IEEE Fellows; and 142 Fellows of the American Academy of Arts & Sciences, among other awards and distinctions.

In April 2018 the 2017 NAI Fellows will be inducted as part of the Seventh Annual NAI Conference of the National Academy of Inventors at the Mayflower Hotel, Autograph Collection in Washington, D.C., and Andrew H. Hirshfeld, U.S. Commissioner for Patents, will provide the keynote address for the induction ceremony.

The 2017 class of NAI Fellows was evaluated by the 2017 Selection Committee, which included 18 members comprising NAI Fellows, U.S. National Medals recipients, National Inventors Hall of Fame inductees, members of the National Academies of Sciences, Engineering, and Medicine and senior officials from the USPTO, National Institute of Standards and Technology, Association of American Universities, American Association for the Advancement of Science, Association of Public and Land-grant Universities, Association of University Technology Managers, and National Inventors Hall of Fame, among other organizations.

Leti, a research institute of CEA Tech, today announced it has created the world’s first microfluidic circuit for cooling a particle detector, perhaps paving the way to a revolutionary, new detector technique at the Large Hadron Collider. This world-first event has been developed for CERN, the European nuclear research organization.

This breakthrough cooling system is part of CERN’s NA62 Gigatracker (GTK), a silicon pixel detector used to measure the arrival time and the position of incoming beam particles in the world’s largest particle accelerator. The NA62 detector is designed to study the “very rare” decay of kaons, subatomic particles made of quarks. Understanding these decays will help physicists check some of the predictions that the Standard Model of particle physics makes about short-distance interactions. Specifically, NA62 will measure the rate at which the charged kaon decays into a charged pion and a neutrino-antineutrino pair.

The Standard Model of particle physics explains how the basic building blocks of matter interact, governed by four fundamental forces in nature: gravity, electromagnetism and the strong and weak nuclear forces.

“The very rare decay of Kaons is sensitive to contributions coming from new particles and therefore represents a powerful way of searching for new physics,” said Augusto Ceccucci, NA62 spokesperson. “This technique complements the direct approach of the LHC detectors, and is a key component in CERN’s programs to probe the ultimate constituents of matter and understand the laws of nature.”

The NA62 is comprised of a set of three innovative silicon pixel detectors, whose job is to measure the arrival time and the position of the incoming beam particles. Installed in the heart of the NA62 detector, the silicon sensors are cooled down to approximately minus-20 degrees Celsius by a microfluidic silicon device developed by Leti and CERN researchers. The cooling system is required to remove the heat produced by the readout chips the silicon sensor is bonded to. The NA62 Gigatracker has a cooling plate on top of which both the silicon sensor and the readout chip are bonded.

In 2012, after CERN chose Leti to supply the microfluidic devices, CERN provided an initial fabrication process-flow that Leti’s Silicon Specialty Solutions (Leti-3S) program implemented in its own flow with its expertise in silicon processing, strictly following CERN’s technical specifications.

Leti-3S scientists demonstrated for the first time in the field of high-energy physics (HEP) the possibility of using silicon microfluidic devices for thermal management of silicon pixel detectors and their read-out electronics in LHC experiments.

Leti’s work included using deep silicon plasma-etching processes for microchannel production, its expertise at bonding silicon wafers at microscopic levels, and further grinding and thinning. In addition, Leti built titanium-nickel-gold contacts to connect the coolers to the NA62 device.

“The challenge was above all that we had only two pieces per wafers because of their large dimensions, meaning that two defects could result in a zero-percent yield,” said Catherine Charrier, project leader at Leti. “Maintaining the quality of the coolers on the centimeter dimensions, while respecting micrometric specifications, was a real challenge that we were able to overcome.”

Since being selected by CERN to work on NA62, Leti has contributed to the development of several types of cooling devices.

“Producing these silicon coolers provides us the opportunity to contribute to the scientific communities that use large instruments, which will expand Leti’s scope of operation,” Charrier said.

Leti, a research institute of CEA Tech, demonstrated significant improvements in the field of memory systems at IEDM 2017 this week.

These include reconfiguring Static Random-Access Memory (SRAM) into Content-Addressable Memory (CAM), improving non-volatile crossbar memories and using advanced Tunnel Field-Effect Transistors (TFET). Another breakthrough presents a high-density SRAM bitcell on Leti’s CoolCubeTM 3D platform, which reduces the area required for memory by 30 percent, while maintaining full device functionality. This breakthrough points the way to easing the major memory bottleneck in more complex systems on chip (SoC), where up to 90 percent of the SoC area might be taken by SRAM.

The breakthroughs were reported Dec. 5 at IEDM 2017 in a paper titled “Advanced Memory Solutions for Emerging Circuits and Systems.”

A key obstacle to shrinking SRAM on SoCs is bitcell-area limitations linked to required performance and yield, both of which become more challenging as technology scales. Lowering system power consumption is also limited by memory, as the SRAM performance and its stability scale less successfully than logic performance at lower voltages. Other memories like CAM might be affected even more by voltage scaling.

“All of these obstacles become particularly important for the Internet of Things, where ultralow-power consumption and the cost of individual nodes are crucial, and SRAM limitations have a big impact on both,” said Bastien Giraud, one of the paper authors.

Leti approached these challenges with a CoolCubeTM SRAM design focusing on the development of a compact and functional four-transistor bitcell, along with other innovations:

  • Reconfiguring memory between the CAM and SRAM, depending on the application
  • Optimizing memory using TFET, focusing on the exploitation of its negative differential-resistance effect to build ultralow-power SRAM, Flip Flops (FF) and refresh-free Dynamic Random Access Memory (DRAM)
  • A new compensation technique for crosspoint memory that reduces the voltage drop and leads to larger memory arrays.

Leti said its proposed CAM/SRAM outperforms memories, with operations at 1.56GHz and 0.13fJ/bit energy per search. In addition, the proposed TFET designs are competitive in terms of area, performance and static power consumption. Leti’s proposed compensation technique in crosspoint memory also enables the design of cost-efficient large memory arrays, while reducing the impact of temporal and spatial variations.

Short-term applications include crossbar circuits for storage-class memory and flexible SOCs with SRAM/CAM re-configurability.

“In the longer term, Leti’s CoolCubeTM technology will be able to deliver very high-density SRAM,” Giraud said. “Enabling TFET-based DRAM and integrating TFET standard cells into CMOS designs will allow circuit designers to take advantage of the best features of both technologies.”

By Inna Skvortsova, SEMI

Electromagnetic interference (EMI) is an increasingly important topic across the global electronics manufacturing supply chain.  Progressively smaller geometries of ICs, lower supply voltages, and higher data rates all make devices and processes more vulnerable to EMI. Electrical noise, EMI-induced signal generated by equipment, and factors such as power line transients affect manufacturing processes, from wafer handling to wire bonding to PCB assembly and test, causing millions of dollars in losses to the industry. Furthermore, conducted emission capable of causing electrical overstress (EOS) can damage sensitive semiconductor devices.  Intel consistently names EOS as the “number one source of damage to IC components.” (Intel® Manufacturing Enabling Guide 2001, 2010, 2016).

While EMC (Electromagnetic Compatibility) standards, such as the European EMC Directive and FCC Testing and Certification, etc. provide limits on allowed emission levels of equipment, once the equipment is installed along with other tools, the EMI levels in actual operating environments can be substantially different and therefore impact the equipment operation, performance, and reliability. For example, (i) Occasional transients induce “extra” pulses in rotary feedback of the servo motor which in time contributes to robotic arm’s erroneous position eventually damaging the wafer; (ii) Combination of high-frequency noise from servo motors and switched mode power supplies in the tool creates difference in voltage between the bonding wire/funnel and the device which causes high current and eventual electrical overstress to the devices; (iii) Wafer probe test provides inconsistent results due to high level of EMI on the wafer chuck caused by a combination of several servo motors in the wafer handler.  Field cases like these illustrate the gap between EMC test requirements and real-life EMI tolerance levels and its impact on semiconductor manufacturing and handling.

EMI on AC power lines

EMI on AC power lines

New standard, SEMI E176-1017, Guide to Assess and Minimize Electromagnetic Interference (EMI) in a Semiconductor Manufacturing Environment, developed by the NA Chapter of the Global Metrics Technical Committee bridges this gap. Targeted to IC manufacturers and anyone handling semiconductor devices, such as PCB assembly and integration of electronic devices, SEMI E176 is a practical guide as well as an educational document. SEMI E176 provides a concise summary of EMI origins, EMI propagation, measurement techniques and recommendations on mitigation of undesirable electromagnetic emission to enable equipment co-existence and proper operation as well as reduction of EOS in its intended usage environment. Specifically, E176 provides recommended levels for different types of EMI based on IC geometries.

“SEMI E176 is likely the only active Standard in the entire industry providing recommendations on both acceptable levels of EMI in manufacturing environments and the means of achieving and maintaining these numbers,” said Vladimir Kraz, co-Chair of the NA Metrics Technical Committee and president of OnFILTER, Inc. “E176 is also unique because it is not limited just to semiconductor manufacturing, but has application across other industries.  Back-end assembly and test, as well as PCB assembly are just as affected by EMI and can benefit from SEMI E176 implementation as there are strong similarities between handling of semiconductor devices in IC manufacturing and in PCB assemblies and prevention of defects is often shared between IC and PCBA manufacturers.”

The newly published SEMI E176 and recently updated SEMI E33-0217, Guide for Semiconductor Manufacturing Equipment Electromagnetic Compatibility (EMC),provide complete documentation for establishing and maintaining low EMI levels in the manufacturing environment.

Undesirable emission has operational, liability and regulatory consequences.  Taming it is a challenging task and requires a comprehensive approach that starts from proper system design practices and ends with developing EMI expertise in the field.  The new SEMI 176 provides practical guidance on reducing EMI to the levels necessary for effective high yield semiconductor manufacturing today and in the future.

SEMI Standards development activities take place throughout the year in all major manufacturing regions. To get involved, join the SEMI International Standards Program at: www.semi.org/standardsmembership.

 

Quantenna Communications, Inc. (Nasdaq:QTNA), a developer of high performance Wi-Fi solutions, today announced that Dr. Nambi Seshadri, Quantenna’s chief technologist has been selected as the 2018 IEEE Alexander Graham Bell Medal recipient for exceptional contributions to wireless, networking and engineering. In addition to this highest honor, Seshadri’s prize consists of a gold medal, a bronze replica, a certificate, and an honorarium.

“The innovations by Nambi form the basis for some of today’s Wi-Fi and other wireless networking standards and systems, now in use by billions of Wi-Fi users,” said Dr. Sam Heidari, Chairman and Chief Executive Officer, Quantenna. “We are honored to have such a distinguished and accomplished chief technologist on our team. The process is extraordinarily competitive, this is a great lifetime accomplishment and one of the most prestigious honors that one may receive in our field.”

Every year, the IEEE board of directors selects a SINGLE individual to receive the IEEE Alexander Graham Bell Medal. The selection criteria used include weighing the value of the individual’s contribution to communication among people as well as to communication sciences and engineering, and an evaluation of the contributor, nominator and references. The timeliness of the recognition, and quality of the nomination also are considered.

The IEEE Alexander Graham Bell Medal was established in 1976 by the IEEE Board of Directors, in commemoration of the centennial of the telephone’s invention, to provide recognition for outstanding contributions to telecommunications. The invention of the telephone by Alexander Graham Bell in 1876 was a major event in electrotechnology. It was instrumental in stimulating the broad telecommunications industry that has dramatically improved life throughout the world. As an individual, Bell himself exemplified the contributions that scientists and engineers have made to the betterment of mankind.

In addition to serving as chief technologist to Quantenna, Seshadri is a Professor of Electrical and Computer Engineering (ECE) for the University of California, San Diego. Prior to Quantenna, Seshadri held multiple senior positions at Broadcom Corporation where he helped Broadcom’s wireless initiatives, including it’s foray into cellular, mobile multimedia, low power wireless connectivity, GPS and others. During 2011-2014, he also served as the General Manager of the Mobile Platforms Business Unit. Prior to joining Broadcom Corporation, he was a Member of Technical Staff at with AT&T Bell Lab Laboratories and Head of Communications Research at AT&T Shannon Labs where he contributed to fundamental advances in wireless communication theory and practice.

Seshadri was elected Fellow of the Institute of Electrical and Electronic Engineers (IEEE) in 2000 and was elected to the National Academy of Engineering (USA) in 2012 and as a Foreign Member of the Indian National Academy of Engineering in the year 2013. He holds approximately 200 patents. He was a co-recipient of the IEEE Information Theory Paper Award in 1999 for his paper with Tarokh and Calderbank on space-time codes, and his IEEE Journal on Selected Areas In Communications (JSAC) paper on space-time coding modems with Naguib, Tarokh, and Calderbank was selected by IEEE Communication Society for publication in, “The Best of the Best: Fifty Years of Communications and Networking Research,” for 2003.

A research group in Japan announced that it has quantified for the first time the impacts of three electron-scattering mechanisms for determining the resistance of silicon carbide (SiC) power semiconductor devices in power semiconductor modules. The university-industry team consisting of researchers from the University of Tokyo and Mitsubishi Electric Corporation has found that resistance under the SiC interface can be reduced by two-thirds by suppressing electron scattering by the charges, a discovery that is expected to help reduce energy consumption in electric power equipment by lowering the resistance of SiC power semiconductors.

Electron scattering under the silicon carbide (SiC) interface is limited by three factors: roughness of the SiC interface, charges under the SiC interface and atomic vibration. Credit: 2017 Mitsubishi Electric Corporation.

Electron scattering under the silicon carbide (SiC) interface is limited by three factors: roughness of the SiC interface, charges under the SiC interface and atomic vibration. Credit: 2017 Mitsubishi Electric Corporation.

Electric power equipment used in home electronics, industrial machinery, trains and other apparatuses requires a combination of maximized efficiency and minimized size. Mitsubishi Electric, a leading Japanese electronics and electrical equipment manufacturer, is accelerating use of SiC devices for power semiconductor modules, which are key components in electric power equipment. SiC power devices offer lower resistance than conventional silicon power devices, so to further lower their resistance it is important to understand correctly the characteristics of the resistance under the SiC interface.

“Until now, however, it had been difficult to measure separately resistance-limiting factors that determine electron scattering,” says Satoshi Yamakawa, senior manager of the SiC Device Development Center at Mitsubishi Electric’s Advanced Technology R&D Center.

Electron scattering focusing on atomic vibration was measured using technology from the University of Tokyo. The impact that charges and atomic vibration have on electron scattering under the SiC interface was revealed to be dominant in Mitsubishi Electric’s analyses of fabricated devices. Although it has been recognized that electron scattering under the SiC interface is limited by three factors, namely, the roughness of the SiC interface, the charges under the SiC interface and the atomic vibration, the contribution of each factor had been unclear. A planar-type SiC metal-oxide-semiconductor field-effect transistor (SiC-MOSFET), in which electrons conduct away from the SiC interface to around several nanometers, was fabricated to confirm the impact of the charges.

“We were able to confirm at an unprecedented level that the roughness of the SiC interface has little effect while charges under the SiC interface and atomic vibration are dominant factors,” says Koji Kita, an associate professor at the University of Tokyo’s Graduate School of Engineering and one of scientists leading the research.

Using an earlier planar-type SiC-MOSFET device for comparison, resistance was reduced by two-thirds owing to suppression of electron scattering, which was achieved by making the electrons conduct away from the charges under the SiC interface. The previous planar-type device has the same interface structure as that of the SiC-MOSFET fabricated by the electronics maker.

For the test, Mitsubishi Electric handled the design, fabrication and analysis of the resistance-limiting factors and the University of Tokyo handled the measurement of electron-scattering factors.

“Going forward, we will continue refining the design and specifications of our SiC MOSFET to further lower the resistance of SiC power devices,” says Mitsubishi Electric’s Yamakawa.

This research achievement was announced at the 63rd International Electron Devices Meeting (IEDM) in San Francisco, California, on December 4, 2017.