Tag Archives: letter-ap-tech

Semiconductor test equipment supplier Advantest Corporation (TSE:6857) has developed the M4171 handler to meet the mobile electronics market’s needs for cost-efficient thermal control testing of ICs with high power dissipation during device characterization and pre-production bring up.  This portable, single-site handler automates device loading and unloading, thermal conditioning and binning in engineering labs, where most testing today involves manual device handling. It also features an active thermal control (ATC) capability typically available only on larger footprint, more costly production-volume handlers.

The M4171 can be used to remotely conduct device handling and thermal control from anywhere around the world through a network connection.  In addition to requiring fewer operators and lowering labor costs, this handler maximizes system utilization among working groups in different locations.

The combination of automated device handling, wide-temperature ATC capabilities from -45° C to 125° C and remote operation make the M4171 unique.  It can run multi-mode test processes (Single Insertion Multiple Temperature), automated testing, automatic ID testing, output tray re-testing and manual testing, both pre-defined and user defined.

The Tri Temp Technology on the M4171 enables the users to operate over a broad range of temperatures which greatly increases any lab’s efficiency.  The system uses direct device-surface contact, which enables quick temperature switching for fast ramp up and ramp down and improves cycle temperature testing by over 40 percent compared to manual thermal-control solutions.

The M4171 handler is compatible with the V93000 and T2000 platforms as well as other testers.  Other features include a 2D code reader, a device rotator and a high contact force option.  Operation is simple with an intuitive, easy-to-use GUI that includes pre-defined functions.

“By bringing cost-efficient automated testing into the lab and enabling our customers to get higher utilization from their installed base, we are providing substantial productivity advantages,” said Toshio Goto, executive officer and manager of the Device Handling business unit at Advantest.  “As our first single-site ATC handler, the M4171 is opening new market opportunities for us in device characterization within labs and benchtop environments.”

 

Crosstalk and noise can become a major source of reliability problems of CNT based VLSI interconnects in the near future. Downscaling of component size in integrated circuits (ICs) to nanometer scale coupled with high density integration makes it challenging for researchers to maintain signal integrity in ICs. There are high chances of occurrence of crosstalk between adjacent wires. This crosstalk in turn, will increase the peak noise in the transient signals that pass through the interconnects. As multiple occurrences of crosstalk happen, the noise propagates through multiple stages of wires and the problem worsens to logic failure.

But thanks to semiconducting CNTs, which till now have found applications in the fabrication of futuristic field effect transistors, when placed around an interconnect, can reduce crosstalk to a large extent. Basically, semiconducting CNTs are non-conducting, have small dielectric constant, medium to large band gaps and hence can act as insulating shields to electric fields.

As semiconducting CNTs are one dimensional nanowires, they have very high anisotropic properties along their axis as well as their radius. The dielectric polarizability, which is the measure of number of polarizable bonds in a material, is found to be very smaller along the CNT radius compared to its axis. So, semiconducting CNTs are less polarizable along their radius which further suggests that they have small dielectric constants. The famous Clausius-Mossotti relation can be used to derive the dielectric constant from the dielectric polarizability. Further, this relation also tells that the dielectric constant of a CNT increases with its radius. So, obviously small diameter semiconducting CNTs are the ideal candidates as the low-k dielectric medium between two CNT interconnects.

The contact geometry is modified in such a way that more metal atoms are present at the centre where metallic CNTs are present. The contact has lesser number of metal atoms at the periphery where semiconducting CNTs are present. This helps in building a Schottky barrier at the contact semiconducting CNT interface and hence, inhibits any carrier movement.

Finally, experimental results show that the radial dielectric constant can be as low as 2.82 if (2,2) CNTs are used as shields. The coupling capacitance between adjacent wires is dependent on the interconnect thickness as well as the semiconducting CNT shield thickness. Crosstalk between CNT wires can be reduced by 28% if semiconducting CNTs are used. The crosstalk induced peak noise was also found to be 25% lesser for semiconducting CNT shielded interconnects at different input voltages of 0.8V, 0.5V and 0.3V.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, and Leti, an institute of CEA Tech, today announced the world’s first successful 300-mm wafer-to-wafer direct hybrid bonding with pitch dimension connections as small as 1µm (micron). This breakthrough also achieved copper pads as small as 500nm.

The copper/oxide hybrid bonding process, a key enabler for 3D high-density IC applications, was demonstrated in Leti’s cleanrooms using EVG’s fully automated GEMINI FB XT fusion wafer bonding system. This result was obtained in the framework of the program IRT Nanoelec headed by Leti. EVG joined the institute’s 3D Integration Consortium in February 2016.

Wafer bonding an enabling process for 3D device stacking

Vertical stacking of semiconductor devices has become an increasingly viable approach to enabling continuous improvements in device density and performance. Wafer-to-wafer bonding is an essential process step to enable 3D stacked devices. However, tight alignment and overlay accuracy between the wafers is required to achieve good electrical contact between the interconnected device on the bonded wafers, as well as to minimize the interconnect area at the bond interface so that more space can be made available on the wafer for producing devices. The constant reduction in pitches that are needed to support component roadmaps is fueling tighter wafer-to-wafer bonding specifications with each new product generation.

Demonstration results

In the Leti demonstration, the top and bottom 300mm wafers were directly bonded in the GEMINI FB XT automated production fusion bonding system, which incorporates EVG’s proprietary SmartView NT face-to-face aligner and an alignment verification module to enable in-situ post-bond IR alignment measurement. The system achieved overlay alignment accuracy to within 195nm (3-sigma) overall, with mean alignment results well centered below 15nm. Post-bake acoustic microscopy scans of the full 300mm bonded wafer stack as well as specific dies confirmed a defect-free bonding interface for pitches ranging from 1µm to 4µm with optimum copper density.

Focused Ion Beam Scanning Electron Microscope (FIB-SEM) cross-section of 1-µm pitch copper pads on a pair of 300-mm wafers bonded with the GEMINI®FB XT automated production fusion bonding system from EV Group. Photo courtesy of Leti.

Focused Ion Beam Scanning Electron Microscope (FIB-SEM) cross-section of 1-µm pitch copper pads on a pair of 300-mm wafers bonded with the GEMINI®FB XT automated production fusion bonding system from EV Group. Photo courtesy of Leti.

“To our knowledge, this is the first reported demonstration of sub-1.5µm pitch copper hybrid bonding feasibility,” said Frank Fournel, head of bonding process engineering at Leti. “This latest demonstration represents a real breakthrough and important step forward in enabling the achievement and eventual commercialization of high-density 3D chip stacking.”

This demonstration is summarized in a paper co-authored by Leti, titled “1 µm Pitch Direct Hybrid Bonding with with <300nm Wafer-to-wafer Overlay Accuracy,” which was presented at the 2017 IEEE S3S Conference.

“3D integration holds the promise for increased device density and bandwidth as well as lower power consumption for a variety of applications, from next-generation CMOS image sensors and MEMS to high-performance computing,” stated Markus Wimplinger, corporate technology development and IP director at EV Group. “As a leader in 3D integration research and development, Leti has been at the forefront in moving this critical technology toward industry adoption and commercialization. EVG shares that vision, and we are pleased to have played a role in supporting Leti’s latest achievement in 3D integration.”

Leveraging EVG’s high-throughput XT Frame platform and an equipment front-end module (EFEM), the GEMINI FB XT automated production fusion bonding system is optimized for ultra-high throughput and productivity. The SmartView NT aligner integrated into the system provides industry-leading wafer-to-wafer overlay alignment accuracy (sub-200nm, 3-sigma). In addition, the GEMINI FB XT can accommodate up to six pre- and post-processing modules for surface preparation, conditioning and metrology steps such as wafer cleaning, plasma activation alignment verification, debonding (allowing pre-bonded wafers to be separated automatically and re-processed if necessary) and thermo-compression bonding.

EVG will showcase the GEMINI FB XT at the SEMICON Europa exhibition being held November 14-17 at the Messe München in Munich, Germany. Attendees interested in learning more about the product, as well as EVG’s full suite of wafer bonding and lithography solutions, are invited to visit the company’s booth #B1-1424.

Alpha and Omega Semiconductor Limited (AOS) (Nasdaq:AOSL) a designer, developer and global supplier of a broad range of power semiconductors and power ICs, today announced the release of AONS66916 production utilizing the latest Alpha Shield Gate Technology Generation 2 (AlphaSGT2). The AONS66916 has RDS(ON) * Qg  (FOM) and more robust capability for a greater safety margin. In synchronous rectification, it is essential to optimize the reverse recovery charge and reduce the voltage overshoot. These attributes enable higher efficiency and robustness to critical high density telecom and server applications.

The AlphaSGT2 provides ~30% lower RDS(ON) compared to AlphaSGT1 and is designed to be more robust with significant avalanche energy improvement. AlphaSGT2 technology reduces both conduction and switching losses. Thus, with AlphaSGT2 technology, circuit designers can prevent paralleling devices for lower turn-on resistance, enabling higher power density in power supply applications.

“The new AlphaSGT2 100V technology is designed for critical applications such as Telecom and Datacom power supplies where power density, high efficiency, and robustness is essential,” said Peter H. Wilson, Director of Product Marketing at AOS.

Technical Highlights

Part Number VDS (V) VGS (V) RDS(ON)MAX (mOhms) Qg (typ) (nC) ID @ TA = 25°C (A)
@ 10V
AONS66916 100 ±20 3.6 67 100

The AONS66916 is immediately available in production quantities with a lead-time of 15 weeks. The unit price of 1,000 pieces is $ 1.2.

Alpha and Omega Semiconductor Limited, or AOS, is a designer, developer and global supplier of a broad range of power semiconductors, including a wide portfolio of Power MOSFET, IGBT, IPM and Power IC products.

Enabling the A.I. era


November 8, 2017

BY PETE SINGER, Editor-in-Chief

There’s a strongly held belief now that the way in which semiconductors will be designed and manufactured in the future will be largely determined by a variety of rapidly growing applications, including artificial intelligence/deep learning, virtual and augmented reality, 5G, automotive, the IoT and many other uses, such as bioelectronics and drones.

The key question for most semiconductor manufacturers is how can they benefit from these trends? One of the goals of a recent panel assembled by Applied Materials for an investor day in New York was to answer that question.

The panel, focused on “enabling the A.I. era,” was moderated by Sundeep Bajikar (former Sellside Analyst, ASIC Design Engineer). The panelists were: Christos Georgiopoulos (former Intel VP, professor), Matt Johnson (SVP in Automotive at NXP), Jay Kerley (CIO of Applied Materials), Mukesh Khare (VP of IBM Research) and Praful Krishna (CEO of Coseer). The panel discussion included three debates: the first one was “Data: Use or Discard”; the second was “Cloud versus Edge”; and the third was “Logic versus Memory.”

“There’s a consensus view that there will be an explosion of data generation across multiple new categories of devices,” said Bajikar, noting that the most important one is the self-driving car. NXP’s Johnson responded that “when it comes to data generation, automotive is seeing amazing growth.” He noted the megatrends in this space: the autonomy, connectivity, the driver experience, and electrification of the vehicle. “These are changing automotive in huge ways. But if you look underneath that, AI is tied to all of these,” he said.

He said that estimates of data generation by the hour are somewhere from 25 gigabytes per hour on the low end, up to 250 gigabytes or more per hour on the high end. or even more in some estimates.

“It’s going to be, by the second, the largest data generator that we’ve seen ever, and it’s really going to have a huge impact on all of us.”

Intel’s Georgiopoulos agrees that there’s an enormous amount of infrastructure that’s getting built right now. “That infrastructure is consisting of both the ability to generate the data, but also the ability to process the data both on the edge as well as on the cloud,” he said. The good news is that sorting that data may be getting a little easier. “One of the more important things over the last four or five years has been the quality of the data that’s getting generated, which diminishes the need for extreme algorithmic development,” he said. “The better data we get, the more reasonable the AI neural networks can be and the simpler the AI networks can be for us to extract information that we need and turn the data information into dollars.” Check out our website at www.solid-state.com for a full report on the panel.

The technologies to watch identified by TechInsights analysts at the beginning of the year have not been disappointing.

BY STACY WEGNER, Ottawa, Canada, and JEONGDONG CHOE, Ottawa, Canada

TechInsights analysts have been keeping an intent watch on where technology has progressed, how it’s changing, and what new developments are emerging. At the end of the first quarter, our analysts shared their insights and thoughts about what to keep an eye on as the year unfolds. In this article, they provide an update on what 2017 has delivered so far.

Intelligent, connected devices

As we wrote earlier this year, in 2016, wearables were extremely interesting mainly because there was so much uncertainty around whether or not the market would be viable. Some, no, many, say the wearables market will cool off and possibly just expire. At TechInsights, we do will not speculate about whether this market is going to survive. We will report what we find and analyze what is currently being sold. Apple, Samsung, and Huawei have all released smartwatches for what would parallel a “flagship” in the mobile market (FIGURE 1). Fitness bands are becoming even ”smarter” and combining sensors where possible. Perhaps one of the most notable developments is Nokia’s acquisition and complete integration of Withings into its existing brands.

Screen Shot 2017-11-07 at 12.24.01 PM

We are witnessing the “rise of the machines,” in products from scales and hair brushes to rice cookers. Primarily these devices offer consumers convenience. For example, with a connected scale, instead of recording your weight manually, the smart scales do the job for you, syncing with various health apps so you can track your weight over time. The connected hair brush provides insights into your hair’s manageability, frizziness, dryness, split ends and breakage to provide a hair quality score. Brushing patterns, pressure applied and brush stroke counts are analyzed to measure effectiveness of brushing habits and a personal diagnosis is provided with tips and real-time product recommendations. The most common connected devices include refrigerators, lights, washing machines, thermostats, and televisions.

One dominant example is the ever-popular Amazon Echo, which has taken on a life of its own and is generating spin-off markets and competition. In July, it was reported that Amazon’s Alexa voice platform passed 15,000 skills — the voice-powered apps that run on devices like the Echo speaker, Echo Dot, newer Echo Show and others. The figure is up from the 10,000 skills Amazon officially announced in February. Amazon’s Alexa is building out an entire voice app ecosystem putting it much further ahead than its nearest competitor. The success seen with Echo has motivated other companies like Google, Lenovo, LG, Samsung and Apple to release compet- itive speakers, however it is estimated that Amazon is expected to control 70 percent of the market this year. In addition, Amazon and Microsoft recently announced a partnership to better integrate their digital assistants. This cross-platform integration provides users with access to Cortana features that Alexa is missing, and vice versa. Finally, the high- performance far-field microphones found in Amazon Echo products may soon find their way to other hardware companies as Amazon announced that the technology is available to those who want to integrate into the Alexa Experience. With its new reference solution, it’s never been easier for device makers to integrate Alexa and offer their customers the same voice experiences.

In the mobile market overall, we are seeing a strong emergence of devices targeted for the very hot market of India. The mobile devices for this market range from supporting 15 or more cellular bands to as few as five cellular bands, and that is for smart- phones. At TechInsights, we will be analyzing OEMs in India like Micromax, Intex, and Lava to see how they approach dealing with strong competitors like Samsung and Xiaomi.

Memory devices

In early 2017, 32L and 48L 3D NAND products were common and all the NAND players were eager to develop next generation 3D NAND products such as 64L and 128L. 3D NAND has been jumping into 64L (FIGURE 2). Samsung, Western Digital, Toshiba, Intel, and Micron already revealed CS or mass-products on the market. SK Hynix also showed their 72L NAND die as a CS product. In the second half of this year, we will see 64L and 72L NAND products on the commercial market. For n+1 generation with 96L or 128L, we expect that two-stacked cell array architecture for 3D NAND would be adopted in 2018. Micron/Intel will keep their own FG based 3D NAND cell structure for the next generation.

Screen Shot 2017-11-07 at 12.24.10 PM

Referring to DRAM, all the major players already used their advanced process technology for cell array integration such as an advanced ALD for high-k dielectrics, low damage plasma etching and honeycomb capacitor structure. Buried WL, landing pad and plug for a capacitor node, and MESH structure are still main stream. Samsung 18nm DRAM products for DDR4 and LPDDR4X are on the market. SK Hynix and Micron will reveal the same tech node DRAM products in this year. n+1 gener- ation with 15nm or 16nm node will be next in 2018. Once 6F2 15nm DRAM cell technology is successful, 4F2 DRAM products such as a capacitorless DRAM might be delayed. In 2018, 18nm and 15nm DRAM technology will be used for GDDR6 and LPDDR5.

When it comes to emerging memory, 3D XPoint memory technology is a hot potato (FIGURE 3). The XPoint products from Intel are on the market as an Optane SSD with 16GB and 32GB. Performance including retention, reliability and speed are not matched as expected, but they used a double stacked memory cell between M4 and M5 on the memory array. It’s a PCM with GST based material. An OTS with Se-As-Ge-Si is added between the PCM and the electrode (WL or BL). We expect to see multiple (triple or quadruple) stacked XPoint memory architecture within a couple years. For other emerging memory such as STT-MRAM, PCRAM and ReRAM, we’re waiting on some commercial products from Adesto (CBRAM 45nm, RM33 series) and Everspin (STT-MRAM pMTJ 256Mb, AUP-AXL-M128).

Screen Shot 2017-11-07 at 12.24.21 PM

Conclusion

The technologies to watch identified by TechInsights analysts at the beginning of the year have not been disappointing. As our analysts continue to examine and reveal the innovations others can’t inside advanced technology, we will continue to share our findings on these and new technologies as they emerge, including how they are used, how they impact the market, and how they will be changed by the next discovery or invention.

Samsung Electronics Co., Ltd. announced today that 8-nanometer (nm) FinFET process technology, 8LPP (Low Power Plus), has been qualified and is ready for production.

The newest process node, 8LPP provides up to 10-percent lower power consumption with up to 10-percent area reduction from 10LPP through narrower metal pitch. 8LPP will provide differentiated benefits for applications including mobile, cryptocurrency and network/server, and is expected to be the most attractive process node for many other high performance applications.

As the most advanced and competitive process node before EUV is employed at 7nm, 8LPP is expected to rapidly ramp-up to the level of stable yield by adopting the already proven 10nm process technology.

“With the qualification completed three months ahead of schedule, we have commenced 8LPP production,” said Ryan Lee, Vice President of Foundry Marketing at Samsung Electronics. “Samsung Foundry continues to expand its process portfolio in order to provide distinct competitive advantages and excellent manufacturability based on what our customers and the market require.”

“8LPP will have a fast ramp since it uses proven 10nm process technology while providing better performance and scalability than current 10nm-based products,” said RK Chunduru, Senior Vice President of Qualcomm.

Details of the recent update to Samsung’s foundry roadmap, including 8LPP availability and 7nm EUV development, will be presented at the Samsung Foundry Forum Europe on October 18, 2017, in Munich, Germany. The Samsung Foundry Forum was held in the United States, South Korea and Japan earlier this year, sharing Samsung’s cutting-edge process technologies with global customers and partners.

 

Leti, a research institute of CEA Tech, will hold a workshop on Oct. 17 to present updates on their progress developing CoolCube high-density 3D sequential, monolithic-integration technology, and their supporting design-and-manufacturing ecosystems.

The workshop at the Hyatt Regency San Francisco Airport, Burlingame, Calif., is an official satellite event of the 2017 IEEE S3S conference. It will feature presentations from Leti and Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated, as well as partner firms, such as Applied Materials, SCREEN Semiconductor and HP Enterprise. Workshop attendees will include representatives of a growing ecosystem of design, manufacturing, and related companies.

As an extension of High Density 3D Cu-Cu/Hybrid Bonding Chip-to-Wafer/Wafer-to-Wafer Technologies, the CoolCube  concept enables stacking active layers of transistors in the third dimension, while coping with thermal budgets that do not degrade the performance of transistors or metal interconnects. Leti and Qualcomm have been collaborating for four years on various 3DVLSI advanced concepts, which have broad applications in low-power mobile devices and other IC platforms.

Workshop topics will include:

  • a review of 3DVLSI research at Qualcomm Technologies
  • an update on Leti’s technology and design
  • a complete Leti 3D-technologies landscape presentation, and
  • exploration of expectations and challenges around 3DVLSI technology.

The workshop is designed to encourage an active exchange of ideas among attendees on applications, markets, integration and other related areas.

Leti will highlight technological solutions available now for top-tier CMOS integration using CoolCube:

  • high-quality mono-crystalline channel
  • high-performance source/drain contacts
  • high-reliability gate stack and
  • low-parasitic stable intermediate back-end-of-line on 300mm wafers.

Leti this year taped out a test vehicle based on its internal technology and CoolCube circuit and will publish final results of the test in 2018. In this CMOS integration, the technology starts from 28nm foundry wafers and extends to current Leti top-tier processes. During the Oct. 17 workshop, Leti will present the next step: a newCoolCube tape-out, scheduled for mid-2018 and open to partners and collaborators. It is targeted to demonstrate by hardware promising applications enabled by CoolCube/3DVLSI.  Design contributions are already planned or expected in the following fields: neuromorphic, near-memory processing, high-performance FPGA and energy-efficient computing.

“As CoolCube has evolved, its development team has received a growing number of inquiries from companies and organizations all along the semiconductor value chain, including materials and equipment suppliers, electronic design automation (EDA) companies, fabless chipmakers and foundries, and assembly and test houses,” said Jean-Eric Michallet, Leti Head of Microelectronics Components Department. “Mutual cooperation will be an essential element of successful integration into high-volume production, and representatives of companies in these sectors are encouraged to attend the workshop.”

 

A research collaboration between Osaka University and the Nara Institute of Science and Technology for the first time used scanning tunneling microscopy (STM) to create images of atomically flat side-surfaces of 3D silicon crystals. This work helps semiconductor manufacturers continue to innovate while producing smaller, faster, and more energy-efficient computer chips for computers and smartphones.

Spatial-derivative STM images with 200x200 nm^2 at Vs = +1.5 V. Flat terraces become brighter and edges darker. The downstairs direction runs from left ((110) top-surface) to right ((-1-10) back-surface). Credit: Osaka University

Spatial-derivative STM images with 200×200 nm^2 at Vs = +1.5 V. Flat terraces become brighter and edges darker. The downstairs direction runs from left ((110) top-surface) to right ((-1-10) back-surface). Credit: Osaka University

Our computers and smartphones each are loaded with millions of tiny transistors. The processing speed of these devices has increased dramatically over time as the number of transistors that can fit on a single computer chip continues to increase. Based on Moore’s Law, the number of transistors per chip will double about every 2 years, and in this area it seems to be holding up. To keep up this pace of rapid innovation, computer manufacturers are continually on the lookout for new methods to make each transistor ever smaller.

Current microprocessors are made by adding patterns of circuits to flat silicon wafers. A novel way to cram more transistors in the same space is to fabricate 3D-structures. Fin-type field effect transistors (FETs) are named as such because they have fin-like silicon structures that extend into the air, off the surface of the chip. However, this new method requires a silicon crystal with a perfectly flat top and side-surfaces, instead of just the top surface, as with current devices. Designing the next generation of chips will require new knowledge of the atomic structures of the side-surfaces.

Now, researchers at Osaka University and the Nara Institute of Science and Technology report that they have used STM to image the side-surface of a silicon crystal for the first time. STM is a powerful technique that allows the locations of the individual silicon atoms to be seen. By passing a sharp tip very close to the sample, electrons can jump across the gap and create an electrical current. The microscope monitored this current, and determined the location of the atoms in the sample.

“Our study is a big first step toward the atomically resolved evaluation of transistors designed to have 3D-shapes,” study coauthor Azusa Hattori says.

To make the side-surfaces as smooth as possible, the researchers first treated the crystals with a process called reactive ion etching. Coauthor Hidekazu Tanaka says, “Our ability to directly look at the side-surfaces using STM proves that we can make artificial 3D structures with near-perfect atomic surface ordering.”

Columbia Engineering researchers, led by Harish Krishnaswamy, associate professor of electrical engineering, in collaboration with Professor Andrea Alu’s group from UT-Austin, continue to break new ground in developing magnet-free non-reciprocal components in modern semiconductor processes. At the IEEE International Solid-State Circuits Conference in February, Krishnaswamy’s group unveiled a new device: the first magnet-free non-reciprocal circulator on a silicon chip that operates at millimeter-wave frequencies (frequencies near and above 30GHz). Following up on this work, in a paper (DOI 10.1038/s41467-017-00798-9) published today in Nature Communications, the team demonstrated the physical principles behind the new device.

Most devices are reciprocal: signals travel in the same manner in forward and reverse directions. Nonreciprocal devices, such as circulators, on the other hand, allow forward and reverse signals to traverse different paths and therefore be separated. Traditionally, nonreciprocal devices have been built from special magnetic materials that make them bulky, expensive, and not suitable for consumer wireless electronics.

The team has developed a new way to enable nonreciprocal transmission of waves: using carefully synchronized high-speed transistor switches that route forward and reverse waves differently. In effect, it is similar to two trains approaching each other at super-high speeds that are detoured at the last moment so that they do not collide.

The key advance of this new approach is that it enables circulators to be built in conventional semiconductor chips and operate at millimeter-wave frequencies, enabling full-duplex or two-way wireless. Virtually all electronic devices currently operate in half-duplex mode at lower radio-frequencies (below 6GHz), and consequently, we are rapidly running out of bandwidth. Full-duplex communications, in which a transmitter and a receiver of a transceiver operate simultaneously on the same frequency channel, enables doubling of data capacity within existing bandwidth. Going to the higher mm-wave frequencies, 30GHz and above, opens up new bandwidth that is not currently in use.

“This gives us a lot more real estate,” notes Krishnaswamy, whose Columbia High-Speed and Mm-wave IC (CoSMIC) Lab has been working on silicon radio chips for full duplex communications for several years. His method enables loss-free, compact, and extremely broadband non-reciprocal behavior, theoretically from DC to daylight, that can be used to build a wide range of non-reciprocal components such as isolators, gyrators, and circulators.

“This mm-wave circulator enables mm-wave wireless full-duplex communications, Krishnaswamy adds, “and this could revolutionize emerging 5G cellular networks, wireless links for virtual reality, and automotive radar.”

The implications are enormous. Self-driving cars, for instance, require low-cost fully-integrated millimeter-wave radars. These radars inherently need to be full-duplex, and would work alongside ultra-sound and camera-based sensors in self-driving cars because they can work in all weather conditions and during both night and day. The Columbia Engineering circulator could also be used to build millimeter-wave full-duplex wireless links for VR headsets, which currently rely on a wired connection or tether to the computing device.

“For a smooth wireless VR experience, a huge amount of data has to be sent back and forth between the computer and the headset requiring low-latency bi-directional communication,” says Krishnaswamy. “A mm-wave full-duplex transceiver enabled by our CMOS circulator could be a promising solution as it has the potential to deliver high speed data with low latency, in a small size with low cost.”

The team, funded by sources including the National Science Foundation EFRI program, the DARPA SPAR program, and Texas Instruments, is currently working to improve the linearity and isolation performance of their circulator. Their long-term goal is to build a large-scale mm-wave full-duplex phased array system that uses their circulator.