Tag Archives: letter-ap-tech

Advanced Linear Devices Inc. (ALD), a designer of analog semiconductors, today announced a zero-gate threshold voltage EPAD P-Channel MOSFET Array launching the industry’s first precision sub-threshold circuit. The MOSFET currently has the industry’s lowest operating voltage of 0.2 Volt (V) and current of less than one nano amp (nA). These chips enable the operating regions required for the next generations of development in energy harvesting, Internet of Things (IoT) sensors applications.

The ALD310700A/ALD310700 quad zero threshold MOSFET is intended for the development of small signal precision applications utilizing 0.00V Zero Threshold Voltage. The circuit is ideal for designs requiring very low operating voltages of < +0.5V power supplies. Allowing circuits to operate in the subthreshold region for the first time ever, expands the MOSFET’s operating range into never-before achieved signal levels.

The new MOSFET simplifies circuit biasing schemes and reduces component counts while providing greater precision and sensitivity of sensor applications for IoT engineers. The P-Channel MOSFET can work in conjunction with ALD N-Channel Zero Threshold MOSFET devices in matched sensor applications. The ALD310700A/ALD310700 is the P-channel version of the popular ALD110800A/ALD110800 Precision Zero Threshold N-channel device. Together, these two MOSFET series deliver complementary precision performance. These complementary paired devices enable the design of 0.5% precision current mirrors, current sources, and circuits referenced to power or ground sources including differential amplifier input stages, transmission gates and multiplexers.

Notable device features

  •     Precision offset voltages (VOS): 2mV max.; 10mV max.;
  •     Low minimum operating voltage of less than 0.2V;
  •     Ultra-low minimum operating current of less than 1nA:
  •     Matched and tracked temperature characteristics.

“These devices operate at a point with 100 times lower power than comparable MOSFET arrays. More importantly they enable the next generation of applications at power levels and precision that were impossible until now,” said Robert Chao, President, and Founder, Advanced Linear Devices Inc. “These arrays offer circuit designers working on IoT nodes that require matched sensor activity a method to collect power from supercapacitors or deep cycle batteries.”

As an example, some potential energy harvesting sources, such as thermal electric generators that yield just 0.2V, produce such low levels of energy that they are barely useful for driving power in electronic circuitry. The ALD P-Channel Zero-Threshold (VGS(th)=0.00) EPAD MOSFET arrays can be coupled with a low voltage step-up converter to give low-level power sources a greater range as an energy harvesting source.

This device is available in a quad version and is a member of the EPAD® Matched Pair MOSFET Family. The parts can be ordered directly from ALD or DigiKey and Mouser. Prices start at $2.00 at 100 pieces.

A team of University of Wisconsin–Madison engineers has created the most functional flexible transistor in the world — and with it, a fast, simple and inexpensive fabrication process that’s easily scalable to the commercial level.

It’s an advance that could open the door to an increasingly interconnected world, enabling manufacturers to add “smart,” wireless capabilities to any number of large or small products or objects — like wearable sensors and computers for people and animals — that curve, bend, stretch and move.

Literal flexibility may bring the power of a new transistor developed at UW–Madison to digital devices that bend and move. PHOTO COURTESY OF JUNG-HUN SEO, UNIVERSITY AT BUFFALO, STATE UNIVERSITY OF NEW YORK

Literal flexibility may bring the power of a new transistor developed at UW–Madison to digital devices that bend and move. PHOTO COURTESY OF JUNG-HUN SEO, UNIVERSITY AT BUFFALO, STATE UNIVERSITY OF NEW YORK

Transistors are ubiquitous building blocks of modern electronics. The UW–Madison group’s advance is a twist on a two-decade-old industry standard: a BiCMOS (bipolar complementary metal oxide semiconductor) thin-film transistor, which combines two very different technologies — and speed, high current and low power dissipation in the form of heat and wasted energy — all on one surface.

As a result, these “mixed-signal” devices (with both analog and digital capabilities) deliver both brains and brawn and are the chip of choice for many of today’s portable electronic devices, including cellphones.

“The industry standard is very good,” says Zhenqiang (Jack) Ma, the Lynn H. Matthias Professor and Vilas Distinguished Achievement Professor in electrical and computer engineering at UW–Madison. “Now we can do the same things with our transistor — but it can bend.”

Ma is a world leader in high-frequency flexible electronics. He and his collaborators described their advance in the inaugural issue of the journal npj Flexible Electronics, published Sept. 27.

Making traditional BiCMOS flexible electronics is difficult, in part because the process takes several months and requires a multitude of delicate, high-temperature steps. Even a minor variation in temperature at any point could ruin all of the previous steps.

Ma and his collaborators fabricated their flexible electronics on a single-crystal silicon nanomembrane on a single bendable piece of plastic. The secret to their success is their unique process, which eliminates many steps and slashes both the time and cost of fabricating the transistors.

“In industry, they need to finish these in three months,” he says. “We finished it in a week.”

He says his group’s much simpler high-temperature process can scale to industry-level production right away.

“The key is that parameters are important,” he says. “One high-temperature step fixes everything — like glue. Now, we have more powerful mixed-signal tools. Basically, the idea is for flexible electronics to expand with this. The platform is getting bigger.”

His collaborators include Jung-Hun Seo of the University at Buffalo, State University of New York; Kan Zhang of UW–Madison; and Weidong Zhou of the University of Texas at Arlington.

GLOBALFOUNDRIES is now delivering in volume its 14nm High Performance (HP) technology that will enable IBM’s next-generation of processors for server systems. The jointly developed 14HP process is specifically designed to deliver the ultra-high performance and data-processing capacity IBM needs to support its cloud, commerce, and enterprise solutions in the era of big data and cognitive computing. IBM announced general availability of the IBM Z on September 13.

14HP is the industry’s only technology to integrate a three-dimensional FinFET transistor architecture on a silicon-on-insulator (SOI) substrate. Featuring a 17-layer metal stack and more than eight billion transistors per chip, the technology leverages embedded DRAM and other innovative features to deliver higher performance, reduced energy, and better area scaling over previous generations to address a wide range of deep computing workloads.

The 14HP technology powers the processors that run IBM’s latest z14 mainframes. The underlying semiconductor process allows IBM customers to enable massive transaction scale of high-volume workloads, apply machine learning to their most valuable data, and rapidly derive actionable insights to enable intelligent decisions—all while delivering pervasive encryption that provides the ultimate in data protection.

“GlobalFoundries has been a strategic partner in the development of a custom semiconductor technology to enable the aggressive requirements of the processors for our newest server systems,” said Ross Mauril, general manager, IBM Z. “We are excited to bring this 14HP technology to our IBM Z product line.”

“GF and IBM together have an unmatched heritage of developing and manufacturing ultra-high performance SOI chips,” said Mike Cadigan, senior vice president of global sales and business development at GF. “This new generation of 14HP processors is another example of the close collaboration between our engineering teams to meet the demands of a new generation of server systems.”

“The 14HP technology leverages the proven 14nm FinFET high-volume experience of our Fab 8 facility in Saratoga County, N.Y.,” said Tom Caulfield, senior vice president and general manager of GF’s Fab 8. “We are in high volume production with a broad set of customer designs across a range of applications. Our mature and diverse manufacturing capability will enable IBM to bring its latest processor designs to market to service their broad customer base.”

GLOBALFOUNDRIES today announced the availability of a new set of enhanced RF SOI process design kits (PDKs) to help designers improve their designs of RF switches and deliver differentiated RF front-end solutions for a wide range of markets including front-end modules for mobile devices, mmWave, 5G and other high-frequency applications.

GF’s advanced RF technology platform, 7SW SOI, is optimized for multi-band RF switching in next-generation smartphones and poised to drive innovation in Internet of Things (IoT) applications. Designed for use with Coupling Wave Solutions’ (CWS) simulation tool, SiPEX™, GF’s 7SW SOI PDK allows designers to integrate RF switches with other critical RF blocks that are essential to the design of complex electronic systems for future RF communication chips. Specifically, this new capability allows designers to improve RF simulation output by simulating a highly-resistive substrate parasitic effect across their entire design.

“GF leads the industry in RFSOI technology, and we are committed to providing our customers with design productivity solutions for our RF processes,” said Bami Bastani, senior vice president of RF at GF. “CWS’ SiPEX™ tool provides our customers with best-in-class correlation between simulated results and real world measurements, further optimizing the design layout to achieve efficiency and deliver differentiated RF front-end solutions.”

“This is great news for the RF design community,” said Brieuc Turluche, chairman of the board of directors and chief executive officer of CWS. “The integration of SiPEX into GF’s RF SOI PDKs is a major milestone to achieve first-time correct complex and optimized RF SOI designs for high-performing cellular, IoT, 5G and Wi-Fi communication chips.”

GF’s RF SOI technologies offer significant performance, integration and area advantages in front-end RF solutions for mobile devices and RF chips for high-frequency, high-bandwidth wireless infrastructure applications. CWS’ SiPEX accelerates the design of RF SOI switches by improving linearity simulation accuracy. It can also be effective in the design of low-noise amplifiers (LNA) and power amplifiers (PA), enabling designers to reduce their size to lower costs.

SiPEX™ is available in the current release of GF’s 7SW SOI PDK. For more information on the company’s RF SOI solutions, contact your GF sales representative or go to www.globalfoundries.com.

Decades ago, the Moore’s law predicted that the number of transistors in a dense integrated circuit doubles approximately every two years. This prediction was proved to be right in the past few decades, and the quest for ever smaller and more efficient semiconductor devices have been a driving force in breakthroughs in the technology.

With an enduring and increasing need for miniaturization and large-scale integration of photonic components on the silicon platform for data communication and emerging applications in mind, a group of researchers from the Hong Kong University of Science and Technology and University of California, Santa Barbara, successfully demonstrated record-small electrically pumped micro-lasers epitaxially grown on industry standard (001) silicon substrates in a recent study. A submilliamp threshold of 0.6 mA, emitting at the near-infrared (1.3?m) was achieved for a micro-laser with a radius of 5 μm. The thresholds and footprints are orders of magnitude smaller than those previously reported lasers epitaxially grown on Si.

Their findings were published in the prestigious journal Optica on August 4, 2017 (doi: 10.1364/OPTICA.4.000940).

“We demonstrated the smallest current injection QD lasers directly grown on industry-standard (001) silicon with low power consumption and high temperature stability,” said Kei May Lau, Fang Professor of Engineering and Chair Professor of the Department of Electronic & Computer Engineering at HKUST.

“The realization of high-performance micron-sized lasers directly grown on Si represents a major step toward utilization of direct III-V/Si epitaxy as an alternate option to wafer-bonding techniques as on-chip silicon light sources with dense integration and low power consumption.”

The two groups have been collaborating and has previously developed continuous-wave (CW) optically-pumped micro-lasers operating at room temperature that were epitaxially grown on silicon with no germanium buffer layer or substrate miscut. This time, they demonstrated record-small electrically pumped QD lasers epitaxially grown on silicon. “Electrical injection of micro-lasers is a much more challenging and daunting task: first, electrode metallization is limited by the micro size cavity, which may increase the device resistance and thermal impedance; second, the whispering gallery mode (WGM) is sensitive to any process imperfection, which may increase the optical loss,” said Yating Wan, a HKUST PhD graduate and now postdoctoral fellow at the Optoelectronics Research Group of UCSB.

“As a promising integration platform, silicon photonics need on-chip laser sources that dramatically improve capability, while trimming size and power dissipation in a cost-effective way for volume manufacturability. The realization of high-performance micron-sized lasers directly grown on Si represents a major step toward utilization of direct III-V/Si epitaxy as an alternate option to wafer-bonding techniques,” said John Bowers, Deputy Chief Executive Officer of AIM Photonics.

Researchers examining the flow of electricity through semiconductors have uncovered another reason these materials seem to lose their ability to carry a charge as they become more densely “doped.” Their results, which may help engineers design faster semiconductors in the future, are published online in the journal ACS Nano.

Semiconductors are found in just about every piece of modern electronics, from computers to televisions to your cell phone. They fall somewhere between metals, which conduct electricity very well, and insulators like glass that don’t conduct electricity at all. This moderate conduction property is what allows semiconductors to perform as switches and transistors in electronics.

The most common material for semiconductors is silicon, which is mined from the earth and then refined and purified. But pure silicon doesn’t conduct electricity, so the material is purposely and precisely adulterated by the addition of other substances known as dopants. Boron and phosphorus ions are common dopants added to silicon-based semiconductors that allow them to conduct electricity.

But the amount of dopant added to a semiconductor matters – too little dopant and the semiconductor won’t be able to conduct electricity. Too much dopant and the semiconductor becomes more like a non-conductive insulator.

“There’s a sweet spot when it comes to doping where the right amount allows for the efficient conduction of electricity, but after a certain point, adding more dopants slows down the flow,” says Preston Snee, associate professor of chemistry at the University of Illinois at Chicago and corresponding author on the paper.

“For a long time scientists thought that the reason efficient conduction of electricity dropped off with the addition of more dopants was because these dopants caused the flowing electrons to be deflected away, but we found that there’s also another way too many dopants impede the flow of electricity.”

Snee, UIC chemistry student Asra Hassan, and their colleagues wanted to get a closer look at what happens when electricity flows through a semiconductor.

Using the Advanced Photon Source Argonne National Laboratory, they were able to capture X-ray images of what happens at the atomic level inside a semiconductor. They used tiny chips of cadmium sulfide for their semiconductor “base” and doped them with copper ions. Instead of wiring the tiny chips for electricity, they generated a flow of electrons through the semiconductors by shooting them with a powerful blue laser beam. At the same time, they took very high energy X-ray photos of the semiconductors at millionths of a microsecond apart – which showed what was happening at the atomic level in real time as electrons flowed through the doped semiconductors.

They found that when electrons were flowing through, the copper ions transiently formed bonds with the cadmium sulfate semiconductor base, which is detrimental to conduction.

“This has never been seen before,” said Hassan. “Electrons are still bouncing off dopants, which we knew already, but we now know of this other process that contributes to impeding flow of electricity in over-doped semiconductors.”

The bonding of the dopant ions to the semiconductor base material “causes the current to get stuck at the dopants, which we don’t want in our electronics, especially if we want them to be fast and efficient,” she said. “However, now that we know this is happening inside the material, we can design smarter systems that minimize this effect, which we call ‘charge carrier modulation of dopant bonding’.”

To perpetuate the pace of innovation and progress in microelectronics technology over the past half-century, it will take an enormous village rife with innovators. This week, about 100 of those innovators throughout the broader technology ecosystem, including participants from the military, commercial, and academic sectors, gathered at DARPA headquarters at the kickoff meeting for the Agency’s new CHIPS program, known in long form as the Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies program.

Many future microelectronics systems could be assembled with a library of plug-and-play chiplets that combine their respective modular functions with unprecedented versatility.

Many future microelectronics systems could be assembled with a library of plug-and-play chiplets that combine their respective modular functions with unprecedented versatility.

“Now we are moving beyond pretty pictures and mere words, and we are rolling up our sleeves to do the hard work it will take to change the way we think about, design, and build our microelectronic systems,” said Dan Green, the CHIPS program manager. The crux of the program is to develop a new technological framework in which different functionalities and blocks of intellectual property—among them data storage, computation, signal processing, and managing the form and flow of data—can be segregated into small chiplets, which then can be mixed, matched, and combined onto an interposer, somewhat like joining the pieces of a jigsaw puzzle. Conceivably an entire conventional circuit board with a variety of different but full-sized chips could be shrunk down onto a much smaller interposer hosting a huddle of yet far smaller chiplets.

Central to the design and intention of the program is the creation of a new community of researchers and technologists that mix-and-match mindsets, skillsets, technological strengths, and business interests. That is why the dozen selected prime contractors for the program include large defense companies (Lockheed Martin, Northrop Grumman, and Boeing), large microelectronics companies (Intel, Micron, and Cadence Design Systems), other semiconductor design players (Synopsys, Intrinsix Corp., and Jariet Technologies), and university teams (University of Michigan, Georgia Institute of Technology, and North Carolina State University). What’s more, many of these prime contractors will be working with additional partners who will extend the village of innovators working on the CHIPS program.

“If the CHIPS program is successful, we will gain access to a wider variety of specialized blocks that we will be able to integrate into our systems more easily and with lower costs,” said Green. “This should be a win for both the commercial and defense sectors.”

Among the specific technologies that could emerge from this newly formed research community are compact replacements for entire circuit boards, ultrawideband radio frequency (RF) systems, which require tight integration of fast data converters with powerful processing functions, and, by combining chiplets that provide different accelerator and processor functions, fast-learning systems for teasing out interesting and actionable data from much larger volumes of mundane data. “By bringing the best design capabilities, reconfigurable circuit fabrics, and accelerators from the commercial domain, we should be able to create defense systems just by adding smaller specialized chiplets,” said Bill Chappell, director of DARPA’s Microsystems Technology Office.

“The CHIPS program is part of DARPA’s much larger effort, the Electronics Resurgence Initiative, in which we are striving to build an electronics community that mixes the best of the commercial and defense capabilities for national defense,” Chappell said. “The ERI, which will involve roughly $200 million annual investments for the next four years, will nurture research in materials, device designs, and circuit and system architecture. The next round of investments are expected this September as part of the broader initiative.”

MRSI Systems, a manufacturer of fully automated, ultra-precision, high speed die bonding and epoxy dispensing systems, is launching a new High Speed Die Bonder, MRSI-HVM3, to support photonics customers’ high volume manufacturing requirements. The MRSI-HVM3 is in full production and MRSI Systems is shipping to customers worldwide.

Scaling imperatives

Today, high volume manufacturing of photonic, sensor, and semiconductor devices demands a die bonding system that can deliver industry leading speed without sacrificing high precision and superior flexibility. The new MRSI-HVM3, a high speed, flexible, 3 micron die bonder, has been built to address this challenge. This new system leverages a well-defined set of MRSI’s core competencies, built up over 30 years, in the areas of system design, software development, machine vision, motion control, industrial automation, and process solutions.

Customer outcomes

As Dr. Yi Qian, Vice President of Product Management, states, “The new MRSI-HVM3 incorporates the latest hardware and software innovations. Equipped with ultrafast-ramp eutectic stations, it deploys multiple levels of parallel processing utilizing dual gantries, dual heads, dual bonding stages, and “on-the-fly” tool changes. Used across all products, MRSI’s platform software makes it easy for users to change process settings on their own for new parts, new processes, and new products. These features provide our customers with best-in-class throughput for capacity expansion; high accuracy for high-density packaging; and unmatched flexibility for multi-chip multi-process production in one machine. Ultimately the system will generate great ROIs for customers. The MRSI-HVM3 high speed die bonder supports many applications including chip-on-carrier (CoC), chip-on-submount (CoS), and chip-on-baseplate or board (CoB).”

“MRSI Systems has been serving optoelectronic and microelectronic customers for the past 33 years and understands their requirement to scale efficiently in today’s fast paced marketplace. MRSI is pleased to meet these needs with the launch of our new high speed die bonder for high volume manufacturing of photonics packaging,” said Mr. Michael Chalsen, President, MRSI Systems.

Private demonstrations at CIOE

MRSI Systems is exhibiting at CIOE with their Chinese Representative CYCAD Century Science and Technology (Booth #1C66) in Shenzhen, September 6-9, 2017. There will be private demonstrations of the MRSI-HVM3 performing CoC eutectic and epoxy bonding. Please reach out to your MRSI contact to ensure you have an opportunity to see the capabilities of this new product.

MRSI Systems is a manufacturer of fully automated, high-precision, high-speed die bonding and epoxy dispensing systems.

Samsung Electronics Co., Ltd. has announced new V-NAND (Vertical NAND) memory solutions and technology that will address the pressing requirements of next-generation data processing and storage systems. With the rapid increase of data-intensive applications across many industries using artificial intelligence and Internet of Things (IoT) technologies, the role of flash memory has become extremely critical in accelerating the speed at which information can be extracted for real-time analysis.

At the inaugural Samsung Tech Day and this year’s Flash Memory Summit, Samsung is showcasing solutions to address next-generation data processing challenges centered around the company’s latest V-NAND technology and an array of solid state drives (SSDs). These solutions will be at the forefront of enabling today’s most data-intensive tasks such as high-performance computing, machine learning, real-time analytics and parallel computing.

“Our new, highly advanced V-NAND technologies will offer smarter solutions for greater value by providing high data processing speeds, increased system scalability and ultra-low latency for today’s most demanding cloud-based applications,” said Gyoyoung Jin, executive vice president and head of Memory Business at Samsung Electronics. “We will continue to pioneer flash innovation by leveraging our expertise in advanced 3D-NAND memory technology to significantly enhance the way in which information-rich data is processed.”

Samsung heralds era of 1-terabit (Tb) V-NAND chip

Samsung announced a 1Tb V-NAND chip that it expects to be available next year. Initially mentioned in 2013, during unveiling of the industry’s first 3D NAND, Samsung has been working to enable its core memory technologies to realize one terabit of capacity on a single chip using a V-NAND structure.

The arrival of a 1Tb V-NAND chip next year will enable 2TB of memory in a single V-NAND package by stacking 16 1Tb dies and will represent one of the most important memory advances of the past decade.

NGSFF (Next Generation Small Form Factor) SSD to improve server storage capacity and IOPS

Samsung is sampling the industry’s first 16-terabyte (TB) NGSFF SSD, which will dramatically improve the memory storage capacity and IOPS (input/output operations per second) of today’s 1U rack servers. Measuring 30.5mm x 110mm x 4.38mm, the Samsung NGSFF SSD provides hyper-scale data center servers with substantially improved space utilization and scaling options.

Utilizing the new NGSFF drive instead of M.2 drives in a 1U server can increase the storage capacity of the system by four times. To highlight the advantages, Samsung demonstrated a reference server system that delivers 576TB in a 1U rack, using 36 16TB NGSFF SSDs. The 1U reference system can process about 10 million random read IOPS, which triples the IOPS performance of a 1U server equipped with 2.5-inch SSDs. A petabyte capacity can be achieved using only two of the 576TB systems.

Samsung plans to begin mass producing its first NGSFF SSDs in the fourth quarter of this year, while working to standardize the form factor with industry partners.

Z-SSD: optimized for systems requiring fast memory responsiveness

Following last year’s introduction of its Z-SSD technology, Samsung introduced its first Z-SSD product, the SZ985. Featuring ultra-low latency and high performance, the Z-SSD will be used in data centers and enterprise systems dealing with extremely large, data-intensive tasks such as real-time “big data” analytics and high-performance server caching. Samsung is collaborating with several of its customers on integrating the Z-SSD in upcoming applications.

The Samsung SZ985 requires only 15 microseconds of read latency time which is approximately a seventh of the read latency of an NVMe SSD. At the application level, the use of Samsung’s Z-SSDs can reduce system response time by up to 12 times, compared to using NVMe SSDs.

With its fast response time, the new Z-SSD will play a pivotal role in eliminating storage bottlenecks in the enterprise and in improving the total cost of ownership (TCO).

New approach to storage with proprietary Key Value SSD technology

Samsung also introduced a completely new technology called Key Value SSD. The name refers to a highly innovative method of processing complex data sets. With the sharply increasing use of social media services and IoT applications, which contribute to the creation of object data such as text, image, audio and video files, the complexity in processing this data increases substantially.

Today, SSDs convert object data of widely ranging sizes into data fragments of a specific size called “blocks.” The use of these blocks requires implementation processes consisting of LBA (logical block addressing) and PBA (physical block addressing) steps. However, Samsung’s new Key Value SSD technology allows SSDs to process data without converting it into blocks. Samsung’s Key Value instead assigns a “key” or specific location to each “value,” or piece of object data – regardless of its size. The key enables direct addressing of a data location, which in turn enables the storage to be scaled. Samsung’s Key Value technology enables SSDs to scale-up (vertically) and scale-out (horizontally) in performance and capacity. As a result, when data is read or written, a Key Value SSD can reduce redundant steps, which leads to faster data inputs and outputs, as well as increasing TCO and significantly extending the life of an SSD.

 

GLOBALFOUNDRIES today announced that it has demonstrated silicon functionality of a 2.5D packaging solution for its high-performance 14nm FinFET FX-14 integrated design system for application-specific integrated circuits (ASICs).

The 2.5D ASIC solution includes a stitched interposer capability to overcome lithography limitations and a two terabits per second (2Tbps) multi-lane HBM2 PHY, developed in partnership with Rambus, Inc. Building on the 14nm FinFET demonstration, the solution will be integrated on the company’s next-generation FX-7 ASIC design system built on GF’s 7nm FinFET process technology.

“With the tremendous advances in interconnect and packaging technology that has occurred in recent years, the line between wafer processing and packaging has blurred,” said Kevin O’Buckley, vice president of ASIC product development at GF. “Incorporating 2.5D packaging into ASIC design boosts performance beyond scaling and is a natural evolution of our capabilities. It enables us to support our customers in a one-stop end-to-end fashion, from product design all the way through manufacturing and testing.”

The Rambus memory PHY is aimed at high-end networking and data center applications performing the most data-intensive tasks in systems requiring low-latency and high-bandwidth. The PHY is compliant with the JEDEC JESD235 HBM2 standard, supporting data rates up to 2Gbps per data pin, enabling a total bandwidth of 2Tbps.

“We strive to deliver comprehensive HBM PHY technologies that will enable data center and networking solution providers to meet today’s most demanding workloads and take advantage of compelling market opportunities,” said Luc Seraphin, senior vice president and general manager, Memory and Interfaces Division at Rambus. “Our collaboration with GF combines our HBM2 PHY with their 2.5D packaging and FX-14 ASIC design system and provides a fully-integrated solution for the industry’s fastest-growing applications.”

FX-14 and FX-7 are complete ASIC design solutions that take advantage of GF’s experience in volume production with FinFET process technology. They comprise functional modules based on the industry’s broadest and deepest intellectual property (IP) portfolio, which makes possible unique solutions for next-generation wired/5G wireless networking, cloud/data center servers, machine learning/deep neural networks, automotive, and aerospace/defense applications. GF is one of only two companies in the world that delivers best-in-class IP plus advanced memory and packaging solutions.