Tag Archives: letter-ap-tech

IntelliProp, Inc., a developer of Intellectual Property (IP) Cores and semiconductors for Data Storage and Memory applications, announced today the IPA-PM185-CT, Gen-Z Persistent Memory Controller, code named “Cobra.” This controller combines DRAM and NAND and sits on the Gen-Z fabric, not the memory bus. Cobra has the ability to support byte addressability to DRAM cache and Block addressability to NAND flash supporting up to 32GB of DRAM and 6TB of NAND. IntelliProp is a member of the Gen-Z consortium and is working closely with a number of other companies to support the first multi-company Gen-Z demo, being shown this week at Flash Memory Summit.

IntelliProp is exhibiting at Flash Memory Summit, being held at the Santa Clara Convention Center, August 8-10, 2017. IntelliProp is in booth #821. The Gen-Z “Cobra” Controller along with other IP & ASSP demos will be shown at IntelliProp’s booth. The Gen-Z Cobra controller will also be showcased in the Gen-Z Consortium demo in booth #739.

IntelliProp is also showing the NVMe Host Accelerator IP Core, the IPC-NV164-HI. This Core will find primary application with companies doing FPGA and ASIC designs who need high performance connectivity with PCIe based NVMe storage devices. Compliant with the NVMe 1.3 specification, the NVMe Host Accelerator IP Core provides a simple firmware or RTL driven interface for data movement to and from an NVMe endpoint attached to a PCIe link. “We manage the command and completion queues in hardware to accelerate performance by off-loading the processor from needing to handle numerous interrupts,” said Hiren Patel, VP of Business Development at IntelliProp. “The NVMe Host Accelerator IP Core is shipping today for all Xilinx and Altera FPGAs including the latest Ultrascale Plus and Arria 10 FPGAs.  And for those customers that want acceleration with Linux, IntelliProp has also written a Linux driver to work with the NVMe Host Accelerator IP Core,” continued Mr. Patel.

IntelliProp is excited to also announce the availability of additional NVMe products for the storage market.   IntelliProp has released the IPC-NV171A-BR, NVMe-to-NVMe Bridge and the IPP-NV186A-BR, NVMe-to-SATA Bridge. “The NVMe-to-NVMe bridge allows customers to manipulate data or commands from a PCIe root-complex such as a PC to an NVMe drive. The NVMe-to-SATA bridge allows customers to use SATA drives which will enumerate as NVMe drives in the host system,” said Hiren Patel.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its full-flow digital and signoff tools and the Cadence® Verification Suite have been optimized to support Arm® Cortex®-A75 and Cortex-A55 CPUs, based on Arm DynamIQ™ technology, and the Arm Mali™-G72 GPU, the latest offerings from Arm for premium mobile, machine learning, and consumer devices. To accelerate the adoption of Arm’s latest processors, Cadence delivered new 7nm-ready Rapid Adoption Kits (RAKs) for the Cortex-A75 and the Cortex-A55 CPUs, which include the DynamIQ Shared Unit (DSU) that provides a shared level 3 cache between the CPUs, and a 7nm-ready RAK for the Mali-G72 GPU.

Customers are already using the complete digital and signoff flow and the Cadence Verification Suite to tape out complex systems-on-chip (SoCs) containing the latest Arm Cortex and Mali processors. To learn more about the Cadence full-flow digital and signoff solutions that support the Cortex-A75, Cortex-A55, and Mali-G72 processors, please visit www.cadence.com/go/dandsarmraks7nm. For more information on the Cadence Verification Suite that enables Arm-based designs using the Cortex-A75, Cortex-A55 and Mali-G72 processors, please visit www.cadence.com/go/vsuitearm7nm.

The Cadence RAKs accelerate physical implementation, signoff, and verification of 7nm designs, allowing designers to deliver mobile and consumer devices to market faster. With the delivery of the new RAKs, Cadence is also providing specialized technical support for Arm IP implementation based on the deep collaboration between Arm and Cadence over many years.

The Cadence digital and signoff tools have been configured to provide optimal power, performance and area (PPA) results using the RAKs, which include scripts, an example floorplan, and documentation for Arm’s 7nm IP libraries. The comprehensive Cadence RTL-to-GDS flow incorporates the following digital and signoff tools in the RAKs:

  • Innovus™ Implementation System: Statistical on-chip variation (SOCV) propagation and optimization results in improved timing, power, and area closure for 7nm designs
  • Genus™ Synthesis Solution: Register-transfer level (RTL) synthesis supports all the latest 7nm advanced-node requirements and provides convergent design closure using the Innovus Implementation System
  • Conformal® Logic Equivalence Checking (LEC): Ensures the accuracy of logic changes and engineering change orders (ECOs) during the implementation flow
  • Conformal Low Power: Enables the creation and validation of power intent in context of the design, combining low-power equivalence checking with structural and functional checks to allow full-chip verification of power-efficient designs
  • Tempus™ Timing Signoff Solution: Offers path-based, signoff-accurate and physically aware design optimization, providing the quickest path to tapeout
  • Voltus™ IC Power Integrity Solution: Static and dynamic analysis used during implementation and signoff ensures optimal power distribution
  • Quantus™ QRC Extraction Solution: Fulfills all 7nm advanced-node requirements to ensure accurate correlation to final silicon

“The Cortex-A75 and Cortex-A55 CPUs deliver distributed intelligence from edge-to-cloud, and pairing them with the Mali-G72 GPU enables consumers to experience stunning graphics efficiently across multiple devices,” said Nandan Nayampally, vice president and general manager, Compute Products Group, Arm. “By continuing to collaborate with Cadence on the delivery of new digital implementation and signoff RAKs along with optimization of the Cadence Verification Suite, our mutual customers can quickly integrate and augment their differentiated solutions for next-generation devices.”

The Cadence Verification Suite that has also been optimized for Arm-based designs includes:

  • JasperGold® Formal Verification Platform: Enables IP and subsystem verification including formal proofs for Arm AMBA® protocols
  • Xcelium® Parallel Logic Simulation: Provides production-proven multi-core simulation accelerating SoC development and validation of Arm-based designs
  • Palladium® Z1 Enterprise Emulation Platform: Includes hybrid technology that is integrated with Arm Fast Models for up to 50X faster OS and software bring-up and up to 10X faster software-based testing in addition to Dynamic Power Analysis technology for low power
  • Protium™ S1 FPGA-Based Prototyping Platform: Integration with the Palladium Z1 enterprise emulation platform combined with Arm DS-5 provides pre-silicon embedded software debug
  • vManager™ Planning and Metrics: Metric-driven verification across the JasperGold platform, Xcelium simulation, Palladium Z1 platform and Cadence VIP solutions for Arm-based SoC verification convergence
  • Perspec™ System Verifier: Provides software-driven use-case verification with the PSLib for Armv8 architectures, delivering up to 10X productivity improvement versus typical manual test development
  • Indago™ Debug Platform: RTL design, testbench and embedded software debug capabilities synchronized with Arm CPUs for accurate combined views of hardware and software
  • Cadence Verification Workbench: Integrates with Arm Socrates™ packaged Armv8 IP and VIP for fast SoC integration and UVM testbench assembly
  • Cadence Interconnect Workbench: Provides fast performance analysis and verification of Arm CoreLink™interconnect intellectual property (IP)-based systems in combination with Xcelium simulation, the Palladium Z1 platform, and Cadence Verification IP
  • Verification IP Portfolio: Enables IP and SoC verification including Arm AMBA interconnect, supporting Xcelium simulation, the JasperGold platform, and the Palladium Z1 platform

“We worked closely with Arm to optimize our advanced digital implementation and signoff solutions and our verification solutions for the new Arm CPUs and GPU so our customers can efficiently create 7nm mobile and consumer designs,” said Dr. Anirudh Devgan, executive vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Designers using the RAKs and the Cadence Verification Suite can benefit from improved PPA and reduced project times, while creating the most advanced Arm-based products.”

Transistors, as used in billions on every computer chip, are nowadays based on semiconductor-type materials, usually silicon. As the demands for computer chips in laptops, tablets and smartphones continue to rise, new possibilities are being sought out to fabricate them inexpensively, energy-saving and flexibly. The group led by Dr. Christian Klinke has now succeeded in producing transistors based on a completely different principle. They use metal nanoparticles which are so small that they no longer show their metallic character under current flow but exhibit an energy gap caused by the Coulomb repulsion of the electrons among one another. Via a controlling voltage, this gap can be shifted energetically and the current can thus be switched on and off as desired. In contrast to previous similar approaches, the nanoparticles are not deposited as individual structures, rendering the production very complex and the properties of the corresponding components unreliable, but, instead, they are deposited as thin films with a height of only one layer of nanoparticles. Employing this method, the electrical characteristics of the devices become adjustable and almost identical.

These Coulomb transistors have three main advantages that make them interesting for commercial applications: The synthesis of metal nanoparticles by colloidal chemistry is very well controllable and scalable. It provides very small nanocrystals that can be stored in solvents and are easy to process. The Langmuir-Blodgett deposition method provides high-quality monolayered films and can also be implemented on an industrial scale. Therefore, this approach enables the use of standard lithography methods for the design of the components and the integration into electrical circuits, which renders the devices inexpensive, flexible, and industry-compatible. The resulting transistors show a switching behavior of more than 90% and function up to room temperature. As a result, inexpensive transistors and computer chips with lower power consumption are possible in the future. The research results have now been published in the scientific journal “Science Advances“.

“Scientifically interesting is that the metal particles inherit semiconductor-like properties due to their small size. Of course, there is still a lot of research to be done, but our work shows that there are alternatives to traditional transistor concepts that can be used in the future in various fields of application”, says Christian Klinke. “The devices developed in our group can not only be used as transistors, but they are also very interesting as chemical sensors because the interstices between the nanoparticles, which act as so-called tunnel barriers, react highly sensitive to chemical deposits.”

ASM International introduced the Intrepid® ESTM 300mm epitaxy (epi) tool for advanced-node CMOS logic and memory high-volume production applications. Intrepid ES introduces innovative closed loop reactor control technology that enables optimal within wafer and wafer-to-wafer process performance, critical for today’s advanced transistors and memories. Furthermore, Intrepid ES reduces the cost per wafer significantly for a 7nm epi process compared with prior node processes. The new tool has been qualified for production at a leading-edge foundry customer, and is targeting production applications in other industry segments as well. To date, over 40 reactors have been delivered.

“Over the past several years, multiple customers have been very clear that there is a need to address several technical and cost challenges in the epi market,” said Chuck del Prado, President and Chief Executive Officer of ASM International. “Intrepid ES is the result of a focused development program to address major challenges in this market, including film non-uniformity, process repeatability, tool uptime and high cost per wafer. This early success of the Intrepid ES clearly demonstrates that we are on track in addressing our customers’ emerging epi requirements.”

The new Intrepid ES tool is based on a combination of reactor and platform design improvements. It demonstrates improved film performance and enhanced reactor stability. Fundamental to its technology is an isothermal reactor environment in which the wafer is processed. This provides consistent and repeatable temperature control across the wafer and wafer-to-wafer.

Two European research institutes today announced their new collaboration to develop innovative, next-generation microelectronics technologies to spur innovation in their countries and strengthen European strategic and economic sovereignty.

Leti, a research institute of CEA Tech in Grenoble, France, and the Berlin-based Fraunhofer Group for Microelectronics, Europe’s largest R&D provider of smart systems, will initially focus on extending CMOS and More-than-Moore technologies to enable next-generation components for applications in the Internet of Things, augmented reality, automotive, health, aeronautics and other sectors, as well as systems to support French and German industries.

The agreement was signed today by Leti CEO Marie Semaria and Fraunhofer Group for Microelectronics Chairman Hubert Lakner during Leti Innovation Days, which are marking Leti’s 50th anniversary.

“The ability to, one, develop key enabling technologies that overcome the formidable technical challenges that our leading technology companies will face, and, two, transfer them quickly to industry, is an essential focus for research institutes and industrials in France and Germany,” Semaria said. “Building on our previous, successful collaborations, Leti and the Fraunhofer Group for Microelectronics will bring our complementary strengths to the task of keeping France and Germany’s microelectronics industries in the forefront – and offer our innovations across Europe.”

“Micro-/nanoelectronics and smart systems are key enabling technologies for the economic success of Europe, especially in France and Germany. Thus, Europe can no longer afford to scatter its research competences. For the benefit of industry, joining forces will become more and more important, not only for industry but also for RTOs,” Lakner explained. “The new cooperation agreement will be the starting point for a strategic research cooperation of the two countries in order to jointly support the upcoming EC initiative, Important Project of Common European Interest (IPCEI), on micro- and nanoelectronics.”

Specific R&D projects that the collaboration will focus on include:

o    Silicon-based technologies for next-generation CMOS processes and products, including design, simulation, unit process and material development as well as production techniques

o    Extended More than Moore technologies for sensing and communication applications

o    Advanced-packaging technologies.

The second phase of the collaboration may be expanded with additional academic partners and other countries, as needed.

The SEMI Foundation and the Micron Technology Foundation announced their partnership this week to deliver the 213th SEMI High Tech U (HTU) program which kicks off in earnest today at Micron’s facilities in Milpitas. Forty students from local high schools are attending the three-day science, technology, engineering and math (STEM) program.

The nonprofit SEMI Foundation has been holding its flagship program, SEMI High Tech U, at industry sites around the world since 2001 to emphasize the importance of STEM skills and inspire young people to pursue careers in high technology fields. HTU allows students to meet engineers and volunteer instructors from industry in a face-to-face setting with tech-related, hands-on activities such as etching wafers, making circuits, coding and professional interviews training.

“We are delighted to partner with Micron in our common goal to motivate the next generation of innovators,” said Ajit Manocha, president and CEO of SEMI and the SEMI Foundation. “HighTech U has reached more than 6,000 students in eleven states as well as nine countries internationally. We are pleased to join with Micron to serve students here in Silicon Valley.”

“Micron Technology Foundation has been inspiring learners of all ages and supporting early exposure to technology through our own Micron Chip Camp for 17 years,” said Sanjay Mehrotra, Micron president and CEO. “SEMI High Tech U is complementary to these efforts and we are proud to partner with the SEMI Foundation to deliver our first joint program focused on high school students to promote careers in STEM-related high tech industries such as semiconductor manufacturing.”

 

Ajit Manocha, president and CEO of SEMI, and Sanjay Mehrotra, president and CEO of Micron, with SEMI High Tech U students.

Ajit Manocha, president and CEO of SEMI, and Sanjay Mehrotra, president and CEO of Micron, with SEMI High Tech U students.

Manocha and Mehrotra jointly welcomed participating students to the SEMI HTU program and shared highlights of their professional experience during a pre-event kick-off at Micron in Milpitas on Monday, June 26. Students will spend Tuesday at Micron working on STEM focused, hands-on activities. Micron team members will assist in teaching the modules, offering students a connection to semiconductor professionals. On Wednesday, the program convenes at San Jose State University where students will learn about etching wafers and tour the SJSU campus. The program will culminate Thursday at Micron with critical thinking and soft skills development activities along with mock interviews. Students will “graduate” from SEMI High Tech U on Thursday afternoon at Micron.

Synopsys, Inc. (Nasdaq: SNPS) today announced the enablement of the Synopsys Design Platform and DesignWare Embedded Memory IP on GLOBALFOUNDRIES 7nm Leading-Performance (7LP) FinFET process technology. Synopsys and GF collaboration on the new process addressed several new challenges specific to the 7LP process. This process is expected to deliver 40 percent more processing power and twice the area scaling compared to GF’s 14nm FinFET process. Designers of premium mobile processors, cloud servers and networking infrastructure can take advantage of these benefits by confidently deploying the silicon-proven Synopsys Design Platform and Embedded Memory IP.

“GF’s leading-performance 7nm platform is exceeding initial performance targets and is now ready for customer designs,” said Alain Mutricy, senior vice president of product management at GF. “GF and Synopsys have collaborated to provide designers with tools and methodology that fully leverage the power and highest absolute performance of our 7LP technology, and will allow customers to create innovative products across a range of high-performance applications.”

GF and Synopsys worked together to ensure support of the comprehensive suite of Synopsys Design Platform digital implementation solutions for GF 7LP, including Design Compiler Graphical synthesis, IC Compiler II place-and-route, IC Validator physical verification, PrimeTime static timing analysis and StarRC extraction. To enable designers to achieve the full benefit of the GF 7LP process, the Synopsys tools employ advanced techniques including color track generation, pin color alignment checking and legalization, mixing of single-height and double-height physical boundary cells, power grid alignment to track and color-track aware routing.

The two companies are also collaborating on the development of Synopsys DesignWare Memory Compilers to deliver leading performance, power, area and yield for GF’s 7nm process technology. This joint effort consists of optimizing the GF 7LP process design rules and line patterns to achieve the best results. Early versions of the memory compilers will be on the GF 7LP process qualification vehicle.

“Synopsys and GF have always worked closely to address our customers’ needs, including collaborations on FDSOI and 14nm FinFET processes,” said Michael Jackson, corporate vice president of marketing and business development in the Design Group at Synopsys. “With today’s announcement, we are ready to enable designs on the 7LP process. We will continue to collaborate and ensure that our customers can get superior quality of results and faster time to results by using the Synopsys Design Platform and DesignWare Embedded Memory IP.”

MagnaChip Semiconductor Corporation (NYSE: MX), a Korea-based designer and manufacturer of analog and mixed-signal semiconductor platform solutions for communications, IoT, consumer, industrial and automotive applications, announced today it now offers 0.13 micron BCD process technology integrated with high-density embedded Flash. This BCD process offers 40V power LDMOS and delivers 64K Bytes flash memory, making it suitable for programmable PMIC, wireless power chargers and USB-C power-delivery IC products.

Increasingly, products such as programmable PMICs, wireless power chargers and USB-C power-delivery ICs require embedded non-volatile memory and other functions to be integrated onto a single Power IC.  Aside from embedded non-volatile memory, which is used for program code storage, these products require power LDMOS, which is well suited for high-power requirements. The inclusion of embedded FLASH is crucial in order to minimize chip size when high non-volatile memory density is required.  For IoT and automotive applications, this BCD process provides 1.5V and 5V CMOS devices with a very low leakage current level that enables low-power consumption.  Furthermore, this new BCD process has various option devices for Hall sensors, varactors, inductors, and RF CMOS devices that are useful for highly integrated IC solutions, which yield smaller system size and lower system cost.

MagnaChip’s 30V high voltage with embedded Flash process for touch IC is already in volume production, and the new BCD with embedded Flash 40V process announced today is now being adopted by foundry customers. Embedded Flash IP, designed and verified by MagnaChip, reduces foundry customers’ design time by providing proven intellectual property (IP) with a range of diverse memory densities. MagnaChip also verifies and provides key analog intellectual property, such as ADC (Analog-to-Digital Converter), DAC (Digital-to-Analog Converter), LDO (Low Dropout Regulator), POR (Power On Reset), PLL (Phase Locked Loop), OSC (Oscillator), which reduces design time.

YJ Kim, Chief Executive Officer of MagnaChip, commented, “The combination of analog-based BCD and non-volatile memory is ideal for producing power management solutions and power ICs used in smartphones, IoT devices and for USB-C applications.” Mr. Kim added, “Our goal is to continue to develop specialized process technologies that meet the increasing needs for the application-specific solutions of our foundry customers.”

BY DR. PHIL GARROU, Contributing Editor

The need for ever more computational power continues to grow and exaflop (1018 ) capabilities may soon become necessary. A paper by AMD on “Design and Analysis of an APU for Exascale Computing” presented at the IEEE High Performance Computing Architec- tures Conference (HPCA) gave the AMD vision for an exascale node architecture for exascale computing including low-power and high-performance CPU cores, integrated energy-efficient GPU units, in-package high-bandwidth 3D memory, die-stacking and chiplet technologies, and advanced memory systems.

Two of the building blocks for this exascale node architecture are (1) it’s chiplet-based approach that decouples performance-critical processing components like CPUs and GPUs from components that do not scale well with technology (e.g., analog components), allowing fabrication in individually optimized process technologies for cost reduction and design reuse in other market segments and (2) the use of in-package 3D memory, which is stacked directly above high- bandwidth-consuming GPUs.

The exascale heterogeneous processor (Figure 1) is an accelerated processing unit (APU) consisting of CPU and GPU compute integrated with in-package 3D DRAM. The overall structure makes use of a modular “chiplet” design, with the chiplets 3D-stacked on other “active interposer” chips. “The use of advanced packaging technologies enables a large amount of computational and memory resources to be located in a single package.” The exascale targets for memory bandwidth and energy efficiency are incredibly challenging for off-package memory solutions. Thus AMD proposes to integrate 3D-stacked DRAM into the EHP package.

In the center of the EHP are two CPU clusters, each consisting of four multi-core CPU chiplets stacked on an active interposer base die. On either side of the CPU clusters are a total of four GPU clusters, each consisting of two GPU chiplets on a respective active interposer. Upon each GPU chiplet is a 3D stack of DRAM. The DRAM is directly stacked on the GPU chiplets to maximize bandwidth. The interposers underneath the chiplets provide interconnection between the chiplets along with other functions such as external I/O interfaces, power distribution and system management. Interposers maintain high-bandwidth connectivity among themselves by utilizing wide, short distance, point-to-point paths.

Chiplets

The performance requirements require a large amount of compute and memory to be integrated into a single package. Rather than build a single, monolithic system on chip (SOC), AMD proposes to leverage advanced die-stacking technologies to decompose the EHP into smaller components consisting of active interposers and chiplets. Each chiplet houses either multiple GPU compute units or CPU cores. The chiplet approach differs from conventional multi-chip module (MCM) designs in that each individual chiplet is not a complete chip. For example, the CPU chiplet contains CPU cores and caches, but lacks memory interfaces and external I/O.

A monolithic SOC imposes a single process technology choice on all components in the system. With chiplets and interposers, each discrete piece of silicon can be optimized for its own functions. It is expected that smaller chiplets will have higher yield due to their size, and when combined with KGD testing, can be assembled into larger systems at reasonable cost.

It is expected that the decomposition (or disintegration as I prefer to call it) of the EHP into smaller pieces will enable silicon-level reuse of IP (note – this is one of the main drivers of the DARPA CHIPS program)

Imec, a research and innovation hub in nano-electronics and digital technologies, and Cascade Microtech, a FormFactor company, announced the successful development of a fully-automatic system for pre-bond testing of advanced 3D chips. Pre-bond testing is important to increase the yield of 3D stacked chips. The new system enables probing and hence testing of chips with large arrays of 40µm-pitch micro-bumps, on 300mm wafers. The relevance of this new tool is underlined by winning the 2017 National Instruments Engineering Impact Award yesterday at a ceremony in Austin, Texas.

As an emerging technology, 3D IC stacking still has many open options and technical challenges. One of these challenges is probing of the individual chips, before being stacked, to ensure a good yield of the 3D stacked ICs. The inter-chip connections of 3D stacked ICs are made by large arrays of fine-pitch micro-bumps which makes probing these bumps a challenge. Until today, the probing solution is to add dedicated pre-bond probe pads to the to-be-stacked dies, but this requires extra space and design effort and increases test time.

Imec and Cascade Microtech have now developed a fully automatic test cell that can provide test access by probing large arrays of fine-pitch micro-bumps. The system is based on a Cascade Microtech CM300 probe station and National Instruments PXI test instrumentation, complemented by in-house developed software for automatic test generation, data analysis, and visualization. The system allows testing of wafers up to 300mm diameter, including thinned wafers on tape frame with exposed through-silicon vias. After several years of intense collaboration between imec and Cascade Microtech, partly supported by the EU-funded FP7 SEA4KET project, good results were achieved with Cascade Microtech’s Pyramid Probe prototype RBI probe cards on imec’s 300mm wafers with 40µm-pitch micro-bumped chips.

“Imec provided us with unique early insights into the test requirements for 3D ICs, which drove the development of this system,” said Jörg Kiesewetter, director of engineering at Cascade Microtech Dresden. “Also the availability of imec’s dedicated micro-bump test wafers has helped us to fine-tune both the probe station and the probe cards for this application.”

“At imec, we are using the system now on a routine basis to test our 40µm-pitch micro-bumped wafers,” stated Erik Jan Marinissen, principal scientist at imec. “As everything in the semiconductor realm, also micro-bumps are subject to downscaling. Hence, with Cascade, we have started experiments to also probe our 20µm-pitch micro-bump arrays, and those look promising.”