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The 63rd annual IEEE International Electron Devices Meeting (IEDM), to be held at the Hilton San Francisco Union Square hotel December 2-6, 2017, has issued a Call for Papers seeking the world’s best original work in all areas of microelectronics research and development.

The paper submission deadline this year is Wednesday, August 2, 2017. For the second year in a row the IEDM submission deadline is about 1½ months later than what had been the norm, reducing the time between paper submissions and publication of the cutting-edge research results for which the conference is known. Authors are asked to submit four-page camera-ready abstracts (instead of the traditional three pages), which will be published as-is in the proceedings.

Only a very limited number of late-news papers will be accepted. Authors are asked to submit late-news abstracts announcing only the most recent and noteworthy developments. The late-news submission deadline is September 11, 2017.

“Based on the success of the later paper-submission deadline last year, we have decided to make it an IEDM tradition,” said Dr. Barbara DeSalvo, Chief Scientist at Leti. “This helps ensure a rich and unique technical program.”

At IEDM each year, the world’s best scientists and engineers in the field of microelectronics gather to participate in a technical program consisting of more than 220 presentations, along with special luncheon presentations and a variety of panels, special sessions, Short Courses, IEEE/EDS award presentations and other events highlighting leading work in more areas of the field than any other conference.

This year special emphasis is placed on the following topics:
Advanced memory technologies
More-than-Moore device concepts
Neuromorphic computing/machine learning
Optoelectronics, photonics, displays and imaging systems
Package-device level interactions
Sensors and MEMS devices for biological/medical applications
Spin for memory and logic
Steep subthreshold devices
Technologies for 5nm and beyond

Overall, papers in the following areas of technology are encouraged:

  • Circuit and Device Interaction
  • Characterization, Reliability and Yield
  • Compound Semiconductor and High-Speed Devices
  • Memory Technology
  • Modeling and Simulation
  • Nano Device Technology
  • Optoelectronics, Displays and Imagers
  • Power Devices
  • Process and Manufacturing Technology
  • Sensors, MEMS and BioMEMS

As electronics become increasingly pervasive in our lives – from smart phones to wearable sensors – so too does the ever rising amount of electronic waste they create. A United Nations Environment Program report found that almost 50 million tons of electronic waste were thrown out in 2017–more than 20 percent higher than waste in 2015.

Troubled by this mounting waste, Stanford engineer Zhenan Bao and her team are rethinking electronics. “In my group, we have been trying to mimic the function of human skin to think about how to develop future electronic devices,” Bao said. She described how skin is stretchable, self-healable and also biodegradable – an attractive list of characteristics for electronics. “We have achieved the first two [flexible and self-healing], so the biodegradability was something we wanted to tackle.”

The team created a flexible electronic device that can easily degrade just by adding a weak acid like vinegar. The results were published May 1 in the Proceedings of the National Academy of Sciences.

A newly developed flexible, biodegradable semiconductor developed by Stanford engineers shown on a human hair. Credit: Bao Lab

A newly developed flexible, biodegradable semiconductor developed by Stanford engineers shown on a human hair. Credit: Bao Lab

“This is the first example of a semiconductive polymer that can decompose,” said lead author Ting Lei, a postdoctoral fellow working with Bao.

In addition to the polymer – essentially a flexible, conductive plastic – the team developed a degradable electronic circuit and a new biodegradable substrate material for mounting the electrical components. This substrate supports the electrical components, flexing and molding to rough and smooth surfaces alike. When the electronic device is no longer needed, the whole thing can biodegrade into nontoxic components.

Biodegradable bits

Bao, a professor of chemical engineering and materials science and engineering, had previously created a stretchable electrode modeled on human skin. That material could bend and twist in a way that could allow it to interface with the skin or brain, but it couldn’t degrade. That limited its application for implantable devices and – important to Bao – contributed to waste.

Bao said that creating a robust material that is both a good electrical conductor and biodegradable was a challenge, considering traditional polymer chemistry. “We have been trying to think how we can achieve both great electronic property but also have the biodegradability,” Bao said.

Eventually, the team found that by tweaking the chemical structure of the flexible material it would break apart under mild stressors. “We came up with an idea of making these molecules using a special type of chemical linkage that can retain the ability for the electron to smoothly transport along the molecule,” Bao said. “But also this chemical bond is sensitive to weak acid – even weaker than pure vinegar.” The result was a material that could carry an electronic signal but break down without requiring extreme measures.

In addition to the biodegradable polymer, the team developed a new type of electrical component and a substrate material that attaches to the entire electronic component. Electronic components are usually made of gold. But for this device, the researchers crafted components from iron. Bao noted that iron is a very environmentally friendly product and is nontoxic to humans.

The researchers created the substrate, which carries the electronic circuit and the polymer, from cellulose. Cellulose is the same substance that makes up paper. But unlike paper, the team altered cellulose fibers so the “paper” is transparent and flexible, while still breaking down easily. The thin film substrate allows the electronics to be worn on the skin or even implanted inside the body.

From implants to plants

The combination of a biodegradable conductive polymer and substrate makes the electronic device useful in a plethora of settings – from wearable electronics to large-scale environmental surveys with sensor dusts.

“We envision these soft patches that are very thin and conformable to the skin that can measure blood pressure, glucose value, sweat content,” Bao said. A person could wear a specifically designed patch for a day or week, then download the data. According to Bao, this short-term use of disposable electronics seems a perfect fit for a degradable, flexible design.

And it’s not just for skin surveys: the biodegradable substrate, polymers and iron electrodes make the entire component compatible with insertion into the human body. The polymer breaks down to product concentrations much lower than the published acceptable levels found in drinking water. Although the polymer was found to be biocompatible, Bao said that more studies would need to be done before implants are a regular occurrence.

Biodegradable electronics have the potential to go far beyond collecting heart disease and glucose data. These components could be used in places where surveys cover large areas in remote locations. Lei described a research scenario where biodegradable electronics are dropped by airplane over a forest to survey the landscape. “It’s a very large area and very hard for people to spread the sensors,” he said. “Also, if you spread the sensors, it’s very hard to gather them back. You don’t want to contaminate the environment so we need something that can be decomposed.” Instead of plastic littering the forest floor, the sensors would biodegrade away.

As the number of electronics increase, biodegradability will become more important. Lei is excited by their advancements and wants to keep improving performance of biodegradable electronics. “We currently have computers and cell phones and we generate millions and billions of cell phones, and it’s hard to decompose,” he said. “We hope we can develop some materials that can be decomposed so there is less waste.”

MRAM lowers system power


April 28, 2017

BY BARRY HOBERMAN, CEO, Spin Transfer Technologies

ST-MRAM (spin-transfer magnetic RAM) is an extremely promising new technology with the potential to replace major segments of the market for flash, SRAM, and DRAM semiconductors in applications such as mobile products, automotive, IoT, and data storage. With ST MRAM technology, data is stored in minute magnetic nodes—a physical mechanism different from traditional non-volatile memory (NVM). MRAM technology fundamentally requires less energy to use, and features like byte-addressability that further contributes to energy efficiency.

Embedded MRAM primarily fills the role that is currently handled by embedded NOR flash: storage of code and data that must survive when the power is removed. Indeed, MRAM is challenging NOR flash due to overall lower power and byte-addressability.

Energy consumption starts with voltages and currents: their product yields the power of the device – that is, the rate of energy consumption. Lower voltages and currents mean lower power. Energy consumed is determined by how long that rate is sustained – power multiplied by operating time. Therefore speed, the ability to finish a job sooner, also contributes to lower energy consumption especially when devices can enter sleep mode after tasks are complete.

To understand how NOR flash consumes energy, we need to look at how it operates. Let’s say we have a 32-bit word whose value we wish to update. With NOR flash, you can store data only in locations that have been freshly erased. This means you have to erase the old value before you can write the new value.

But there’s a more significant challenge; you can’t just erase those 32 bits. NOR flash can only be erased in sectors. So, in order to update those 32 bits, you have to find a new place to write them. This means creating and maintaining pointers to keep track of stored data since, with each update, the data location will move. Eventually, you run out of fresh space, and must perform garbage collection to free up the space used by all the out-of-date instances.

By contrast, MRAM has none of these requirements. Because it is byte-addressable, you can read and write just as you would with SRAM. Those 32 bits that needed updating? You simply write the new value over the old value. MRAM consumes less energy for a number of reasons:

No erase before writing: NOR flash erasure is very slow. With MRAM, there’s really no notion of erasing data; you’re either writing 1s or 0s, in any combination. The need to erase is a key contributor to the energy consumption of a NOR flash device.
Faster, lower-power writing: Not only can MRAM devices be written more quickly than NOR flash (even without considering erasure), the power while writing is also lower. The fact that you can complete the operation sooner means you can put the device to sleep sooner, yet another advantage to lowering energy.

No charge pumps: NOR flash, unlike MRAM, needs high voltages internally – much higher than the voltages at the external power pins. Those voltages are generated by internal charge pumps. Ideally, power would stay the same, but real charge pumps aren’t ideal; their inefficiency means lost energy.
Charge pumps also take longer to power up, and settle after a sleeping device awakens. This increases wake-up times dramatically. MRAM wakes up in nanoseconds to micro- seconds; NOR flash in milliseconds.

No complex storage management: The lack of byte-addressability in NOR flash creates complexity that increases the time to store data and code. Data tables must be maintained, along with the occasional garbage collection. The CPU, or some other circuit, must manage this data storage. These other devices consume energy, so the more time spent managing data, the more energy consumed. This energy consumption doesn’t apply to MRAM technology.

Mixed read/write stream: NOR flash storage operations, due to complexity, mean long lock-out times during writes. No data reading is permitted during these times. If certain pieces of data are quickly needed, then further management may be required to anticipate this ahead of a data write, so the data can be cached. By contrast, MRAM can handle a stream of operations – reads and writes – in any combination.

Staggered writing: Data can be stored 32 bits at a time. While overall energy consumption in doing this is lower for MRAM than for NOR flash, it still might challenge the peak current capabilities of a battery-powered device. The ability for MRAM to break the write into four successive single-byte writes, a feature known as “staggered write,” reduces current demands on the battery.

A case study is presented based on the use of high throughput experimentation (HTE) for the discovery of new memory materials.

BY LARRY CHEN, MARK CLARK, CHARLENE CHEN, SUSAN CHENG and MILIND WELING, IMI Inc., San Jose, CA

The ever increasing demands for data translate into more sophisticated and specific thin film requirements for semiconductor materials. Each film layer has to not only demonstrate desired film properties, but also show good interfacial behavior with neighboring layers to contribute to the performance of the whole film stack or device. As a result, modern thin film material systems are including more elements from the periodic table with more complex compositions. The demand for short time to market has also increased, making the development of new materials even more difficult. In this paper, we present a case study of using high throughput experimentation (HTE) for the discovery of new memory materials. By using a combinatorial approach of sputtering technology, HTE can be applied to PVD chalcogenides and other materials targeted at memory semiconductors.
PVD background

Ever since the deposition of materials by magnetron sputtering was introduced by F. M. Penning, the technology has become a major method for industrial thin film deposition, which typically generates dense, hard, and robust thin film materials at relatively low production cost. The technology has been applied to major industries such as semiconductors, photovoltaics, optical coatings, displays, hard mechanical coatings, and so on. However, optimizing the magnetron sputtering processes has always been challenging to process and hardware design engineers, since material properties like density, crystalline structure, grain size, optical indices of a deposited film strongly depend on various process parameters, such as power, pressure, substrate temperature, sputter gas type, plasma type, sputter source to substrate distance, substrate bias, and pumping throughput. Additionally, the material properties heavily depend on the underlying layers, including the chosen substrate, below a film stack due to a texture effect in film structure and a formation of interfacial layers which comes from the intermixing of both materials. All the above parameters contribute to increasing the level of complexity of the development.

The semiconductor industry is constantly searching for new materials with unprecedented physical, optical, electrical, and mechanical properties, not only as a single film but also as a component of complex featured film stacks or functioning devices. This requires exploration of new materials not limited to pure or binary systems, but to ternary, quaternary systems and beyond. A very efficient solution to cope with the increasing complexity of development and the demand for short development time is a combinatorial approach.

The combinatorial approach can be defined as a process that couples the capability for parallel production of large arrays of diverse materials together with different high-throughput measurement techniques for various intrinsic and performance properties supported by data analytics for identifying lead materials [3]. For magnetron sputtering technology, the optimization of process param- eters has to be included as a major component of combinatorial approach. Considering all the multi-dimensional space of the development mentioned above, the combinatorial approach can be an excellent and efficient way of developing new materials in magnetron sputtering in terms of cost and time.

HTE methodology for PVD materials discovery

Platform Considerations As all process parameters in magnetron sputtering are somewhat correlated, it has been challenging for process engineers to come up with fully optimized process parameters for thin film production. In addition, semiconductor production facilities are typically optimized for consistent, efficient, high volume production of a single product at a time, and not for a wide range of simultaneous experiments. These factors make it challenging for memory manufacturers to test multiple materials, conditions and devices in an efficient manner, and without compromising either data quality or production throughput.

IMI’s high throughput experimentation (HTE) platform is set up for accelerated experimentation. Its combina- torial PVD tool typically has four sputter guns and one additional port at the center. All sputter guns can be equipped with various types of target materials including chalcogenides, puremetals, oxides, and nitrides, and each sputter source can be operated by different plasma modes independently, such as direct current (DC), pulsed direct current (PDC), and radio frequency (RF) with the ability to co-sputter with all four guns. The additional port at the center can be equipped with an ion beam source for ion beam assisted deposition, or ion beam cleaning, or an additional sputter gun which enables five gun co-sputtering operation. Process parameter windows can cover larger regimes than most production tool process parameters (Table 1).

Screen Shot 2017-04-28 at 1.03.58 PM

FIGURE 1 shows an example of a multi-target sputter chamber capable of controllably forming a variety of compounds in an array across a 300 mm substrate and an example substrate shown at right. The materials can also be deposited on a die-to-die basis (not shown) over a 300mm wafer test vehicle for direct device testing without the need for patterning. The effectiveness of the combinatorial screening can be increased by guiding the selection of material compositions using both semi-phenomenological and DFT-based modeling, as well as relating the experimental data to the results obtained from simulated annealing using ab-initio molecular dynamics and further DFT analysis of the simulated quasi-amorphous structures.

Deposition methodology

Two different methods can be used to deposit the combinatorial films of interest: site isolated spot and gradient approaches. For the site isolated spot approach, multiple numbers of spots were deposited on a substrate. Each individual spot represents a split condition from a design of experiment (DOE). Film composition can be controlled through the co-sputter of guns, which are equipped with targets consisting of different materials. Also, the process condition of each spot can be varied through the process parameter settings. All deposition conditions and procedures are fully automated.

In the gradient approach, non-uniform film in terms of composition and thickness is intentionally generated on top of a substrate by co-sputtering through an open large area aperture. A semi-empirical model is used for the control of non-uniformity. The modeling also helps in controlling the film composition throughout a target’s lifetime. In this approach, composition gradients and the thickness gradients can be generated by a single film deposition on a substrate. Theoretically, an infinite number of variations can be analyzed within a film, which is only limited by the spatial resolution of metrologies.

Characterization and device performance

Once films have been deposited via PVD, characterization can be carried out, including testing of physical, optical and electrical parameters. These can range from general film characteristics including composition, thickness and crystallinity, to device-specific electrical parameters such as leakage, threshold voltage, and On/ Off ratio.

Measuring and analyzing large numbers of data generated from HTE methodology can be time- consuming. By using the automated metrology tools and a unified database system, measurements and analysis steps can be expedited to limit bottlenecks and deliver data most efficiently. A multi-stage approach can also help to prioritize and focus experimental resources on the most promising candidates.

Screen Shot 2017-04-28 at 1.04.05 PM

HTE vs traditional methods

Key benefits of the HTE approach include the expedited learning cycle, cost reduction, and improved data quality. For semiconductor applications, a single 200mm or 300mm wafer can hold more than 30 splits, which can lead to a reduction in cycle of learning time (one device wafer instead of more than 30). Additionally, as all spots on a single wafer go through the same follow-up device fabrication steps together, data can be free from unexpected fluctuations of subsequent steps. Overall, the HTE approach can expedite the learning cycle by 5 ~ 10 times compared to single substrate based approach. A comparison of both HTE with traditional methods is summarized in Table 2.

Screen Shot 2017-04-28 at 1.04.12 PM

A case study in NVM

New materials for memory elements such as non-volatile memory (NVM) selectors must meet a wide range of performance parameters (FIGURE 3 shows a typical memory cell with the selector element called out), in order to reduce sneak currents and manage variability in memory arrays.

Screen Shot 2017-05-12 at 12.20.15 PM

 

Table 3 lists some of the key parameters desired in a memory selector material.

Of course, optimizing all of these parameters simultaneously in a single element or compound (and one that is practical for high volume memory manufacturing) is challenging. IMI’s HTE methodology enables rapid and simultaneous optimization of key trade-offs between performance, reliability and integration, in the quest for an ideal selector.

HTE for NVM selector materials

Use of a HTE methodology allows rapid screening of NVM selector candidate material compounds, compo- sitions and stacks. IMI has conducted multiple customer engagements in memory selector materials screening, and a typical experimental workflow is outlined in FIGURE 4, showing progression from PVD deposition, through physical and electrical characterizations of films and devices.

Screen Shot 2017-04-28 at 1.04.28 PM

This experimental process can be carried out multiple times, through subsequently more advanced stages on a fewer number of samples, as promising candidates are narrowed down and further optimized. FIGURE 5 shows a possible strategy for testing a series of candi- dates through three different stages. In the earlier stages, a wide range of options could be screened quickly, but the more extensive (and time consuming) characterization and analysis can be saved for later stages, when only the best performing candidates are already selected. This enables the best use of deposition and testing resources, leading to optimal results in an efficient timeframe.

Screen Shot 2017-04-28 at 1.04.36 PM Screen Shot 2017-04-28 at 1.04.41 PM

Fast and high-quality experimental results

IMI has extensive experience in working both on dynamic random access memory (DRAM) as well as NVM materials. In DRAM, the company has worked on development of dielectric, electrode and interface layer materials. IMI’s process engineers, materials scientists and electrical engineers work upfront with a customer on the design of experiments to ensure the delivery of rapid cycles of learning with the most efficient use of resources.

A typical customer project might range between a few months up to a year or more, encompassing hundreds or even thousands of different experiments. In NVM selectors alone, IMI has conducted:
• 2500+experiments on Metal Chalcogenides
• 2000+ experiments on MIEC
• 1000+experiments on Transition Metal Oxides

Conclusion

High throughput experimentation can offer rapid, high quality materials data when effectively applied to PVD memory selector development. However it does require an advanced platform, and a facility and team experienced in efficient deposition and testing of the materials and devices. Materials and device expertise is also helpful in managing and optimizing the experimental workflow for maximum efficiency and high quality data.

Researcher team led by Professor Takayuki Ohba at Tokyo Institute of Technology, ICE Cube Center, in collaboration with the WOW (Wafer-on-Wafer) Alliance(term 2), an Industry-academic collaborative research organization consisting of multiple semiconductor related companies aiming for practical applications of 3D IC technology, demonstrated the thermal resistance of the 3D stacked device can be reduced down to less than 1/3 relative to the conventional one bonded by bump(term 3) 3D IC in Through-Silicon-Via (TSV) wiring(term 4). Since semiconductor circuits are highly heat-generating bodies during operation, when heat is hard to be released, the temperature of the semiconductor results in highly rise, which leads to be a malfunction. The development of heat dissipation technology has been a big challenge.

To address this challenge, Ohba and colleagues analyzed thermal properties in 3D IC using finite element method (FEM)(term 5) and thermal network calculation method. The study identified three main factors of thermal resistance; the interconnection layers, dielectric layers and organic layers in the conventional bump type device. Contrary to the bump type, the thermal performance of a bumpless 3D IC was almost 150 times better than that of a conventional IC at the same TSV density. The researchers demonstrated to reduce the total thermal resistance to 0.46 Kcm2/W, whereas the conventional method is 1.54 Kcm2/W. This suggests that the bumpless enables lower temperature rise and three to four times further DRAM stacking.

This is a cross-sectional structure of micro bump and bumpless. Credit: Tokyo Institute of Technology

This is a cross-sectional structure of micro bump and bumpless. Credit: Tokyo Institute of Technology

Based on their demonstration experiments, the scientists will work toward practical use of large-capacity memory technology for mobile terminals and servers.

NXP Semiconductors N.V. (NASDAQ:NXPI) today announced a new laterally diffused metal oxide semiconductor (LDMOS) technology for RF power transistors designed for operation up to 65 volts (V). This extra-high voltage LDMOS process will give rise to a new generation of products: the MRFX series.

As RF becomes more pervasive in various industrial applications, NXP is providing RF power engineers with a means to reduce design cycle time:

  • More power – Higher voltage enables higher output power, which helps decrease the number of transistors to combine, simplifying power amplifiers complexity and reducing their size.
  • Faster development time – With higher voltage, the output power can be increased while retaining a reasonable output impedance. This simplifies the matching to 50 ohms, especially in wideband applications. Faster matching dramatically speeds up the development time.
  • Design reuse – This impedance benefit also ensures pin-to-pin compatibility with current 50 V LDMOS transistors, making it possible for RF designers to reuse existing printed circuit board (PCB) designs for even shorter time to market.
  • Manageable current level – A higher voltage lowers the current in the system, limiting the stresses on DC power supplies and reducing magnetic radiation.
  • Wide safety margin – The NXP 65 V LDMOS technology has a breakdown voltage of 182 V, which improves reliability and enables higher efficiency architectures.

The first product in the MRFX series is the MRFX1K80, the industry’s most powerful continuous wave (CW) RF transistor. It is designed to deliver 1800 watts (W) CW at 65 V for applications from 1 to 470 megahertz (MHz) and is capable of handling 65:1 voltage standing wave ratio (VSWR).

“The drop-in compatibility between our 1250, 1500 and our new 1800 W transistors enables our customers to create a single scalable platform for multiple end products,” said Pierre Piel, senior director and general manager for multi-market RF power at NXP. “With this new generation, we help our customers deliver on their commitment of higher performing, more rugged products in a shorter amount of time.”

The MRFX1K80 is targeted for industrial, scientific and medical (ISM) applications such as laser generation, plasma etching, magnetic-resonance imaging (MRI), skin treatment and diathermy, as well as particle accelerators and other scientific applications. The MRFX1K80 is also designed for radio and very high frequency (VHF) TV broadcast transmitters. Industrial heating, welding, curing or drying machines currently using vacuum tubes will also benefit from the higher level of control that solid state enables.

ON Semiconductor (Nasdaq: ON) announced it is expanding its portfolio of Interline Transfer Electron Multiplication CCD (IT-EMCCD) image sensors with new options that target not only low-light industrial applications such as medical and scientific imaging, but also commercial and military applications for high-end surveillance.

The new 4 megapixel KAE-04471 uses larger 7.4 micron pixels than those found in existing IT-EMCCD devices, doubling the light gathering capability of the new device and improving image quality under light starved conditions. The KAE-04471 is pin and package compatible with the existing 8 megapixel KAE-08151, allowing camera manufacturers to easily leverage existing camera designs to support the new device.

The new KAE-02152 shares the same 1080p resolution and 2/3” optical format as the existing KAE-02150, but incorporates an enhanced pixel design that increases sensitivity in near-infrared (NIR) wavelengths – an improvement that can be critical in applications such as surveillance, microscopy and ophthalmology. The KAE-02152 is fully drop-in compatible with the existing KAE-02150, and both devices are available in packages that incorporate an integrated thermoelectric cooler, simplifying the work required by camera manufacturers to develop a cooled camera design.

“As the need for sub-lux imaging solutions expands in surveillance, medical, scientific and defense markets, customers are looking for new options that provide the critical performance required in these applications,” said Herb Erhardt, Vice President and General Manager, Industrial Solutions Division, Image Sensor Group at ON Semiconductor. “The new products allow customers to choose from a variety of resolutions, pixel sizes, sensitivities, color configurations and packaging options in our IT-EMCCD portfolio to meet their low-light imaging needs.”

Interline Transfer EMCCD devices combine two established imaging technologies with a unique output structure to enable a new class of low-noise, high-dynamic range imaging. While Interline Transfer CCDs provide excellent image quality and uniformity with a highly efficient electronic shutter, this technology is not always ideal for very low-light imaging. And while EMCCD image sensors excel under low-light conditions, they historically have only been available as low resolution devices with limited dynamic range. Combining these technologies allows the low-noise architecture of EMCCD to be extended to multi-megapixel resolutions, and an innovative output design allows both standard CCD (normal-gain) and EMCCD (high-gain) outputs to be utilized for a single image capture – extending dynamic range and scene detection from sunlight to starlight in a single image.

Engineering grade versions of the KAE-04471 are now available, with production versions available in 2Q17. Engineering grade versions of the KAE-02152 in both a standard package as well as a package incorporating an integrated thermoelectric cooler are also available, with production versions of both configurations available in 3Q17. All IT-EMCCD devices ship in ceramic micro-PGA packages, and are available in both Monochrome and Bayer Color configurations.

Evaluation kits for devices in the IT-EMCCD portfolio allow the full performance of this technology to be examined and reviewed under real-world conditions. Customers can purchase an evaluation kit, or inquire about an on-site demonstration of IT-EMCCD devices, by contacting their local ON Semiconductor sales representative.

A recent study, affiliated with UNIST has created a three-dimensional, tactile sensor that could detect wide pressure ranges from human body weight to a finger touch. This new sensor with transparent features is capable of generating an electrical signal based on the sensed touch actions, also, consumes far less electricity than conventional pressure sensors.

The breakthrough comes from a research, conducted by Professor Jang-Ung Park of Materials Science and Engineering and his research team at UNIST. In the study, the research team presented a novel method of fabricating a transistor-type active-matrix pressure sensor using foldable substrates and air-dielectric layers.

This image shows the transistor-type active-matrix 3-D pressure sensors with air-dielectric layers. Credit: UNIST

This image shows the transistor-type active-matrix 3-D pressure sensors with air-dielectric layers. Credit: UNIST

Today, most transistors are created with silicon channel and silicon oxide-based dielectrics. However, these transistors have been found to be either lacking transparency or inflexible, which may hinder their utility in fabricating highly-integrated pressure sensor arrays and transparent pressure sensors.

In this regard, Professor Park’s team decided to use highly-conductive and transparent graphene transistors with air-dielectric layers. The sensor can detect different types of touch-including swiping and tapping..

“Using air as the dielectric layer in graphene field-effect transistors (FETs) can significantly improve transistor performance due to the clean interface between graphene channel and air,” says Professor Park. “The thickness of the air-dielectric layers is determined by the applied pressure. With that technology, it would be possible to detect pressure changes far more effectively.”

A convantional touch panel, which may be included in a display device, reacts to the static electrical when pressure is applied to the monitor screen. With this method, the position on screen contacted by a finger, stylus, or other object can be easily detected using changes in pressure, but can not provide the intensity of pressure.

The research team placed graphene channel, metal nanowire electrodes, as well as an elastic body capable of trapping air on one side of the foldable substrate. Then they covered the other side of the substrate, like a lid and kept the air. In this transistor, the force pressing the elastic body is transferred to the air-dielectric layer and alters its thickness. Such changes in the thickness of the air-dielectric layer is converted into an electrical signal and transmitted via metal nanowires and the graphene channel, expressing both the position and the intensity of the pressure.

This is regarded as a promising technology as it enables the successful implementation of active-matrix pressure sensors. Moreover, when compared with the passive-matrix type, it consumes less power and has a faster response time.

It is possible to send and receive signals only by flowing electricity to the place where pressure is generated. The change in the thickness of the air dielectric layer is converted into an electrical signal to represent the position and intensity of the pressure. In addition, since all the substrates, channels, and electrode materials used in this process are all transparent, they can also be manufactured with invisible pressure sensors.

“This sensor is capable of simultaneously measuring anything from lower pressure (less than 10 kPa), such as gentle tapping to high pressure (above 2 MPa), such as human body weight,” says Sangyoon Ji (Combined M.S./Ph.D. student of Materials Science and Engineering), the first co-author of the study. “It can be also applied to 3D touchscreen panels or smart running shoes that can analyze life patterns of people by measuring their weight distribution.”

“This study not only solves the limitations of conventional pressure sensors, but also suggests the possibility to apply them to various fields by combining pressure sensor with other electronic devices such as display.” says Professor Park.

Today, Transphorm Inc. announced that its second generation, JEDEC-qualified high voltage gallium nitride (GaN) technology is now the industry’s first GaN solution to earn automotive qualification—having passed the Automotive Electronics Council’s AEC-Q101 stress tests for automotive-grade discrete semiconductors.

Transphorm’s automotive GaN FET, the TPH3205WSBQA, offers an on-resistance of 49 milliOhms (mΩ) in an industry standard TO-247 package. The part initially targets on-board charger (OBC) and DC to DC systems for plug-in hybrid electric vehicles (PHEVs) and battery electric vehicles (BEV). Today, OBCs are uni-directional (AC to DC) using standard boost topologies. However, being that GaN FETs are bi-directional by nature, they become the perfect fit for the bridgeless totem-pole power factor correction (PFC) topology. Meaning, a bi-directional OBC can then be designed with GaN to reduce the number of silicon (Si) devices, weight and overall system cost of today’s solution.

“With the electrification of the automobile, the industry faces new system size, weight, performance, and cost challenges that can be addressed by GaN,” said Philip Zuk, Senior Director of Technical Marketing at Transphorm. “However, supplying this market means devices must meet the highest possible standards for Quality and Reliability, those set by the AEC. At Transphorm, we have a culture of Quality and Reliability. And, are proud to be leading the industry into the new era of in-vehicle power electronics.”

The automotive market is one of the fastest growing segments for all power semiconductors, with IHS Markit forecasting a $3 billion revenue by 2022. Due to its inherent attributes, Transphorm’s GaN can support a large portion of the market. When compared to incumbent tech such as superjunction MOSFETs, IGBTs and Silicon Carbide (SiC), those attributes include:

  • Up to 40 percent greater power density
  • Increased efficiency
  • Lower thermal budget
  • Reduced system weight
  • Up to 20 percent decrease in overall system cost
  • High volume manufacturing with 6-inch GaN on Silicon

As a result, Transphorm’s GaN can be used in other high voltage DC to DC automotive systems including air conditioning, heating, oil pumps and power steering.

In electronics, the race for smaller is huge.

Physicists at the University of Cincinnati are working to harness the power of nanowires, microscopic wires that have the potential to improve solar cells or revolutionize fiber optics.

University of Cincinnati physicist Hans-Peter Wagner is exploring nanowire semiconductors to harness the power of light at the nano level. Credit: Andrew Higley/UC Creative Services

University of Cincinnati physicist Hans-Peter Wagner is exploring nanowire semiconductors to harness the power of light at the nano level. Credit: Andrew Higley/UC Creative Services

Nanotechnology has the potential to solve the bottleneck that occurs in storing or retrieving digital data – or could store data in a completely new way. UC professors and their graduate students presented their research at the March 13 conference of the American Physical Society in New Orleans, Louisiana.

Hans-Peter Wagner, associate professor of physics, and doctoral student Fatemesadat Mohammadi are looking at ways to transmit data with the speed of fiber optics but at a significantly smaller scale.

Wagner and lead author Mohammadi are studying this field, called plasmonics, with researchers from three other universities. For the novel experiment, they built nanowire semiconductors with organic material, fired laser pulses at the sample and measured the way light traveled across the metal; technically, the excitations of plasmon waves.

“So, if we succeed in getting a better understanding about the coupling between the excitations in semiconductor nanowires and metal films, it could open up a lot of new perspectives,” Wagner said.

The successful harnessing of this phenomenon — called plasmon waveguiding — could allow researchers to transmit data with light at the nano level.

Universities around the world are studying nanowires, which have ubiquitous applications from biomedical sensors to light-emitting diodes or LEDs. Four UC papers on the topic are among more than 150 others by nanowire researchers around the world to be presented at the March conference.

“You’re trying to optimize the physical structure on something approaching the atomic scale. You can make very high efficiency devices like lasers,” said Leigh Smith, head of UC’s Department of Physics. Smith and UC Physics Professor Howard Jackson also presented papers on nanowires at the conference. Virtually everyone benefits from this line of research, even if the quantum mechanics underlying the latest biosensors exceed a casual understanding. For example, home pregnancy tests use gold nanoparticles – the indicator that turns color. People use technologies all the time that they don’t understand,” Smith said.

Gordon Moore, co-founder of Intel Corp., observed that the number of transistors used in a microchip has roughly doubled every two years since the 1970s. This phenomenon, now called Moore’s Law suggests that computer processing power improves at a predictable rate.

Some computer scientists predicted the demise of Moore’s Law was inevitable with the advent of microprocessors. But nanotechnology is extending that concept’s lifespan, said Brian Markwalter, senior vice president of research and technology for the Consumer Technology Association. His trade group represents 2,200 members in the $287 billion U.S. tech industry.

“It’s not a race to be small just to be the smallest. There’s a progression of being able to do more on smaller chips. The effect for consumers is that every year they get better and better products for the same price or less,” he said.

Nanotechnology is opening a universe of new possibilities, Markwalter said.

“It’s almost magical. They get better, faster, cheaper and use less power,” he said.

Markwalter said UC professor Wagner’s research is exciting because it shows promise in using optical switches to address a bottleneck in data transmission that occurs whenever you try to store or remove data.

“It’s really a breakthrough area to merge the semiconductor world and the optical world,” Markwalter said. “[Wagner’s] working at the intersection of fiber optics and photonics.”

But even nanotechnology has its limits, Smith said.

“We’re running toward the limits of what’s physically possible with present technologies,” Smith said. “The challenges are pretty immense. In 10 or 20 years there has to be a fundamental paradigm shift in how we make structures. If we don’t we’ll be caught at the same place we are now.”

How one UC experiment works:

UC graduate student Fatemesadat Mohammadi and Associate Physics Professor Hans-Peter Wagner fire laser pulses at semiconductor nanowires to excite electrons (called excitons) that potentially serve as an energy pump to guide plasmon waves over a coated metal film just a few nanometers thick without losing power, a nettlesome physical property called resistivity

They measure the resulting luminescence of the nanowire to observe how light couples to the metal film. By sending light over a metal film, a process called plasmonic waveguiding, researchers one day could transmit data with light at the nano level.

“The luminescence is our interest. So we coat them and see: How does the photoluminescence characteristic change?” Mohammadi said.

To make the semiconductor, they use a technique called high-vacuum organic molecular beam deposition (pictured above) to spread organic and metal layers on gallium-nitride nanorods.

The use of organic film is unique to the UC experiment, Wagner said. The film works as a spacer to control the energy flow between excitons in the nanowire and the oscillation of metal electrons called plasmons.

The organic material has the added benefit of also containing excitons that, arranged properly, could support the energy flow in a semiconductor, he said.

Coating the nanorods with gold significantly shortens the lifetime of the exciton emission resulting in what’s called a quenched photoluminescence. But by using organic spacers between the nanorod and the gold film, the researchers are able to extend the emission lifetime to nearly the equivalent of nanorods without a coating.

Once the gold-coated sample is prepared, they take it to an adjacent lab room and subject it to pulses of laser light.

Mohammadi said it took days of painstaking work to arrange the small city of mirrors and beam splitters bolted at precise angles to a workbench for the experiment (pictured above left).

The reactions in the nanowire take just 10 picoseconds (which is a trillionth of a second.) And the laser pulses are faster still — 20 femtoseconds (a figure that has 15 zeros following it or a quadrillionth of a second.)

The UC project used a gold coating so that experiments could be replicated at a later date without risk of oxidation. But traditional coatings such as silver, Mohammadi said, hold even more promise.