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Synopsys, Inc. (Nasdaq:  SNPS) today announced that TSMC has certified the complete suite of products in the Synopsys Galaxy Design Platform for the most current version of 12-nanometer (nm) FinFET process technology. This 12nm certification brings with it the broad body of design collateral, including routing rules, physical verification runsets, signoff-accurate extraction technology files, SPICE correlated timing and interoperable process design kits (iPDKs) for this latest FinFET process. Synopsys Custom Compiler design solution support is enabled through an iPDK.

To accelerate access to this power-efficient, high-density process, IC Compiler II place-and-route system has been enabled to support new standard cell architectures seamlessly co-existing with 16FFC intellectual property (IP). Recent collaborations have resulted in enhancements to IC Compiler II’s core placement and legalization engines ensuring maximum utilization while minimizing placement fragmentation and cell displacement. The 12nm ready iPDK enables designers to use Custom Compiler’s layout assistant features to shorten time in creating FinFET layouts.

“This power-efficient, high-density node offers a broad set of opportunities to our customers, enabling them to deliver highly differentiated products,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Our ongoing collaboration with Synopsys is helping expedite designer access to 12-nm process technology.”

“The long-standing collaboration between Synopsys and TSMC continues to be key in bringing accelerated access to new process technology nodes,” said Bijan Kiani, vice president of product marketing for the Design Group at Synopsys. “With the Galaxy Design Platform certified for 12nm readiness, our mutual customers are enabled to speed up development and deployment to accelerate their time-to-market.”

A silicon optical switch newly developed at Sandia National Laboratories is the first to transmit up to 10 gigabits per second of data at temperatures just a few degrees above absolute zero. The device could enable data transmission for next-generation superconducting computers that store and process data at cryogenic temperatures. Although these supercomputers are still experimental, they could potentially offer computing speeds ten times faster than today’s computers while significantly decreasing power usage.

The fact that the switch operates at a range of temperatures, offers fast data transmission and requires little power could also make it useful for transmitting data from instruments used in space, where power is limited and temperatures vary widely.

“Making electrical connections to systems operating at very cold temperatures is very challenging, but optics can offer a solution,” said lead researcher Michael Gehl, Sandia National Laboratories, New Mexico. “Our tiny switch allows data to be transmitted out of the cold environment using light traveling through an optical fiber, rather than electricity.”

In The Optical Society’s journal for high impact research, Optica, Gehl and his colleagues describe their new silicon micro-disk modulator and show that it can transmit data in environments as cold as 4.8 Kelvin. The device was fabricated with standard techniques used to make CMOS computer chips, which means it can be easily integrated onto chips containing electronic components.

“This is one of the first examples of an active silicon optical device operating at such a low temperature,” said Gehl. “Our device could potentially revolutionize technologies that are limited by how fast you can send information in and out of a cold environment electrically.”

Optics excels at low temperatures

For low-temperature applications, optical methods provide several benefits over electrical data transmission. Because electrical wires conduct heat, they often introduce heat into a system that needs to stay cold. Optical fibers, on the other hand, transmit almost no heat. Also, a single optical fiber can transmit more data at faster rates than an electrical wire, meaning that one fiber can do the job of many electrical connections.

The micro-disk modulator requires very little power to operate — around 1000 times less power than today’s commercially available electro-optical switches — which also helps reduce the heat the device contributes to the cold environment.

To make the new device, the researchers fabricated a small silicon waveguide (used to transmit light waves) next to a silicon micro-disk only 3.5 microns in diameter. Light coming through the waveguide moves into the micro-disk and travels around the disk rather than passing straight through the waveguide. Adding impurities to the silicon micro-disk creates an electrical junction to which a voltage can be applied. The voltage changes the material’s properties in a way that stops the light from moving into the disk and allows it to instead pass through the waveguide. This means that the light signal turns off and on as the voltage switches on and off, providing a way to turn the ones and zeroes that make up electrical data into an optical signal.

Although other research groups have designed similar devices, Gehl and his colleagues are the first to optimize the amount of impurities used and the exact placement of those impurities to allow the micro-disk modulator to operate at low temperatures. Their approach could be used to make other electro-optical devices that work at low temperatures.

Low error rate

To test the micro-disk modulator, the researchers placed it inside a cryostat — a small vacuum chamber that can cool what’s inside to very low temperatures. The micro-disk modulator converted an electrical signal sent into the cryostat to an optical signal. The researchers then examined the optical signal coming out of the cryostat to measure how well it matched the incoming electrical data.

The researchers operated their device at room temperature, 100 Kelvin and 4.8 Kelvin with various data rates up to 10 gigabits per second. Although they observed a slight increase in errors at the highest data rate and lowest temperature, the error rate was still low enough for the device to be useful for transmitting data.

This work builds on years of effort to develop silicon photonic devices for optical communication and high performance computing applications, led by the Applied Photonics Microsystems group at Sandia. As a next step, the researchers want to demonstrate that their device works with data generated inside the low temperature environment, rather than only electrical signals coming from outside the cryostat. They are also continuing to optimize the performance of the device.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced several new capabilities resulting from its close collaboration with TSMC to further 7nm FinFET design innovation for mobile and high-performance computing (HPC) platforms. The Cadence digital, signoff and custom/analog tools have achieved certification for v1.0 Design Rule Manual (DRM) and SPICE certification for the TSMC 7nm process. Cadence has also delivered solutions for a new process design kit (PDK) enabling optimal power, performance and area (PPA) when designing with TSMC’s 7nm process. In addition, the Cadence 7nm Custom Design Reference Flow (CDRF) and the library characterization flow have been enhanced, and its 7nm DDR4 PHY IP is in deployment with customers.

7nm Tool Certification Cadence provides a fully integrated digital flow from implementation to final signoff that has been certified by TSMC for the 7nm process. The digital flow includes the Innovus Implementation System, Quantus QRC Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, Physical Verification System (PVS) and Layout-Dependent Effect (LDE) Electrical Analyzer.

Support for TSMC’s 7nm HPC platform includes via-pillar modeling in the Genus Synthesis Solution and full via-pillar-capable implementation and signoff environments. Additionally, clock-mesh handling and bus-routing capabilities in the tools support the high-performance library to deliver better PPA and mitigated electromigration (EM). These capabilities enable customers to successfully design advanced-node systems while reducing iterations and achieving cost and performance objectives.

The certified custom/analog tools include the Spectre Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre Classic Simulator, Virtuoso Layout Suite, Virtuoso Schematic Editor, and Virtuoso Analog Design Environment (ADE). Enhancements made for the 7nm process include advanced device snapping and an accelerated custom placement and routing flow that enables customers to improve productivity and meet power, multiple patterning, density and EM requirements.

7nm CDRF Delivery Cadence delivered an enhanced Custom Design Reference Flow (CDRF) to address 7nm custom and mixed-signal design challenges. The CDRF incorporates advanced methodologies and features that provide productivity improvements through a series of in-depth “how-to” circuit design, layout implementation, and signoff and verification modules. The circuit design module covers “how-to” topics, such as capturing schematics with device arrays using module generator (ModGen) constraints and the TSMC PDK, functional verification, yield estimation and optimization, and the latest reliability analyses. For signoff verification, the physical verification modules highlight design rule and layout-versus-schematic (LVS) checking, signoff parasitic extraction, and electromigration and IR drop (EM/IR) signoff checks.

The layout implementation module includes connectivity and constraint-driven layout for FinFET device placement, enabling designers to avoid design rule violations and address layout-dependent effects (LDEs). The routing module offers a color-aware flow and an innovative track-pattern system that reduces design time, mitigates parasitics and helps designers avoid EM issues.

7nm Library Characterization Tool Flow Delivery In addition to tool certification, the Cadence Virtuoso Liberate Characterization Solution and the Virtuoso Variety Statistical Characterization Solution have been validated to deliver Liberty libraries for the TSMC 7nm process including advanced timing, noise and power models. The solutions utilized innovative methods to characterize the Liberty Variation Format (LVF), enabling process variation signoff and the ability to create EM models enabling signal EM optimizations and signoff.

7nm IP Collaboration As a leader in DDR controller and PHY IP, Cadence has deployed its DDR4 PHY and LPDDR4 PHY in multiple generations of TSMC process technologies, ranging from 28HPM/28HPC/28HPC+ to 16FF+/16FFC nodes. Through close collaborations with TSMC and customers, Cadence began developing IP on the 7nm process last year. Cadence has taped out its flagship DDR4 PHY using the 7nm process node in Q4 2016, and key customers have integrated the 7nm DDR PHYs into their enterprise-class SoCs.

“TSMC’s latest process advancements combined with enhancements to Cadence tools and IP offer our mutual customers optimal solutions for advanced-node designs,” said Dr. Anirudh Devgan, executive vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “This certification and the v1.0 process maturity milestone represent our readiness to meet the production needs of our most innovative customers using the 7nm process.”

“The availability of new v1.0 design rules and PDK indicates that we’ve reached a new pinnacle with 7nm production designs,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “We’ve collaborated closely with Cadence to certify its tools and deliver IP innovations for 7nm designs, which enable our customers to achieve their PPA objectives with mobile and HPC designs.”

“ARM has collaborated closely with Cadence and TSMC to enable a 7nm design flow for our joint customers,” said Monika Biddulph, general manager of the Systems and Software Group, ARM. “This flow is enabling the development of platforms for high-end mobile and high-performance computing applications.”

Cadence Design Systems, Inc. (NASDAQ:  CDNS) today announced new optimization capabilities within its holistic, integrated design flow for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology. The integrated flow provides design and analysis capabilities and modeling of cross-die interactions for mobile and IoT applications.

The Cadence tools in the enhanced flow include the OrbitIO interconnect designer, System-in-Package (SiP) Layout, Quantus QRC Extraction Solution, Sigrity XtractIM technology, Tempus Timing Signoff Solution, Physical Verification System (PVS), Voltus-Sigrity Package Analysis, Sigrity PowerDC technology and Sigrity PowerSI 3D-EM Extraction Option. With the new flow, system-on-chip (SoC) designers can:

  • Quickly generate netlists among the multiple dies and InFO package in the context of the full system within a single-canvas multi-fabric environment: The OrbitIO interconnect designer efficiently handles multi-die integrations with TSMC InFO technologies to generate top-level netlists that can be directly used for subsequent design steps such as detailed electrical and timing analysis.
  • Generate Standard Parasitic Exchange Format (SPEF) directly from the package design database, which greatly eases timing signoff: Rather than using a traditional methodology that requires converting the package design database of an InFO design to an IC design database to generate SPEF, Sigrity XtractIM technology automatically generates SPEF for heterogeneous InFO systems, which accelerates the timing signoff process and speeds time to market.

“We’ve continued to see strong demand from mobile and IoT customers who want to deploy systems based on TSMC’s InFO technology,” said Steve Durrill, senior product engineering group director at Cadence. “By working closely with TSMC, we are enabling our mutual customers to shorten design and verification cycle times so they can deliver reliable, innovative SoCs to market faster.”

“The Cadence flow developed specifically for our InFO technology is an enabler for customers who need to increase bandwidth within small form factors,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “The integrated full-flow includes a comprehensive set of Cadence digital, signoff and custom IC technologies that address this market need, and our collaboration is helping customers to efficiently achieve their design goals.”

NXP Semiconductors N.V. (NASDAQ:NXPI) today announced the world’s smallest single-chip SoC solution – the MC9S08SUx microcontroller (MCU) family – with an integrated 18V-to-5V LDO and MOSFET pre-driver that delivers ultra-high-voltage solution for drones, robots, power tools, DC fan, healthcare and other low-end brushless DC electric motor control (BLDC) applications. Extending the company’s S08 family of MCUs, the robust 8-bit MC9S08SUx microcontroller family offers 4.5V~18V supply voltage range with lower bill of materials (BOM) cost and tighter integration for higher performance and reliability. The new SoC units address the growing demand to replace multiple device solutions with a single MCU to reduce cost and system size, while simplifying integration and layout for space-constrained use cases.

“The market trend is pointing towards integrated solutions that save system size and cost, and NXP is leading the industry as the only provider to offer a single-chip offering with integrated microcontroller and MOSFET pre-driver in a 4x4x0.65mm form factor, which also makes it possible to cut the printed circuit board size in half,” said Geoff Lees, senior vice president and general manager of the microcontroller business line at NXP. “Historically, several devices were needed to address the needs of BLDC motor control applications, which can be expensive and large in size; our latest addition to the S08 MCU family underscores our dedication to solving unique challenges by introducing new microcontrollers for the broad market.”

Based on the HCS08 core, the MC9S08SUx leverages the enhanced S08L central processor unit with three-phase MOSFET pre-drivers to deliver all-in-one unit for 4.5V-18V motor control applications. The single-chip MC9S08SUx MCU removes the need for Low Drop Out (LDO) voltage regulator(s), operational amplifiers, and pre-drivers for a streamlined, cost-effective solution. Additionally, NXP has integrated virtually all of the necessary features in BLDC motor control, including zero crossing point detection, pulse width measurement, over voltage protection and over current protection, enabling developers to simply configure registers and easily use the functions in applications. The MC9S08SUx family also includes amplifiers for current measurement and supports three high-side PMOSes as well as three low-side NMOSes.

NXP’s S08 microcontrollers, including the new MC9S08SUx family, are supported by CodeWarrior IDE. FreeMASTER support is offered as run-time debugging tool. In addition, IAR Embedded Workbench supports the NXP S08 MCU portfolio, offering a single toolbox complete with configuration files, code examples and project templates. IAR Embedded Workbench support for the MC9S08SUx MCU family will be available March 2017.

“The leading optimization technology in IAR Embedded Workbench helps developers to maximize performance and minimize power consumption for applications based on the new MC9S08SUx MCU family from NXP,” said Jan Nyrén, Product Manager, IAR Systems.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled the IQ Aligner NT–its latest and most advanced automated mask alignment system for high-volume advanced packaging applications. Featuring high-intensity and high-uniformity exposure optics, new wafer handling hardware, full 200-mm and 300-mm wafer coverage that enables global multi-point alignment, and optimized tool software, the new IQ Aligner NT provides a 2X increase in throughput and 2X improvement in alignment accuracy over EVG’s previous-generation IQ Aligner. The system surpasses the most demanding requirements for wafer bump and other back-end lithography applications while providing up to 30 percent lower cost of ownership compared to competing systems.

The IQ Aligner NT from EV Group is the industry's most advanced automated mask alignment system for advanced packaging applications. It provides a 2X increase in throughput and 2X improvement in alignment accuracy over the previous-generation system, as well as up to 30 percent lower cost of ownership compared to competing systems.

The IQ Aligner NT from EV Group is the industry’s most advanced automated mask alignment system for advanced packaging applications. It provides a 2X increase in throughput and 2X improvement in alignment accuracy over the previous-generation system, as well as up to 30 percent lower cost of ownership compared to competing systems.

The IQ Aligner NT is ideally suited for a variety of advanced packaging types, including Wafer-level Chip Scale Packaging (WLCSP), Fan-out Wafer Level Packaging (FOWLP), 3D-IC/Through-silicon Via (TSV), 2.5D Interposers, and Flip Chip.

New lithography capabilities needed

Semiconductor advanced packaging is continually evolving to enable new types of devices with increasing functionality at a lower cost per function. As a result, new developments in lithography are now required to address the unique needs of the advanced packaging market. These needs include:
Extremely tight alignment accuracy
Managing wafer warpage and addressing dimensional mismatch of wafer and mask layout to achieve optimized overlay

Sufficient exposure of the thicker resists and dielectric layers found in back-end processing
Higher resolution to address shrinking bumps and interconnects due to device scaling
At the same time, all of these needs must be met in a highly cost-effective and high-productivity lithography tool platform.

“Leveraging more than three decades of experience in lithography, EVG has pushed the envelope of mask alignment technology to new boundaries with our new IQ Aligner NT,” stated Paul Lindner, executive technology director at EV Group. “This latest addition to our suite of lithography solutions provides unprecedented levels of throughput, accuracy and cost-of-ownership performance, which in turn has opened up a variety of new market opportunities for EVG. We look forward to working closely with customers to meet their critical advanced packaging lithography needs.”

The IQ Aligner NT incorporates a variety of improvements to achieve industry-leading mask alignment performance for advanced packaging lithography:

High-power optics provides a 3X increase in illumination intensity compared to EVG’s previous-generation IQ Aligner, making it ideal for exposing thick resists and other films associated with processing bumps, pillars and other high-topography features:

  • Full clearfield mask movement over 300-mm substrates, which offers the highest process compatibility and flexibility in dark field mask alignment and pattern positioning
  • Dual substrate size concept eliminates the need for any retooling effort, providing a quick and easy on-the-fly bridge tool for two different wafer sizes
  • Fully automated as well as semi-automated/manual wafer loading operation is supported for maximum flexibility
  • Latest EVG CIMFramework system software based on the latest fab software standards and protocols
  • Unsurpassed accuracy and productivity performance

Combining optical and mechanical engineering with optimized tool software, the IQ Aligner NT provides a two-fold increase in throughput (>200 wph for first print, >160 wph for top side alignment) as well as a two-fold improvement in alignment accuracy (250nm 3-sigma). As a result of the tighter alignment specification, customers can also realize improved yields for high-end and high-bandwidth packaging products.

Leti, a research institute of CEA Tech, today announced it has developed a shield that can help protect electronic devices against physical attacks from the chips’ backside. Integrated circuits (ICs) embedded in connected objects, smart cards or other systems dealing with sensitive data would benefit from this technology, which brings more privacy, safety and security to the users.

Physical attacks may occur when hackers have access to the device and can exploit weaknesses of the embedded IC to steal sensitive information or to corrupt its functioning. The shield proposed by Leti protects chips from invasive and semi-invasive attacks by infrared lasers, focused ion beams (FIB), chemicals and other means.

The shield consists of a metal serpentine sandwiched between two polymers, one being opaque to infrared and serving as a physical barrier against FIB attacks. It also hides the design of the chips’ serpentine and combines with the polymer underneath to detect chemical attacks. Altering the serpentine typically triggers the IC to delete sensitive data.

The shield is fabricated using standard packaging processes, which demonstrates that hardware cybersecurity can be implemented at low additional cost. Leti’s research results will be presented at this week’s Device Packaging Conference inFountain Hills, Arizona, in a paper entitled “Backside Shield against Physical Attacks for Secure ICs”.

“Implementation of multiple hardware and software countermeasures is making integrated circuits more secure, but the backside of a chip is still considered to be vulnerable to physical attacks,” said Alain Merle, Leti’s Security Strategic Marketing Manager. “Our team designed, fabricated and tested a novel protection structure combining several elements that will trigger an alert if hackers use the backside of a chip to access the active parts of the IC.”

At the CS International Conference (Brussels, March 7-8), imec will present promising device results with a InGaAs-only TFET (tunnel field-effect transistor). Achieving a sub-60 mV/decade sub-threshold swing at room temperature, these devices are promising candidates to replace MOSFET transistors in future chip generations for ultralow-power applications operating on ultralow supply voltages.

TFETs exploit a different mechanism to inject carriers than MOSFETs, the most dominant transistor type today. While MOSFETs introduce carriers from the source into the conducting channel by thermal injection, a TFET works through band-to-band tunneling (BTBT). With that, they promise sub-threshold swings smaller than 60mV/dec, which is below the limit of what is possible with MOSFETs. This would allow operating them at ultralow supply voltages (below 0.5V).

The device developed at imec is an InGaAs homojunction TFET. It shows a minimum sub-threshold swing of 54mV/dec at 100pA/mm. The sub-threshold swing remains sub-60mV/dec over 1.5 orders of magnitude of current at room temperature. The EOT of the devices is 0.8nm, which plays a major role in achieving the desired sub-60 mV/dec performance.

“We have entered an era where new chip technologies require making trade-offs between power, performance, cost and area. And these trade-offs will be considered separately for different application domains,” says Nadine Collaert, distinguished member of technical staff at imec. “TFETs will most probably find their place in the ultralow-power segment. Many applications in the future require transistors to work at low power and low voltage, such as the many Internet of Things applications.

At CS International, imec’s expert Nadine Collaert will discuss the progress made and challenges ahead in processing TFETs, focusing on the materials and integration, but also on the impact of using TFETs in electronic circuits.

Dream Chip Technologies announced today the presentation of the industry`s first 22nm FD-SOI silicon for a new ADAS System-on-Chip (SoC) for automotive computer vision applications at the Mobile World Congress in Barcelona. The SoC was created in close cooperation with ARM, Arteris, Cadence, GLOBALFOUNDRIES, and INVECAS as part of the European Commission’s ENIAC THINGS2DO reference development platform.

The SoC offers high performance image acquisition and processing capabilities and supports convolutional neural network (CNN) vision workloads to meet the demand for complex automotive object detection and processing.  This ADAS SoC is highly optimized for high-end computer vision performance at a very low-power consumption to enable autonomous driving in production and is capable to support ADAS functions like road-sign recognition, lane departure warning, driver distraction warning, blind spot detection, surround vision, park assist, pedestrian detection, cruise control and emergency braking.”

The design incorporates Dream Chip Technologies’ image signal processing pipeline in conjunction with Cadence Tensilica Vision P6 DSPs and a quad-core cluster of ARM® Cortex®-A53 processors. In addition, a lock-step pair of Cortex-R5 processors provides ISO 26262 compliant functional safety and the SoC is interconnected with an Arteris FlexNoC network-on-chip. The SoC uses multiple IPs such as foundation IPs, LPDDR4, PLL, Thermal Sensor and Process Monitor, from INVECAS. Cadence’s LPDDR4 controller and INVECAS’ LPDDR4 PHY IP provide two LPDDR4 3200 high bandwidth memory interfaces.

Dr. Jens Benndorf, Managing Director and Co-Founder of DCT said: “It was a unique experience to create and coordinate such a powerful team and successfully lead the consortium to two tape-outs. In this project, we have delivered silicon using a brand new process technology for the automotive industry.” He adds: “The project not only shows the strength of the European semiconductor industry, but also an ability to collaborate efficiently to provide technology needed urgently by the industry to power advanced automated driving solutions.”

Dream Chip Technologies has designed many highly complex SoCs for customers worldwide and was selected as the design service lead for this THINGS2DO project. The project has created a camera-based ADAS reference platform which benefits automotive companies through advanced technology and by shortening design cycles and time-to-market for automotive innovation. The SoC is fabricated on GF’s 22FDX® semiconductor process at the foundry’s Fab 1 facility in Dresden, Germany.

The new ADAS platform is targeted at automotive Tier-1s with a need for cost, performance and power-optimized SoCs for a range of ADAS applications and with potential for customization.

The choice of a quad-core Cortex-A53 processor configuration is a popular choice for computer vision applications to manage automotive vision applications. More advanced autonomous driving systems can also be enabled with this level of computer vision capability, including those using multiple smart cameras.

“This project provides a boost for European chip designers focused on solving some of the automotive world’s most complex problems,” said Nandan Nayampally, general manager, CPU Group, ARM. “By using a quad-core ARM Cortex-A53 configuration, with the Cortex-R5 fortifying the safety critical aspects, Dream Chip has produced a highly efficient and functionally safe processing solution that sets a high bar in the automotive vision sector. It underlines the rapidly increasingly deployment of ARM technology in vehicles; ranging from detection sensors to infotainment, ADAS and autonomous driving.”

“ADAS features are exhibiting the highest growth within the automotive electronics domain as vehicle makers look to differentiate on enhanced products that provide real-time vision processing,” said Rajeev Rajan, vice president of IoT and Automotive at GF. “GF’s 22FDX is an ideal platform to design power- and performance-efficient solutions for automotive vision and camera ADAS applications. As an industry first, this milestone affirms our commitment to support and collaboratively shape automotive markets.”

Dasaradha Gude, CEO of INVECAS said: “We are excited to contribute to this program as this collaboration further strengthens INVECAS’ position as a key provider of silicon proven IPs for GLOBALFOUNDRIES’ 22FDX technology. INVECAS’ rich family of IP offerings ranging from Foundation IP, Interface IP like Multiprotocol SerDes, DDR34/LPDDR34, MIPI, HDMI etc. enables complex SoC designs for the automotive market addressing the next wave of connected car opportunities in Europe. Our objective is to provide silicon-proven IP and ASIC solutions to address the challenges of ever growing design complexity faced by the semiconductor industry today.”

GLOBALFOUNDRIES today announced the availability of its 45nm RF SOI (45RFSOI) technology offering, making GF the first foundry to announce an advanced, 300mm RF silicon solution to support next generation millimeter-wave (mmWave) beam forming applications in future 5G base stations and smartphones.

GF’s 45RFSOI offering is the company’s most advanced RF SOI technology. The technology is optimized for beam forming front-end modules (FEMs), with back-end-of-line (BEOL) features including thick copper and dielectrics that enable improved RF performance for LNAs, switches and power amplifiers. The intrinsic characteristics of SOI combined with RF-centric features enable next-generation RF and mmWave applications, including internet broadband low earth orbit (LEO) satellites and 5G FEMs.

The fast emerging 5G and mmWave markets will require innovations in radio technologies, including low power, integrated mmWave radio front ends, antenna phased array subsystems, and high performance radio transceivers. As OEMs integrate more RF content into their smartphones and new high-speed network standards are introduced, state-of-the-art equipment will require additional RF circuitry to support newer modes of operation. This includes chips that support low latency, higher EIRP, and high resolution antenna scanning for ubiquitous coverage and continuous connectivity.

For improved power-handling benefits for devices operating in the GHz frequency range, 45RFSOI incorporates a substrate resistivity of greater than 40 ohm-cm that maximizes the quality factor for passive devices, reduces parasitic capacitances and minimizes disparity in phase and voltage swing. The technology supports operation in mmWave spectrum from 24GHz to 100GHz band, 5x more than 4G operating frequencies.

“Skyworks is pleased to be collaborating with GLOBALFOUNDRIES to drive innovation in millimeter wave solutions,” said Peter Gammel, chief technology officer for Skyworks Solutions, Inc. “GF’s leadership in advanced foundry technology, as exemplified by the 45RFSOI process, is enabling Skyworks to create RF solutions that will revolutionize emerging 5G markets and further advance the deployment of highly integrated RF front-ends for evolving mmWave applications.”

“5G is expected to become the dominant worldwide mobile communications standard of the next decade and will usher in a new paradigm in mobility, multi-GBps data rates, security, low latency, network availability and high quality of service (QoS),” said Bami Bastani, senior vice president of RF Business Unit at GLOBALFOUNDRIES. “Utilizing our long history of SOI leadership and high-volume manufacturing, we are excited to release our most advanced RF SOI technology that will help play a critical role in bringing 5G devices and networks to reality.”

GF’s 45RFSOI technology leverages a partially-depleted SOI technology base that has been in high-volume production since 2008. The advanced 45RFSOI technology is manufactured at the GF’s 300mm production line in East Fishkill, N.Y. and will provide the industry ample capacity to address this high growth market.

Process design kits are available now. Customers can now start optimizing their chip designs to develop differentiated solutions for customers seeking high performance in the RF front end of 5G and mmWave phased array applications.